Both the i.MX8M Mini and Nano have a video_pll which can be used
to source a clock which feeds the lcdif interface. This interface
currently fixes video_pll and divides down the clock feeding LCDIF.
However, when connected to an HDMI bridge chip that supports a
variety of video resolutions and refresh rates, the only settings
that properly sync are ones that evenly divide from the video_pll_out
clock.
This series adds the ability for the clk-compolsite-8m to
request a better parent clock rate if the proper clock flag is
enable and sets that flag in the corresponding imx8mm and
imx8mn video_pll clocks to increase the number of resolutions
and refresh rates timings that the LCDIF can produce.
This also has a side benefit of allowing the video-pll to run
at a lower clock speed which can potentially save some power
depending on the requested resolution and refresh rate.
v4: Sorry for the noise. I forgot to 'git ammend' so V4
is what V3 should have been.
V3: Change the name of clk_divider_determine_rate to
imx8m_clk_divider_determine_rate
V2: Split off the new imx8m_clk_hw_composite_flags definition
into its own patch and re-order to fix build error.
Adam Ford (3):
clk: imx: composite-8m: Add support to determine_rate
clk: imx8mm: Let IMX8MM_CLK_LCDIF_PIXEL set parent rate
clk: imx: Let IMX8MN_CLK_DISP_PIXEL set parent rate
drivers/clk/imx/clk-composite-8m.c | 7 +++++++
drivers/clk/imx/clk-imx8mm.c | 2 +-
drivers/clk/imx/clk-imx8mn.c | 2 +-
drivers/clk/imx/clk.h | 4 ++++
4 files changed, 13 insertions(+), 2 deletions(-)
--
2.34.1
Similar to imx/clk-composite-93 and imx/clk-divider-gate, the
imx8m_clk_composite_divider_ops can support determine_rate.
Without this the parent clocks are set to a fixed value, and
if a consumer needs a slower reate, the clock is divided, but
the division is only as good as the parent clock rate.
With this added, the system can attempt to adjust the parent rate
if the proper flags are set which can lead to a more precise clock
value.
Signed-off-by: Adam Ford <[email protected]>
Reviewed-by: Peng Fan <[email protected]>
Reviewed-by: Fabio Estevam <[email protected]>
---
V4: Sorry for the noise. I forgot to 'git ammend'
What V3 was supposed to be.
V3: Change name clk_divider_determine_rate to
imx8m_clk_divider_determine_rate to match naming convention
V2: No Change
diff --git a/drivers/clk/imx/clk-composite-8m.c b/drivers/clk/imx/clk-composite-8m.c
index cbf0d7955a00..6883a8199b6c 100644
--- a/drivers/clk/imx/clk-composite-8m.c
+++ b/drivers/clk/imx/clk-composite-8m.c
@@ -119,10 +119,17 @@ static int imx8m_clk_composite_divider_set_rate(struct clk_hw *hw,
return ret;
}
+static int imx8m_clk_divider_determine_rate(struct clk_hw *hw,
+ struct clk_rate_request *req)
+{
+ return clk_divider_ops.determine_rate(hw, req);
+}
+
static const struct clk_ops imx8m_clk_composite_divider_ops = {
.recalc_rate = imx8m_clk_composite_divider_recalc_rate,
.round_rate = imx8m_clk_composite_divider_round_rate,
.set_rate = imx8m_clk_composite_divider_set_rate,
+ .determine_rate = imx8m_clk_divider_determine_rate,
};
static u8 imx8m_clk_composite_mux_get_parent(struct clk_hw *hw)
--
2.34.1
By default the display pixel clock needs to be evenly divide
down from the video_pll_out clock which rules out a significant
number of resolution and refresh rates.
The current clock tree looks something like:
video_pll 594000000
video_pll_bypass 594000000
video_pll_out 594000000
disp_pixel 148500000
disp_pixel_clk 148500000
Now that composite-8m supports determine_rate, we can allow
disp_pixel to set the parent rate which then switches
every clock in the chain to a new frequency when disp_pixel
cannot evenly divide from video_pll_out.
Signed-off-by: Adam Ford <[email protected]>
Reviewed-by: Fabio Estevam <[email protected]>
diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c
index a042ed3a9d6c..4b23a4648600 100644
--- a/drivers/clk/imx/clk-imx8mn.c
+++ b/drivers/clk/imx/clk-imx8mn.c
@@ -470,7 +470,7 @@ static int imx8mn_clocks_probe(struct platform_device *pdev)
hws[IMX8MN_CLK_DRAM_ALT] = imx8m_clk_hw_fw_managed_composite("dram_alt", imx8mn_dram_alt_sels, base + 0xa000);
hws[IMX8MN_CLK_DRAM_APB] = imx8m_clk_hw_fw_managed_composite_critical("dram_apb", imx8mn_dram_apb_sels, base + 0xa080);
- hws[IMX8MN_CLK_DISP_PIXEL] = imx8m_clk_hw_composite("disp_pixel", imx8mn_disp_pixel_sels, base + 0xa500);
+ hws[IMX8MN_CLK_DISP_PIXEL] = imx8m_clk_hw_composite_flags("disp_pixel", imx8mn_disp_pixel_sels, base + 0xa500, CLK_SET_RATE_PARENT);
hws[IMX8MN_CLK_SAI2] = imx8m_clk_hw_composite("sai2", imx8mn_sai2_sels, base + 0xa600);
hws[IMX8MN_CLK_SAI3] = imx8m_clk_hw_composite("sai3", imx8mn_sai3_sels, base + 0xa680);
hws[IMX8MN_CLK_SAI5] = imx8m_clk_hw_composite("sai5", imx8mn_sai5_sels, base + 0xa780);
--
2.34.1
On 23-03-23 18:01:23, Adam Ford wrote:
> Both the i.MX8M Mini and Nano have a video_pll which can be used
> to source a clock which feeds the lcdif interface. This interface
> currently fixes video_pll and divides down the clock feeding LCDIF.
> However, when connected to an HDMI bridge chip that supports a
> variety of video resolutions and refresh rates, the only settings
> that properly sync are ones that evenly divide from the video_pll_out
> clock.
>
> This series adds the ability for the clk-compolsite-8m to
> request a better parent clock rate if the proper clock flag is
> enable and sets that flag in the corresponding imx8mm and
> imx8mn video_pll clocks to increase the number of resolutions
> and refresh rates timings that the LCDIF can produce.
>
> This also has a side benefit of allowing the video-pll to run
> at a lower clock speed which can potentially save some power
> depending on the requested resolution and refresh rate.
>
Applied, thanks!
[1/4] clk: imx: composite-8m: Add support to determine_rate
commit: 156e96ff2172518b6f83e97d8f11f677bc668e22
[2/4] clk: imx: Add imx8m_clk_hw_composite_flags macro
commit: 784a9b3916e949c00666588fd167c4ab245ec9d6
[3/4] clk: imx8mm: Let IMX8MM_CLK_LCDIF_PIXEL set parent rate
commit: 5fe6ec93f10b0765d59e0efb6ecba419a6a49d48
[4/4] clk: imx: Let IMX8MN_CLK_DISP_PIXEL set parent rate
commit: 46a974433ea7fa468b45db70536f7cea81feb87c
Best regards,
--
Abel Vesa <[email protected]>
> v4: Sorry for the noise. I forgot to 'git ammend' so V4
> is what V3 should have been.
> V3: Change the name of clk_divider_determine_rate to
> imx8m_clk_divider_determine_rate
> V2: Split off the new imx8m_clk_hw_composite_flags definition
> into its own patch and re-order to fix build error.
>
> Adam Ford (3):
> clk: imx: composite-8m: Add support to determine_rate
> clk: imx8mm: Let IMX8MM_CLK_LCDIF_PIXEL set parent rate
> clk: imx: Let IMX8MN_CLK_DISP_PIXEL set parent rate
>
> drivers/clk/imx/clk-composite-8m.c | 7 +++++++
> drivers/clk/imx/clk-imx8mm.c | 2 +-
> drivers/clk/imx/clk-imx8mn.c | 2 +-
> drivers/clk/imx/clk.h | 4 ++++
> 4 files changed, 13 insertions(+), 2 deletions(-)
>
> --
> 2.34.1
>