This series adds the support for QUP peripherals, PRNG, WDT for IPQ9574
SoC.
This series depends on the below one
https://lore.kernel.org/linux-arm-msm/[email protected]/
Kathiravan T (2):
dt-bindings: watchdog: qcom-wdt: add qcom,apss-wdt-ipq9574 compatible
arm64: dts: qcom: ipq9574: add few device nodes
.../bindings/watchdog/qcom-wdt.yaml | 1 +
arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts | 21 ++
arch/arm64/boot/dts/qcom/ipq9574.dtsi | 202 ++++++++++++++++++
3 files changed, 224 insertions(+)
--
2.17.1
Add a compatible for the IPQ9574 platform's APSS watchdog.
Signed-off-by: Kathiravan T <[email protected]>
---
Documentation/devicetree/bindings/watchdog/qcom-wdt.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/watchdog/qcom-wdt.yaml b/Documentation/devicetree/bindings/watchdog/qcom-wdt.yaml
index 6448b633c970..6910533aee50 100644
--- a/Documentation/devicetree/bindings/watchdog/qcom-wdt.yaml
+++ b/Documentation/devicetree/bindings/watchdog/qcom-wdt.yaml
@@ -18,6 +18,7 @@ properties:
- items:
- enum:
- qcom,kpss-wdt-ipq4019
+ - qcom,apss-wdt-ipq9574
- qcom,apss-wdt-msm8994
- qcom,apss-wdt-qcs404
- qcom,apss-wdt-sa8775p
--
2.17.1
Add QUP(SPI / I2C) peripheral, PRNG, WDOG and the remaining UART nodes.
While at it, enable the SPI NOR in RDP433 board.
Signed-off-by: Kathiravan T <[email protected]>
---
arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts | 21 ++
arch/arm64/boot/dts/qcom/ipq9574.dtsi | 202 ++++++++++++++++++++
2 files changed, 223 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts b/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts
index 2ce8e09e7565..7be578017bf7 100644
--- a/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts
+++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts
@@ -29,6 +29,20 @@
status = "okay";
};
+&blsp1_spi0 {
+ pinctrl-0 = <&spi_0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ flash@0 {
+ compatible = "micron,n25q128a11", "jedec,spi-nor";
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ spi-max-frequency = <50000000>;
+ };
+};
+
&sdhc_1 {
pinctrl-0 = <&sdc_default_state>;
pinctrl-names = "default";
@@ -77,6 +91,13 @@
bias-pull-down;
};
};
+
+ spi_0_pins: spi-0-state {
+ pins = "gpio11", "gpio12", "gpio13", "gpio14";
+ function = "blsp0_spi";
+ drive-strength = <8>;
+ bias-disable;
+ };
};
&xo_board_clk {
diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
index 14a3396b0381..f3da0190284c 100644
--- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
@@ -122,6 +122,13 @@
#size-cells = <1>;
ranges = <0 0 0 0xffffffff>;
+ rng: rng@e3000 {
+ compatible = "qcom,prng-ee";
+ reg = <0x000e3000 0x1000>;
+ clocks = <&gcc GCC_PRNG_AHB_CLK>;
+ clock-names = "core";
+ };
+
tlmm: pinctrl@1000000 {
compatible = "qcom,ipq9574-tlmm";
reg = <0x01000000 0x300000>;
@@ -184,6 +191,36 @@
status = "disabled";
};
+ blsp_dma: dma-controller@7884000 {
+ compatible = "qcom,bam-v1.7.0";
+ reg = <0x07884000 0x2b000>;
+ interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "bam_clk";
+ #dma-cells = <1>;
+ qcom,ee = <0>;
+ };
+
+ blsp1_uart0: serial@78af000 {
+ compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
+ reg = <0x078af000 0x200>;
+ interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
+ status = "disabled";
+ };
+
+ blsp1_uart1: serial@78b0000 {
+ compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
+ reg = <0x078b0000 0x200>;
+ interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
+ status = "disabled";
+ };
+
blsp1_uart2: serial@78b1000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0x078b1000 0x200>;
@@ -194,6 +231,163 @@
status = "disabled";
};
+ blsp1_uart3: serial@78b2000 {
+ compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
+ reg = <0x078b2000 0x200>;
+ interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_UART4_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
+ status = "disabled";
+ };
+
+ blsp1_uart4: serial@78b3000 {
+ compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
+ reg = <0x078b3000 0x200>;
+ interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_UART5_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
+ status = "disabled";
+ };
+
+ blsp1_uart5: serial@78b4000 {
+ compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
+ reg = <0x078b4000 0x200>;
+ interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_UART6_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
+ status = "disabled";
+ };
+
+ blsp1_spi0: spi@78b5000 {
+ compatible = "qcom,spi-qup-v2.2.1";
+ reg = <0x078b5000 0x600>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
+ dmas = <&blsp_dma 12>, <&blsp_dma 13>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ blsp1_i2c1: i2c@78b6000 {
+ compatible = "qcom,i2c-qup-v2.2.1";
+ reg = <0x078b6000 0x600>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
+ dmas = <&blsp_dma 14>, <&blsp_dma 15>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ blsp1_spi1: spi@78b6000 {
+ compatible = "qcom,spi-qup-v2.2.1";
+ reg = <0x078b6000 0x600>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
+ dmas = <&blsp_dma 14>, <&blsp_dma 15>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ blsp1_i2c2: i2c@78b7000 {
+ compatible = "qcom,i2c-qup-v2.2.1";
+ reg = <0x078b7000 0x600>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
+ dmas = <&blsp_dma 16>, <&blsp_dma 17>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ blsp1_spi2: spi@78b7000 {
+ compatible = "qcom,spi-qup-v2.2.1";
+ reg = <0x078b7000 0x600>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
+ dmas = <&blsp_dma 16>, <&blsp_dma 17>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ blsp1_i2c3: i2c@78b8000 {
+ compatible = "qcom,i2c-qup-v2.2.1";
+ reg = <0x078b8000 0x600>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
+ dmas = <&blsp_dma 18>, <&blsp_dma 19>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ blsp1_spi3: spi@78b8000 {
+ compatible = "qcom,spi-qup-v2.2.1";
+ reg = <0x078b8000 0x600>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
+ spi-max-frequency = <50000000>;
+ clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
+ dmas = <&blsp_dma 18>, <&blsp_dma 19>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ blsp1_i2c4: i2c@78b9000 {
+ compatible = "qcom,i2c-qup-v2.2.1";
+ reg = <0x078b9000 0x600>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
+ dmas = <&blsp_dma 20>, <&blsp_dma 21>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ blsp1_spi4: spi@78b9000 {
+ compatible = "qcom,spi-qup-v2.2.1";
+ reg = <0x078b9000 0x600>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
+ dmas = <&blsp_dma 20>, <&blsp_dma 21>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
intc: interrupt-controller@b000000 {
compatible = "qcom,msm-qgic2";
reg = <0x0b000000 0x1000>, /* GICD */
@@ -226,6 +420,14 @@
};
};
+ watchdog: watchdog@b017000 {
+ compatible = "qcom,apss-wdt-ipq9574", "qcom,kpss-wdt";
+ reg = <0x0b017000 0x1000>;
+ interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&sleep_clk>;
+ timeout-sec = <30>;
+ };
+
timer@b120000 {
compatible = "arm,armv7-timer-mem";
reg = <0x0b120000 0x1000>;
--
2.17.1
On 29/03/2023 07:37, Kathiravan T wrote:
> Add a compatible for the IPQ9574 platform's APSS watchdog.
>
> Signed-off-by: Kathiravan T <[email protected]>
> ---
> Documentation/devicetree/bindings/watchdog/qcom-wdt.yaml | 1 +
> 1 file changed, 1 insertion(+)
Acked-by: Krzysztof Kozlowski <[email protected]>
Best regards,
Krzysztof
On Wed, Mar 29, 2023 at 11:07:25AM +0530, Kathiravan T wrote:
> Add a compatible for the IPQ9574 platform's APSS watchdog.
>
> Signed-off-by: Kathiravan T <[email protected]>
Reviewed-by: Guenter Roeck <[email protected]>
> ---
> Documentation/devicetree/bindings/watchdog/qcom-wdt.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/watchdog/qcom-wdt.yaml b/Documentation/devicetree/bindings/watchdog/qcom-wdt.yaml
> index 6448b633c970..6910533aee50 100644
> --- a/Documentation/devicetree/bindings/watchdog/qcom-wdt.yaml
> +++ b/Documentation/devicetree/bindings/watchdog/qcom-wdt.yaml
> @@ -18,6 +18,7 @@ properties:
> - items:
> - enum:
> - qcom,kpss-wdt-ipq4019
> + - qcom,apss-wdt-ipq9574
> - qcom,apss-wdt-msm8994
> - qcom,apss-wdt-qcs404
> - qcom,apss-wdt-sa8775p
> --
> 2.17.1
>
On 3/29/2023 11:07 AM, Kathiravan T wrote:
> Add QUP(SPI / I2C) peripheral, PRNG, WDOG and the remaining UART nodes.
> While at it, enable the SPI NOR in RDP433 board.
>
> Signed-off-by: Kathiravan T <[email protected]>
> ---
> arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts | 21 ++
> arch/arm64/boot/dts/qcom/ipq9574.dtsi | 202 ++++++++++++++++++++
> 2 files changed, 223 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts b/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts
> index 2ce8e09e7565..7be578017bf7 100644
> --- a/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts
> +++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts
> @@ -29,6 +29,20 @@
> status = "okay";
> };
>
> +&blsp1_spi0 {
> + pinctrl-0 = <&spi_0_pins>;
> + pinctrl-names = "default";
> + status = "okay";
> +
> + flash@0 {
> + compatible = "micron,n25q128a11", "jedec,spi-nor";
> + reg = <0>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + spi-max-frequency = <50000000>;
> + };
> +};
> +
> &sdhc_1 {
> pinctrl-0 = <&sdc_default_state>;
> pinctrl-names = "default";
> @@ -77,6 +91,13 @@
> bias-pull-down;
> };
> };
> +
> + spi_0_pins: spi-0-state {
> + pins = "gpio11", "gpio12", "gpio13", "gpio14";
> + function = "blsp0_spi";
> + drive-strength = <8>;
> + bias-disable;
> + };
> };
>
> &xo_board_clk {
> diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
> index 14a3396b0381..f3da0190284c 100644
> --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
> +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
> @@ -122,6 +122,13 @@
> #size-cells = <1>;
> ranges = <0 0 0 0xffffffff>;
>
> + rng: rng@e3000 {
> + compatible = "qcom,prng-ee";
> + reg = <0x000e3000 0x1000>;
> + clocks = <&gcc GCC_PRNG_AHB_CLK>;
> + clock-names = "core";
> + };
> +
> tlmm: pinctrl@1000000 {
> compatible = "qcom,ipq9574-tlmm";
> reg = <0x01000000 0x300000>;
> @@ -184,6 +191,36 @@
> status = "disabled";
> };
>
> + blsp_dma: dma-controller@7884000 {
> + compatible = "qcom,bam-v1.7.0";
> + reg = <0x07884000 0x2b000>;
Does the size needs to be 0x2b000 really ?
Regards,
Sricharan
> + interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&gcc GCC_BLSP1_AHB_CLK>;
> + clock-names = "bam_clk";
> + #dma-cells = <1>;
> + qcom,ee = <0>;
> + };
> +
> + blsp1_uart0: serial@78af000 {
> + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
> + reg = <0x078af000 0x200>;
> + interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
> + <&gcc GCC_BLSP1_AHB_CLK>;
> + clock-names = "core", "iface";
> + status = "disabled";
> + };
> +
> + blsp1_uart1: serial@78b0000 {
> + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
> + reg = <0x078b0000 0x200>;
> + interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
> + <&gcc GCC_BLSP1_AHB_CLK>;
> + clock-names = "core", "iface";
> + status = "disabled";
> + };
> +
> blsp1_uart2: serial@78b1000 {
> compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
> reg = <0x078b1000 0x200>;
> @@ -194,6 +231,163 @@
> status = "disabled";
> };
>
> + blsp1_uart3: serial@78b2000 {
> + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
> + reg = <0x078b2000 0x200>;
> + interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&gcc GCC_BLSP1_UART4_APPS_CLK>,
> + <&gcc GCC_BLSP1_AHB_CLK>;
> + clock-names = "core", "iface";
> + status = "disabled";
> + };
> +
> + blsp1_uart4: serial@78b3000 {
> + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
> + reg = <0x078b3000 0x200>;
> + interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&gcc GCC_BLSP1_UART5_APPS_CLK>,
> + <&gcc GCC_BLSP1_AHB_CLK>;
> + clock-names = "core", "iface";
> + status = "disabled";
> + };
> +
> + blsp1_uart5: serial@78b4000 {
> + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
> + reg = <0x078b4000 0x200>;
> + interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&gcc GCC_BLSP1_UART6_APPS_CLK>,
> + <&gcc GCC_BLSP1_AHB_CLK>;
> + clock-names = "core", "iface";
> + status = "disabled";
> + };
> +
> + blsp1_spi0: spi@78b5000 {
> + compatible = "qcom,spi-qup-v2.2.1";
> + reg = <0x078b5000 0x600>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
> + <&gcc GCC_BLSP1_AHB_CLK>;
> + clock-names = "core", "iface";
> + dmas = <&blsp_dma 12>, <&blsp_dma 13>;
> + dma-names = "tx", "rx";
> + status = "disabled";
> + };
> +
> + blsp1_i2c1: i2c@78b6000 {
> + compatible = "qcom,i2c-qup-v2.2.1";
> + reg = <0x078b6000 0x600>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
> + <&gcc GCC_BLSP1_AHB_CLK>;
> + clock-names = "core", "iface";
> + dmas = <&blsp_dma 14>, <&blsp_dma 15>;
> + dma-names = "tx", "rx";
> + status = "disabled";
> + };
> +
> + blsp1_spi1: spi@78b6000 {
> + compatible = "qcom,spi-qup-v2.2.1";
> + reg = <0x078b6000 0x600>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
> + <&gcc GCC_BLSP1_AHB_CLK>;
> + clock-names = "core", "iface";
> + dmas = <&blsp_dma 14>, <&blsp_dma 15>;
> + dma-names = "tx", "rx";
> + status = "disabled";
> + };
> +
> + blsp1_i2c2: i2c@78b7000 {
> + compatible = "qcom,i2c-qup-v2.2.1";
> + reg = <0x078b7000 0x600>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
> + <&gcc GCC_BLSP1_AHB_CLK>;
> + clock-names = "core", "iface";
> + dmas = <&blsp_dma 16>, <&blsp_dma 17>;
> + dma-names = "tx", "rx";
> + status = "disabled";
> + };
> +
> + blsp1_spi2: spi@78b7000 {
> + compatible = "qcom,spi-qup-v2.2.1";
> + reg = <0x078b7000 0x600>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>,
> + <&gcc GCC_BLSP1_AHB_CLK>;
> + clock-names = "core", "iface";
> + dmas = <&blsp_dma 16>, <&blsp_dma 17>;
> + dma-names = "tx", "rx";
> + status = "disabled";
> + };
> +
> + blsp1_i2c3: i2c@78b8000 {
> + compatible = "qcom,i2c-qup-v2.2.1";
> + reg = <0x078b8000 0x600>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>,
> + <&gcc GCC_BLSP1_AHB_CLK>;
> + clock-names = "core", "iface";
> + dmas = <&blsp_dma 18>, <&blsp_dma 19>;
> + dma-names = "tx", "rx";
> + status = "disabled";
> + };
> +
> + blsp1_spi3: spi@78b8000 {
> + compatible = "qcom,spi-qup-v2.2.1";
> + reg = <0x078b8000 0x600>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
> + spi-max-frequency = <50000000>;
> + clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>,
> + <&gcc GCC_BLSP1_AHB_CLK>;
> + clock-names = "core", "iface";
> + dmas = <&blsp_dma 18>, <&blsp_dma 19>;
> + dma-names = "tx", "rx";
> + status = "disabled";
> + };
> +
> + blsp1_i2c4: i2c@78b9000 {
> + compatible = "qcom,i2c-qup-v2.2.1";
> + reg = <0x078b9000 0x600>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>,
> + <&gcc GCC_BLSP1_AHB_CLK>;
> + clock-names = "core", "iface";
> + dmas = <&blsp_dma 20>, <&blsp_dma 21>;
> + dma-names = "tx", "rx";
> + status = "disabled";
> + };
> +
> + blsp1_spi4: spi@78b9000 {
> + compatible = "qcom,spi-qup-v2.2.1";
> + reg = <0x078b9000 0x600>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>,
> + <&gcc GCC_BLSP1_AHB_CLK>;
> + clock-names = "core", "iface";
> + dmas = <&blsp_dma 20>, <&blsp_dma 21>;
> + dma-names = "tx", "rx";
> + status = "disabled";
> + };
> +
> intc: interrupt-controller@b000000 {
> compatible = "qcom,msm-qgic2";
> reg = <0x0b000000 0x1000>, /* GICD */
> @@ -226,6 +420,14 @@
> };
> };
>
> + watchdog: watchdog@b017000 {
> + compatible = "qcom,apss-wdt-ipq9574", "qcom,kpss-wdt";
> + reg = <0x0b017000 0x1000>;
> + interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>;
> + clocks = <&sleep_clk>;
> + timeout-sec = <30>;
> + };
> +
> timer@b120000 {
> compatible = "arm,armv7-timer-mem";
> reg = <0x0b120000 0x1000>;
On 3/31/2023 1:45 AM, Sricharan Ramabadhran wrote:
>
>
> On 3/29/2023 11:07 AM, Kathiravan T wrote:
>> Add QUP(SPI / I2C) peripheral, PRNG, WDOG and the remaining UART nodes.
>> While at it, enable the SPI NOR in RDP433 board.
>>
>> Signed-off-by: Kathiravan T <[email protected]>
>> ---
>> arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts | 21 ++
>> arch/arm64/boot/dts/qcom/ipq9574.dtsi | 202 ++++++++++++++++++++
>> 2 files changed, 223 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts
>> b/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts
>> index 2ce8e09e7565..7be578017bf7 100644
>> --- a/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts
>> +++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts
>> @@ -29,6 +29,20 @@
>> status = "okay";
>> };
>> +&blsp1_spi0 {
>> + pinctrl-0 = <&spi_0_pins>;
>> + pinctrl-names = "default";
>> + status = "okay";
>> +
>> + flash@0 {
>> + compatible = "micron,n25q128a11", "jedec,spi-nor";
>> + reg = <0>;
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + spi-max-frequency = <50000000>;
>> + };
>> +};
>> +
>> &sdhc_1 {
>> pinctrl-0 = <&sdc_default_state>;
>> pinctrl-names = "default";
>> @@ -77,6 +91,13 @@
>> bias-pull-down;
>> };
>> };
>> +
>> + spi_0_pins: spi-0-state {
>> + pins = "gpio11", "gpio12", "gpio13", "gpio14";
>> + function = "blsp0_spi";
>> + drive-strength = <8>;
>> + bias-disable;
>> + };
>> };
>> &xo_board_clk {
>> diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
>> b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
>> index 14a3396b0381..f3da0190284c 100644
>> --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
>> @@ -122,6 +122,13 @@
>> #size-cells = <1>;
>> ranges = <0 0 0 0xffffffff>;
>> + rng: rng@e3000 {
>> + compatible = "qcom,prng-ee";
>> + reg = <0x000e3000 0x1000>;
>> + clocks = <&gcc GCC_PRNG_AHB_CLK>;
>> + clock-names = "core";
>> + };
>> +
>> tlmm: pinctrl@1000000 {
>> compatible = "qcom,ipq9574-tlmm";
>> reg = <0x01000000 0x300000>;
>> @@ -184,6 +191,36 @@
>> status = "disabled";
>> };
>> + blsp_dma: dma-controller@7884000 {
>> + compatible = "qcom,bam-v1.7.0";
>> + reg = <0x07884000 0x2b000>;
>
> Does the size needs to be 0x2b000 really ?
As per the document, BLSP DMA block size is 0x2b000, however the last
register offset is 0x13934. In most of the places, irrespective of last
register offset, we covered the entire region as mentioned in the document.
Thanks, Kathiravan T.
>
> Regards,
> Sricharan
On Wed, 29 Mar 2023 11:07:24 +0530, Kathiravan T wrote:
> This series adds the support for QUP peripherals, PRNG, WDT for IPQ9574
> SoC.
>
> This series depends on the below one
> https://lore.kernel.org/linux-arm-msm/[email protected]/
>
> Kathiravan T (2):
> dt-bindings: watchdog: qcom-wdt: add qcom,apss-wdt-ipq9574 compatible
> arm64: dts: qcom: ipq9574: add few device nodes
>
> [...]
Applied, thanks!
[2/2] arm64: dts: qcom: ipq9574: add few device nodes
commit: 9ef42640504e09ecc79530b6e532ebf48305516b
Best regards,
--
Bjorn Andersson <[email protected]>