LinuxLists.cc - [PATCH] clk: qcom: gcc-qcm2290: Mark RCGs shared where applicable

2023-04-03 17:50:53

Subject: [PATCH] clk: qcom: gcc-qcm2290: Mark RCGs shared where applicable

The vast majority of shared RCGs were not marked as such. Fix it.

Fixes: 496d1a13d405 ("clk: qcom: Add Global Clock Controller driver for QCM2290")
Signed-off-by: Konrad Dybcio <[email protected]>
---
drivers/clk/qcom/gcc-qcm2290.c | 62 +++++++++++++++++-----------------
1 file changed, 31 insertions(+), 31 deletions(-)

diff --git a/drivers/clk/qcom/gcc-qcm2290.c b/drivers/clk/qcom/gcc-qcm2290.c
index 096deff2ba25..48995e50c6bd 100644
--- a/drivers/clk/qcom/gcc-qcm2290.c
+++ b/drivers/clk/qcom/gcc-qcm2290.c
@@ -650,7 +650,7 @@ static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = {
.name = "gcc_usb30_prim_mock_utmi_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
- .ops = &clk_rcg2_ops,
+ .ops = &clk_rcg2_shared_ops,
},
};

@@ -686,7 +686,7 @@ static struct clk_rcg2 gcc_camss_axi_clk_src = {
.name = "gcc_camss_axi_clk_src",
.parent_data = gcc_parents_4,
.num_parents = ARRAY_SIZE(gcc_parents_4),
- .ops = &clk_rcg2_ops,
+ .ops = &clk_rcg2_shared_ops,
},
};

@@ -706,7 +706,7 @@ static struct clk_rcg2 gcc_camss_cci_clk_src = {
.name = "gcc_camss_cci_clk_src",
.parent_data = gcc_parents_9,
.num_parents = ARRAY_SIZE(gcc_parents_9),
- .ops = &clk_rcg2_ops,
+ .ops = &clk_rcg2_shared_ops,
},
};

@@ -728,7 +728,7 @@ static struct clk_rcg2 gcc_camss_csi0phytimer_clk_src = {
.name = "gcc_camss_csi0phytimer_clk_src",
.parent_data = gcc_parents_5,
.num_parents = ARRAY_SIZE(gcc_parents_5),
- .ops = &clk_rcg2_ops,
+ .ops = &clk_rcg2_shared_ops,
},
};

@@ -742,7 +742,7 @@ static struct clk_rcg2 gcc_camss_csi1phytimer_clk_src = {
.name = "gcc_camss_csi1phytimer_clk_src",
.parent_data = gcc_parents_5,
.num_parents = ARRAY_SIZE(gcc_parents_5),
- .ops = &clk_rcg2_ops,
+ .ops = &clk_rcg2_shared_ops,
},
};

@@ -764,7 +764,7 @@ static struct clk_rcg2 gcc_camss_mclk0_clk_src = {
.parent_data = gcc_parents_3,
.num_parents = ARRAY_SIZE(gcc_parents_3),
.flags = CLK_OPS_PARENT_ENABLE,
- .ops = &clk_rcg2_ops,
+ .ops = &clk_rcg2_shared_ops,
},
};

@@ -779,7 +779,7 @@ static struct clk_rcg2 gcc_camss_mclk1_clk_src = {
.parent_data = gcc_parents_3,
.num_parents = ARRAY_SIZE(gcc_parents_3),
.flags = CLK_OPS_PARENT_ENABLE,
- .ops = &clk_rcg2_ops,
+ .ops = &clk_rcg2_shared_ops,
},
};

@@ -794,7 +794,7 @@ static struct clk_rcg2 gcc_camss_mclk2_clk_src = {
.parent_data = gcc_parents_3,
.num_parents = ARRAY_SIZE(gcc_parents_3),
.flags = CLK_OPS_PARENT_ENABLE,
- .ops = &clk_rcg2_ops,
+ .ops = &clk_rcg2_shared_ops,
},
};

@@ -809,7 +809,7 @@ static struct clk_rcg2 gcc_camss_mclk3_clk_src = {
.parent_data = gcc_parents_3,
.num_parents = ARRAY_SIZE(gcc_parents_3),
.flags = CLK_OPS_PARENT_ENABLE,
- .ops = &clk_rcg2_ops,
+ .ops = &clk_rcg2_shared_ops,
},
};

@@ -830,7 +830,7 @@ static struct clk_rcg2 gcc_camss_ope_ahb_clk_src = {
.name = "gcc_camss_ope_ahb_clk_src",
.parent_data = gcc_parents_6,
.num_parents = ARRAY_SIZE(gcc_parents_6),
- .ops = &clk_rcg2_ops,
+ .ops = &clk_rcg2_shared_ops,
},
};

@@ -854,7 +854,7 @@ static struct clk_rcg2 gcc_camss_ope_clk_src = {
.parent_data = gcc_parents_6,
.num_parents = ARRAY_SIZE(gcc_parents_6),
.flags = CLK_SET_RATE_PARENT,
- .ops = &clk_rcg2_ops,
+ .ops = &clk_rcg2_shared_ops,
},
};

@@ -888,7 +888,7 @@ static struct clk_rcg2 gcc_camss_tfe_0_clk_src = {
.name = "gcc_camss_tfe_0_clk_src",
.parent_data = gcc_parents_7,
.num_parents = ARRAY_SIZE(gcc_parents_7),
- .ops = &clk_rcg2_ops,
+ .ops = &clk_rcg2_shared_ops,
},
};

@@ -912,7 +912,7 @@ static struct clk_rcg2 gcc_camss_tfe_0_csid_clk_src = {
.name = "gcc_camss_tfe_0_csid_clk_src",
.parent_data = gcc_parents_8,
.num_parents = ARRAY_SIZE(gcc_parents_8),
- .ops = &clk_rcg2_ops,
+ .ops = &clk_rcg2_shared_ops,
},
};

@@ -926,7 +926,7 @@ static struct clk_rcg2 gcc_camss_tfe_1_clk_src = {
.name = "gcc_camss_tfe_1_clk_src",
.parent_data = gcc_parents_7,
.num_parents = ARRAY_SIZE(gcc_parents_7),
- .ops = &clk_rcg2_ops,
+ .ops = &clk_rcg2_shared_ops,
},
};

@@ -940,7 +940,7 @@ static struct clk_rcg2 gcc_camss_tfe_1_csid_clk_src = {
.name = "gcc_camss_tfe_1_csid_clk_src",
.parent_data = gcc_parents_8,
.num_parents = ARRAY_SIZE(gcc_parents_8),
- .ops = &clk_rcg2_ops,
+ .ops = &clk_rcg2_shared_ops,
},
};

@@ -963,7 +963,7 @@ static struct clk_rcg2 gcc_camss_tfe_cphy_rx_clk_src = {
.parent_data = gcc_parents_10,
.num_parents = ARRAY_SIZE(gcc_parents_10),
.flags = CLK_OPS_PARENT_ENABLE,
- .ops = &clk_rcg2_ops,
+ .ops = &clk_rcg2_shared_ops,
},
};

@@ -984,7 +984,7 @@ static struct clk_rcg2 gcc_camss_top_ahb_clk_src = {
.name = "gcc_camss_top_ahb_clk_src",
.parent_data = gcc_parents_4,
.num_parents = ARRAY_SIZE(gcc_parents_4),
- .ops = &clk_rcg2_ops,
+ .ops = &clk_rcg2_shared_ops,
},
};

@@ -1006,7 +1006,7 @@ static struct clk_rcg2 gcc_gp1_clk_src = {
.name = "gcc_gp1_clk_src",
.parent_data = gcc_parents_2,
.num_parents = ARRAY_SIZE(gcc_parents_2),
- .ops = &clk_rcg2_ops,
+ .ops = &clk_rcg2_shared_ops,
},
};

@@ -1020,7 +1020,7 @@ static struct clk_rcg2 gcc_gp2_clk_src = {
.name = "gcc_gp2_clk_src",
.parent_data = gcc_parents_2,
.num_parents = ARRAY_SIZE(gcc_parents_2),
- .ops = &clk_rcg2_ops,
+ .ops = &clk_rcg2_shared_ops,
},
};

@@ -1034,7 +1034,7 @@ static struct clk_rcg2 gcc_gp3_clk_src = {
.name = "gcc_gp3_clk_src",
.parent_data = gcc_parents_2,
.num_parents = ARRAY_SIZE(gcc_parents_2),
- .ops = &clk_rcg2_ops,
+ .ops = &clk_rcg2_shared_ops,
},
};

@@ -1054,7 +1054,7 @@ static struct clk_rcg2 gcc_pdm2_clk_src = {
.name = "gcc_pdm2_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
- .ops = &clk_rcg2_ops,
+ .ops = &clk_rcg2_shared_ops,
},
};

@@ -1082,7 +1082,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = {
.name = "gcc_qupv3_wrap0_s0_clk_src",
.parent_data = gcc_parents_1,
.num_parents = ARRAY_SIZE(gcc_parents_1),
- .ops = &clk_rcg2_ops,
+ .ops = &clk_rcg2_shared_ops,
};

static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = {
@@ -1098,7 +1098,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = {
.name = "gcc_qupv3_wrap0_s1_clk_src",
.parent_data = gcc_parents_1,
.num_parents = ARRAY_SIZE(gcc_parents_1),
- .ops = &clk_rcg2_ops,
+ .ops = &clk_rcg2_shared_ops,
};

static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = {
@@ -1114,7 +1114,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = {
.name = "gcc_qupv3_wrap0_s2_clk_src",
.parent_data = gcc_parents_1,
.num_parents = ARRAY_SIZE(gcc_parents_1),
- .ops = &clk_rcg2_ops,
+ .ops = &clk_rcg2_shared_ops,
};

static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = {
@@ -1130,7 +1130,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = {
.name = "gcc_qupv3_wrap0_s3_clk_src",
.parent_data = gcc_parents_1,
.num_parents = ARRAY_SIZE(gcc_parents_1),
- .ops = &clk_rcg2_ops,
+ .ops = &clk_rcg2_shared_ops,
};

static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = {
@@ -1146,7 +1146,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = {
.name = "gcc_qupv3_wrap0_s4_clk_src",
.parent_data = gcc_parents_1,
.num_parents = ARRAY_SIZE(gcc_parents_1),
- .ops = &clk_rcg2_ops,
+ .ops = &clk_rcg2_shared_ops,
};

static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {
@@ -1162,7 +1162,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = {
.name = "gcc_qupv3_wrap0_s5_clk_src",
.parent_data = gcc_parents_1,
.num_parents = ARRAY_SIZE(gcc_parents_1),
- .ops = &clk_rcg2_ops,
+ .ops = &clk_rcg2_shared_ops,
};

static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = {
@@ -1219,7 +1219,7 @@ static struct clk_rcg2 gcc_sdcc1_ice_core_clk_src = {
.name = "gcc_sdcc1_ice_core_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
- .ops = &clk_rcg2_ops,
+ .ops = &clk_rcg2_shared_ops,
},
};

@@ -1266,7 +1266,7 @@ static struct clk_rcg2 gcc_usb30_prim_master_clk_src = {
.name = "gcc_usb30_prim_master_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
- .ops = &clk_rcg2_ops,
+ .ops = &clk_rcg2_shared_ops,
},
};

@@ -1280,7 +1280,7 @@ static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = {
.name = "gcc_usb3_prim_phy_aux_clk_src",
.parent_data = gcc_parents_13,
.num_parents = ARRAY_SIZE(gcc_parents_13),
- .ops = &clk_rcg2_ops,
+ .ops = &clk_rcg2_shared_ops,
},
};

@@ -1303,7 +1303,7 @@ static struct clk_rcg2 gcc_video_venus_clk_src = {
.parent_data = gcc_parents_14,
.num_parents = ARRAY_SIZE(gcc_parents_14),
.flags = CLK_SET_RATE_PARENT,
- .ops = &clk_rcg2_ops,
+ .ops = &clk_rcg2_shared_ops,
},
};

--
2.40.0

2023-04-06 04:11:13

by Shawn Guo

[permalink] [raw]

Subject: Re: [PATCH] clk: qcom: gcc-qcm2290: Mark RCGs shared where applicable

On Mon, Apr 03, 2023 at 07:48:07PM +0200, Konrad Dybcio wrote:
> The vast majority of shared RCGs were not marked as such. Fix it.

It seems we completely missed this shared RCG thing, as vendor drivers
do not use it. Could you help me understand a couple of things?

- How does vendor driver handle shared RCGs?
- How did you find out these shared RCGs?

Shawn

>
> Fixes: 496d1a13d405 ("clk: qcom: Add Global Clock Controller driver for QCM2290")
> Signed-off-by: Konrad Dybcio <[email protected]>
> ---
> drivers/clk/qcom/gcc-qcm2290.c | 62 +++++++++++++++++-----------------
> 1 file changed, 31 insertions(+), 31 deletions(-)
>
> diff --git a/drivers/clk/qcom/gcc-qcm2290.c b/drivers/clk/qcom/gcc-qcm2290.c
> index 096deff2ba25..48995e50c6bd 100644
> --- a/drivers/clk/qcom/gcc-qcm2290.c
> +++ b/drivers/clk/qcom/gcc-qcm2290.c
> @@ -650,7 +650,7 @@ static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = {
> .name = "gcc_usb30_prim_mock_utmi_clk_src",
> .parent_data = gcc_parents_0,
> .num_parents = ARRAY_SIZE(gcc_parents_0),
> - .ops = &clk_rcg2_ops,
> + .ops = &clk_rcg2_shared_ops,
> },
> };
>
> @@ -686,7 +686,7 @@ static struct clk_rcg2 gcc_camss_axi_clk_src = {
> .name = "gcc_camss_axi_clk_src",
> .parent_data = gcc_parents_4,
> .num_parents = ARRAY_SIZE(gcc_parents_4),
> - .ops = &clk_rcg2_ops,
> + .ops = &clk_rcg2_shared_ops,
> },
> };
>
> @@ -706,7 +706,7 @@ static struct clk_rcg2 gcc_camss_cci_clk_src = {
> .name = "gcc_camss_cci_clk_src",
> .parent_data = gcc_parents_9,
> .num_parents = ARRAY_SIZE(gcc_parents_9),
> - .ops = &clk_rcg2_ops,
> + .ops = &clk_rcg2_shared_ops,
> },
> };
>
> @@ -728,7 +728,7 @@ static struct clk_rcg2 gcc_camss_csi0phytimer_clk_src = {
> .name = "gcc_camss_csi0phytimer_clk_src",
> .parent_data = gcc_parents_5,
> .num_parents = ARRAY_SIZE(gcc_parents_5),
> - .ops = &clk_rcg2_ops,
> + .ops = &clk_rcg2_shared_ops,
> },
> };
>
> @@ -742,7 +742,7 @@ static struct clk_rcg2 gcc_camss_csi1phytimer_clk_src = {
> .name = "gcc_camss_csi1phytimer_clk_src",
> .parent_data = gcc_parents_5,
> .num_parents = ARRAY_SIZE(gcc_parents_5),
> - .ops = &clk_rcg2_ops,
> + .ops = &clk_rcg2_shared_ops,
> },
> };
>
> @@ -764,7 +764,7 @@ static struct clk_rcg2 gcc_camss_mclk0_clk_src = {
> .parent_data = gcc_parents_3,
> .num_parents = ARRAY_SIZE(gcc_parents_3),
> .flags = CLK_OPS_PARENT_ENABLE,
> - .ops = &clk_rcg2_ops,
> + .ops = &clk_rcg2_shared_ops,
> },
> };
>
> @@ -779,7 +779,7 @@ static struct clk_rcg2 gcc_camss_mclk1_clk_src = {
> .parent_data = gcc_parents_3,
> .num_parents = ARRAY_SIZE(gcc_parents_3),
> .flags = CLK_OPS_PARENT_ENABLE,
> - .ops = &clk_rcg2_ops,
> + .ops = &clk_rcg2_shared_ops,
> },
> };
>
> @@ -794,7 +794,7 @@ static struct clk_rcg2 gcc_camss_mclk2_clk_src = {
> .parent_data = gcc_parents_3,
> .num_parents = ARRAY_SIZE(gcc_parents_3),
> .flags = CLK_OPS_PARENT_ENABLE,
> - .ops = &clk_rcg2_ops,
> + .ops = &clk_rcg2_shared_ops,
> },
> };
>
> @@ -809,7 +809,7 @@ static struct clk_rcg2 gcc_camss_mclk3_clk_src = {
> .parent_data = gcc_parents_3,
> .num_parents = ARRAY_SIZE(gcc_parents_3),
> .flags = CLK_OPS_PARENT_ENABLE,
> - .ops = &clk_rcg2_ops,
> + .ops = &clk_rcg2_shared_ops,
> },
> };
>
> @@ -830,7 +830,7 @@ static struct clk_rcg2 gcc_camss_ope_ahb_clk_src = {
> .name = "gcc_camss_ope_ahb_clk_src",
> .parent_data = gcc_parents_6,
> .num_parents = ARRAY_SIZE(gcc_parents_6),
> - .ops = &clk_rcg2_ops,
> + .ops = &clk_rcg2_shared_ops,
> },
> };
>
> @@ -854,7 +854,7 @@ static struct clk_rcg2 gcc_camss_ope_clk_src = {
> .parent_data = gcc_parents_6,
> .num_parents = ARRAY_SIZE(gcc_parents_6),
> .flags = CLK_SET_RATE_PARENT,
> - .ops = &clk_rcg2_ops,
> + .ops = &clk_rcg2_shared_ops,
> },
> };
>
> @@ -888,7 +888,7 @@ static struct clk_rcg2 gcc_camss_tfe_0_clk_src = {
> .name = "gcc_camss_tfe_0_clk_src",
> .parent_data = gcc_parents_7,
> .num_parents = ARRAY_SIZE(gcc_parents_7),
> - .ops = &clk_rcg2_ops,
> + .ops = &clk_rcg2_shared_ops,
> },
> };
>
> @@ -912,7 +912,7 @@ static struct clk_rcg2 gcc_camss_tfe_0_csid_clk_src = {
> .name = "gcc_camss_tfe_0_csid_clk_src",
> .parent_data = gcc_parents_8,
> .num_parents = ARRAY_SIZE(gcc_parents_8),
> - .ops = &clk_rcg2_ops,
> + .ops = &clk_rcg2_shared_ops,
> },
> };
>
> @@ -926,7 +926,7 @@ static struct clk_rcg2 gcc_camss_tfe_1_clk_src = {
> .name = "gcc_camss_tfe_1_clk_src",
> .parent_data = gcc_parents_7,
> .num_parents = ARRAY_SIZE(gcc_parents_7),
> - .ops = &clk_rcg2_ops,
> + .ops = &clk_rcg2_shared_ops,
> },
> };
>
> @@ -940,7 +940,7 @@ static struct clk_rcg2 gcc_camss_tfe_1_csid_clk_src = {
> .name = "gcc_camss_tfe_1_csid_clk_src",
> .parent_data = gcc_parents_8,
> .num_parents = ARRAY_SIZE(gcc_parents_8),
> - .ops = &clk_rcg2_ops,
> + .ops = &clk_rcg2_shared_ops,
> },
> };
>
> @@ -963,7 +963,7 @@ static struct clk_rcg2 gcc_camss_tfe_cphy_rx_clk_src = {
> .parent_data = gcc_parents_10,
> .num_parents = ARRAY_SIZE(gcc_parents_10),
> .flags = CLK_OPS_PARENT_ENABLE,
> - .ops = &clk_rcg2_ops,
> + .ops = &clk_rcg2_shared_ops,
> },
> };
>
> @@ -984,7 +984,7 @@ static struct clk_rcg2 gcc_camss_top_ahb_clk_src = {
> .name = "gcc_camss_top_ahb_clk_src",
> .parent_data = gcc_parents_4,
> .num_parents = ARRAY_SIZE(gcc_parents_4),
> - .ops = &clk_rcg2_ops,
> + .ops = &clk_rcg2_shared_ops,
> },
> };
>
> @@ -1006,7 +1006,7 @@ static struct clk_rcg2 gcc_gp1_clk_src = {
> .name = "gcc_gp1_clk_src",
> .parent_data = gcc_parents_2,
> .num_parents = ARRAY_SIZE(gcc_parents_2),
> - .ops = &clk_rcg2_ops,
> + .ops = &clk_rcg2_shared_ops,
> },
> };
>
> @@ -1020,7 +1020,7 @@ static struct clk_rcg2 gcc_gp2_clk_src = {
> .name = "gcc_gp2_clk_src",
> .parent_data = gcc_parents_2,
> .num_parents = ARRAY_SIZE(gcc_parents_2),
> - .ops = &clk_rcg2_ops,
> + .ops = &clk_rcg2_shared_ops,
> },
> };
>
> @@ -1034,7 +1034,7 @@ static struct clk_rcg2 gcc_gp3_clk_src = {
> .name = "gcc_gp3_clk_src",
> .parent_data = gcc_parents_2,
> .num_parents = ARRAY_SIZE(gcc_parents_2),
> - .ops = &clk_rcg2_ops,
> + .ops = &clk_rcg2_shared_ops,
> },
> };
>
> @@ -1054,7 +1054,7 @@ static struct clk_rcg2 gcc_pdm2_clk_src = {
> .name = "gcc_pdm2_clk_src",
> .parent_data = gcc_parents_0,
> .num_parents = ARRAY_SIZE(gcc_parents_0),
> - .ops = &clk_rcg2_ops,
> + .ops = &clk_rcg2_shared_ops,
> },
> };
>
> @@ -1082,7 +1082,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = {
> .name = "gcc_qupv3_wrap0_s0_clk_src",
> .parent_data = gcc_parents_1,
> .num_parents = ARRAY_SIZE(gcc_parents_1),
> - .ops = &clk_rcg2_ops,
> + .ops = &clk_rcg2_shared_ops,
> };
>
> static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = {
> @@ -1098,7 +1098,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = {
> .name = "gcc_qupv3_wrap0_s1_clk_src",
> .parent_data = gcc_parents_1,
> .num_parents = ARRAY_SIZE(gcc_parents_1),
> - .ops = &clk_rcg2_ops,
> + .ops = &clk_rcg2_shared_ops,
> };
>
> static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = {
> @@ -1114,7 +1114,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = {
> .name = "gcc_qupv3_wrap0_s2_clk_src",
> .parent_data = gcc_parents_1,
> .num_parents = ARRAY_SIZE(gcc_parents_1),
> - .ops = &clk_rcg2_ops,
> + .ops = &clk_rcg2_shared_ops,
> };
>
> static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = {
> @@ -1130,7 +1130,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = {
> .name = "gcc_qupv3_wrap0_s3_clk_src",
> .parent_data = gcc_parents_1,
> .num_parents = ARRAY_SIZE(gcc_parents_1),
> - .ops = &clk_rcg2_ops,
> + .ops = &clk_rcg2_shared_ops,
> };
>
> static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = {
> @@ -1146,7 +1146,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = {
> .name = "gcc_qupv3_wrap0_s4_clk_src",
> .parent_data = gcc_parents_1,
> .num_parents = ARRAY_SIZE(gcc_parents_1),
> - .ops = &clk_rcg2_ops,
> + .ops = &clk_rcg2_shared_ops,
> };
>
> static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {
> @@ -1162,7 +1162,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = {
> .name = "gcc_qupv3_wrap0_s5_clk_src",
> .parent_data = gcc_parents_1,
> .num_parents = ARRAY_SIZE(gcc_parents_1),
> - .ops = &clk_rcg2_ops,
> + .ops = &clk_rcg2_shared_ops,
> };
>
> static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = {
> @@ -1219,7 +1219,7 @@ static struct clk_rcg2 gcc_sdcc1_ice_core_clk_src = {
> .name = "gcc_sdcc1_ice_core_clk_src",
> .parent_data = gcc_parents_0,
> .num_parents = ARRAY_SIZE(gcc_parents_0),
> - .ops = &clk_rcg2_ops,
> + .ops = &clk_rcg2_shared_ops,
> },
> };
>
> @@ -1266,7 +1266,7 @@ static struct clk_rcg2 gcc_usb30_prim_master_clk_src = {
> .name = "gcc_usb30_prim_master_clk_src",
> .parent_data = gcc_parents_0,
> .num_parents = ARRAY_SIZE(gcc_parents_0),
> - .ops = &clk_rcg2_ops,
> + .ops = &clk_rcg2_shared_ops,
> },
> };
>
> @@ -1280,7 +1280,7 @@ static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = {
> .name = "gcc_usb3_prim_phy_aux_clk_src",
> .parent_data = gcc_parents_13,
> .num_parents = ARRAY_SIZE(gcc_parents_13),
> - .ops = &clk_rcg2_ops,
> + .ops = &clk_rcg2_shared_ops,
> },
> };
>
> @@ -1303,7 +1303,7 @@ static struct clk_rcg2 gcc_video_venus_clk_src = {
> .parent_data = gcc_parents_14,
> .num_parents = ARRAY_SIZE(gcc_parents_14),
> .flags = CLK_SET_RATE_PARENT,
> - .ops = &clk_rcg2_ops,
> + .ops = &clk_rcg2_shared_ops,
> },
> };
>
> --
> 2.40.0
>

2023-04-06 11:31:17

by Konrad Dybcio

[permalink] [raw]

Subject: Re: [PATCH] clk: qcom: gcc-qcm2290: Mark RCGs shared where applicable

On 6.04.2023 06:04, Shawn Guo wrote:
> On Mon, Apr 03, 2023 at 07:48:07PM +0200, Konrad Dybcio wrote:
>> The vast majority of shared RCGs were not marked as such. Fix it.
>
> It seems we completely missed this shared RCG thing, as vendor drivers
> do not use it. Could you help me understand a couple of things?
>
> - How does vendor driver handle shared RCGs?
See paths with enable_safe_config in e.g.

https://git.codelinaro.org/clo/la/kernel/msm-5.4/-/blob/66f3180d36f49f9bf6c1a6712acbb0c75f6ff516/drivers/clk/qcom/clk-rcg2.c

> - How did you find out these shared RCGs?
I was debugging another issue and noticed (by eye) this was missing.

Konrad
>
> Shawn
>
>>
>> Fixes: 496d1a13d405 ("clk: qcom: Add Global Clock Controller driver for QCM2290")
>> Signed-off-by: Konrad Dybcio <[email protected]>
>> ---
>> drivers/clk/qcom/gcc-qcm2290.c | 62 +++++++++++++++++-----------------
>> 1 file changed, 31 insertions(+), 31 deletions(-)
>>
>> diff --git a/drivers/clk/qcom/gcc-qcm2290.c b/drivers/clk/qcom/gcc-qcm2290.c
>> index 096deff2ba25..48995e50c6bd 100644
>> --- a/drivers/clk/qcom/gcc-qcm2290.c
>> +++ b/drivers/clk/qcom/gcc-qcm2290.c
>> @@ -650,7 +650,7 @@ static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = {
>> .name = "gcc_usb30_prim_mock_utmi_clk_src",
>> .parent_data = gcc_parents_0,
>> .num_parents = ARRAY_SIZE(gcc_parents_0),
>> - .ops = &clk_rcg2_ops,
>> + .ops = &clk_rcg2_shared_ops,
>> },
>> };
>>
>> @@ -686,7 +686,7 @@ static struct clk_rcg2 gcc_camss_axi_clk_src = {
>> .name = "gcc_camss_axi_clk_src",
>> .parent_data = gcc_parents_4,
>> .num_parents = ARRAY_SIZE(gcc_parents_4),
>> - .ops = &clk_rcg2_ops,
>> + .ops = &clk_rcg2_shared_ops,
>> },
>> };
>>
>> @@ -706,7 +706,7 @@ static struct clk_rcg2 gcc_camss_cci_clk_src = {
>> .name = "gcc_camss_cci_clk_src",
>> .parent_data = gcc_parents_9,
>> .num_parents = ARRAY_SIZE(gcc_parents_9),
>> - .ops = &clk_rcg2_ops,
>> + .ops = &clk_rcg2_shared_ops,
>> },
>> };
>>
>> @@ -728,7 +728,7 @@ static struct clk_rcg2 gcc_camss_csi0phytimer_clk_src = {
>> .name = "gcc_camss_csi0phytimer_clk_src",
>> .parent_data = gcc_parents_5,
>> .num_parents = ARRAY_SIZE(gcc_parents_5),
>> - .ops = &clk_rcg2_ops,
>> + .ops = &clk_rcg2_shared_ops,
>> },
>> };
>>
>> @@ -742,7 +742,7 @@ static struct clk_rcg2 gcc_camss_csi1phytimer_clk_src = {
>> .name = "gcc_camss_csi1phytimer_clk_src",
>> .parent_data = gcc_parents_5,
>> .num_parents = ARRAY_SIZE(gcc_parents_5),
>> - .ops = &clk_rcg2_ops,
>> + .ops = &clk_rcg2_shared_ops,
>> },
>> };
>>
>> @@ -764,7 +764,7 @@ static struct clk_rcg2 gcc_camss_mclk0_clk_src = {
>> .parent_data = gcc_parents_3,
>> .num_parents = ARRAY_SIZE(gcc_parents_3),
>> .flags = CLK_OPS_PARENT_ENABLE,
>> - .ops = &clk_rcg2_ops,
>> + .ops = &clk_rcg2_shared_ops,
>> },
>> };
>>
>> @@ -779,7 +779,7 @@ static struct clk_rcg2 gcc_camss_mclk1_clk_src = {
>> .parent_data = gcc_parents_3,
>> .num_parents = ARRAY_SIZE(gcc_parents_3),
>> .flags = CLK_OPS_PARENT_ENABLE,
>> - .ops = &clk_rcg2_ops,
>> + .ops = &clk_rcg2_shared_ops,
>> },
>> };
>>
>> @@ -794,7 +794,7 @@ static struct clk_rcg2 gcc_camss_mclk2_clk_src = {
>> .parent_data = gcc_parents_3,
>> .num_parents = ARRAY_SIZE(gcc_parents_3),
>> .flags = CLK_OPS_PARENT_ENABLE,
>> - .ops = &clk_rcg2_ops,
>> + .ops = &clk_rcg2_shared_ops,
>> },
>> };
>>
>> @@ -809,7 +809,7 @@ static struct clk_rcg2 gcc_camss_mclk3_clk_src = {
>> .parent_data = gcc_parents_3,
>> .num_parents = ARRAY_SIZE(gcc_parents_3),
>> .flags = CLK_OPS_PARENT_ENABLE,
>> - .ops = &clk_rcg2_ops,
>> + .ops = &clk_rcg2_shared_ops,
>> },
>> };
>>
>> @@ -830,7 +830,7 @@ static struct clk_rcg2 gcc_camss_ope_ahb_clk_src = {
>> .name = "gcc_camss_ope_ahb_clk_src",
>> .parent_data = gcc_parents_6,
>> .num_parents = ARRAY_SIZE(gcc_parents_6),
>> - .ops = &clk_rcg2_ops,
>> + .ops = &clk_rcg2_shared_ops,
>> },
>> };
>>
>> @@ -854,7 +854,7 @@ static struct clk_rcg2 gcc_camss_ope_clk_src = {
>> .parent_data = gcc_parents_6,
>> .num_parents = ARRAY_SIZE(gcc_parents_6),
>> .flags = CLK_SET_RATE_PARENT,
>> - .ops = &clk_rcg2_ops,
>> + .ops = &clk_rcg2_shared_ops,
>> },
>> };
>>
>> @@ -888,7 +888,7 @@ static struct clk_rcg2 gcc_camss_tfe_0_clk_src = {
>> .name = "gcc_camss_tfe_0_clk_src",
>> .parent_data = gcc_parents_7,
>> .num_parents = ARRAY_SIZE(gcc_parents_7),
>> - .ops = &clk_rcg2_ops,
>> + .ops = &clk_rcg2_shared_ops,
>> },
>> };
>>
>> @@ -912,7 +912,7 @@ static struct clk_rcg2 gcc_camss_tfe_0_csid_clk_src = {
>> .name = "gcc_camss_tfe_0_csid_clk_src",
>> .parent_data = gcc_parents_8,
>> .num_parents = ARRAY_SIZE(gcc_parents_8),
>> - .ops = &clk_rcg2_ops,
>> + .ops = &clk_rcg2_shared_ops,
>> },
>> };
>>
>> @@ -926,7 +926,7 @@ static struct clk_rcg2 gcc_camss_tfe_1_clk_src = {
>> .name = "gcc_camss_tfe_1_clk_src",
>> .parent_data = gcc_parents_7,
>> .num_parents = ARRAY_SIZE(gcc_parents_7),
>> - .ops = &clk_rcg2_ops,
>> + .ops = &clk_rcg2_shared_ops,
>> },
>> };
>>
>> @@ -940,7 +940,7 @@ static struct clk_rcg2 gcc_camss_tfe_1_csid_clk_src = {
>> .name = "gcc_camss_tfe_1_csid_clk_src",
>> .parent_data = gcc_parents_8,
>> .num_parents = ARRAY_SIZE(gcc_parents_8),
>> - .ops = &clk_rcg2_ops,
>> + .ops = &clk_rcg2_shared_ops,
>> },
>> };
>>
>> @@ -963,7 +963,7 @@ static struct clk_rcg2 gcc_camss_tfe_cphy_rx_clk_src = {
>> .parent_data = gcc_parents_10,
>> .num_parents = ARRAY_SIZE(gcc_parents_10),
>> .flags = CLK_OPS_PARENT_ENABLE,
>> - .ops = &clk_rcg2_ops,
>> + .ops = &clk_rcg2_shared_ops,
>> },
>> };
>>
>> @@ -984,7 +984,7 @@ static struct clk_rcg2 gcc_camss_top_ahb_clk_src = {
>> .name = "gcc_camss_top_ahb_clk_src",
>> .parent_data = gcc_parents_4,
>> .num_parents = ARRAY_SIZE(gcc_parents_4),
>> - .ops = &clk_rcg2_ops,
>> + .ops = &clk_rcg2_shared_ops,
>> },
>> };
>>
>> @@ -1006,7 +1006,7 @@ static struct clk_rcg2 gcc_gp1_clk_src = {
>> .name = "gcc_gp1_clk_src",
>> .parent_data = gcc_parents_2,
>> .num_parents = ARRAY_SIZE(gcc_parents_2),
>> - .ops = &clk_rcg2_ops,
>> + .ops = &clk_rcg2_shared_ops,
>> },
>> };
>>
>> @@ -1020,7 +1020,7 @@ static struct clk_rcg2 gcc_gp2_clk_src = {
>> .name = "gcc_gp2_clk_src",
>> .parent_data = gcc_parents_2,
>> .num_parents = ARRAY_SIZE(gcc_parents_2),
>> - .ops = &clk_rcg2_ops,
>> + .ops = &clk_rcg2_shared_ops,
>> },
>> };
>>
>> @@ -1034,7 +1034,7 @@ static struct clk_rcg2 gcc_gp3_clk_src = {
>> .name = "gcc_gp3_clk_src",
>> .parent_data = gcc_parents_2,
>> .num_parents = ARRAY_SIZE(gcc_parents_2),
>> - .ops = &clk_rcg2_ops,
>> + .ops = &clk_rcg2_shared_ops,
>> },
>> };
>>
>> @@ -1054,7 +1054,7 @@ static struct clk_rcg2 gcc_pdm2_clk_src = {
>> .name = "gcc_pdm2_clk_src",
>> .parent_data = gcc_parents_0,
>> .num_parents = ARRAY_SIZE(gcc_parents_0),
>> - .ops = &clk_rcg2_ops,
>> + .ops = &clk_rcg2_shared_ops,
>> },
>> };
>>
>> @@ -1082,7 +1082,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = {
>> .name = "gcc_qupv3_wrap0_s0_clk_src",
>> .parent_data = gcc_parents_1,
>> .num_parents = ARRAY_SIZE(gcc_parents_1),
>> - .ops = &clk_rcg2_ops,
>> + .ops = &clk_rcg2_shared_ops,
>> };
>>
>> static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = {
>> @@ -1098,7 +1098,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = {
>> .name = "gcc_qupv3_wrap0_s1_clk_src",
>> .parent_data = gcc_parents_1,
>> .num_parents = ARRAY_SIZE(gcc_parents_1),
>> - .ops = &clk_rcg2_ops,
>> + .ops = &clk_rcg2_shared_ops,
>> };
>>
>> static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = {
>> @@ -1114,7 +1114,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = {
>> .name = "gcc_qupv3_wrap0_s2_clk_src",
>> .parent_data = gcc_parents_1,
>> .num_parents = ARRAY_SIZE(gcc_parents_1),
>> - .ops = &clk_rcg2_ops,
>> + .ops = &clk_rcg2_shared_ops,
>> };
>>
>> static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = {
>> @@ -1130,7 +1130,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = {
>> .name = "gcc_qupv3_wrap0_s3_clk_src",
>> .parent_data = gcc_parents_1,
>> .num_parents = ARRAY_SIZE(gcc_parents_1),
>> - .ops = &clk_rcg2_ops,
>> + .ops = &clk_rcg2_shared_ops,
>> };
>>
>> static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = {
>> @@ -1146,7 +1146,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = {
>> .name = "gcc_qupv3_wrap0_s4_clk_src",
>> .parent_data = gcc_parents_1,
>> .num_parents = ARRAY_SIZE(gcc_parents_1),
>> - .ops = &clk_rcg2_ops,
>> + .ops = &clk_rcg2_shared_ops,
>> };
>>
>> static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {
>> @@ -1162,7 +1162,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = {
>> .name = "gcc_qupv3_wrap0_s5_clk_src",
>> .parent_data = gcc_parents_1,
>> .num_parents = ARRAY_SIZE(gcc_parents_1),
>> - .ops = &clk_rcg2_ops,
>> + .ops = &clk_rcg2_shared_ops,
>> };
>>
>> static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = {
>> @@ -1219,7 +1219,7 @@ static struct clk_rcg2 gcc_sdcc1_ice_core_clk_src = {
>> .name = "gcc_sdcc1_ice_core_clk_src",
>> .parent_data = gcc_parents_0,
>> .num_parents = ARRAY_SIZE(gcc_parents_0),
>> - .ops = &clk_rcg2_ops,
>> + .ops = &clk_rcg2_shared_ops,
>> },
>> };
>>
>> @@ -1266,7 +1266,7 @@ static struct clk_rcg2 gcc_usb30_prim_master_clk_src = {
>> .name = "gcc_usb30_prim_master_clk_src",
>> .parent_data = gcc_parents_0,
>> .num_parents = ARRAY_SIZE(gcc_parents_0),
>> - .ops = &clk_rcg2_ops,
>> + .ops = &clk_rcg2_shared_ops,
>> },
>> };
>>
>> @@ -1280,7 +1280,7 @@ static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = {
>> .name = "gcc_usb3_prim_phy_aux_clk_src",
>> .parent_data = gcc_parents_13,
>> .num_parents = ARRAY_SIZE(gcc_parents_13),
>> - .ops = &clk_rcg2_ops,
>> + .ops = &clk_rcg2_shared_ops,
>> },
>> };
>>
>> @@ -1303,7 +1303,7 @@ static struct clk_rcg2 gcc_video_venus_clk_src = {
>> .parent_data = gcc_parents_14,
>> .num_parents = ARRAY_SIZE(gcc_parents_14),
>> .flags = CLK_SET_RATE_PARENT,
>> - .ops = &clk_rcg2_ops,
>> + .ops = &clk_rcg2_shared_ops,
>> },
>> };
>>
>> --
>> 2.40.0
>>

2023-04-06 11:33:55

by Shawn Guo

[permalink] [raw]

Subject: Re: [PATCH] clk: qcom: gcc-qcm2290: Mark RCGs shared where applicable

On Thu, Apr 06, 2023 at 01:18:44PM +0200, Konrad Dybcio wrote:
>
>
> On 6.04.2023 06:04, Shawn Guo wrote:
> > On Mon, Apr 03, 2023 at 07:48:07PM +0200, Konrad Dybcio wrote:
> >> The vast majority of shared RCGs were not marked as such. Fix it.
> >
> > It seems we completely missed this shared RCG thing, as vendor drivers
> > do not use it. Could you help me understand a couple of things?
> >
> > - How does vendor driver handle shared RCGs?
> See paths with enable_safe_config in e.g.
>
> https://git.codelinaro.org/clo/la/kernel/msm-5.4/-/blob/66f3180d36f49f9bf6c1a6712acbb0c75f6ff516/drivers/clk/qcom/clk-rcg2.c

Thanks, Konrad!

For the patch:

Acked-by: Shawn Guo <[email protected]>

2023-05-25 04:54:55

by Bjorn Andersson

[permalink] [raw]

Subject: Re: [PATCH] clk: qcom: gcc-qcm2290: Mark RCGs shared where applicable

On Mon, 3 Apr 2023 19:48:07 +0200, Konrad Dybcio wrote:
> The vast majority of shared RCGs were not marked as such. Fix it.
>
>

Applied, thanks!

[1/1] clk: qcom: gcc-qcm2290: Mark RCGs shared where applicable
commit: 7bf654a0d95e75b415f454e10627309d650762d0

Best regards,
--
Bjorn Andersson <[email protected]>