This series enables support for AMD Pensando Elba SoC based platforms.
The Elba SoC has the following features:
- Sixteen ARM64 A72 cores
- Dual DDR 4/5 memory controllers
- 32 lanes of PCIe Gen3/4 to the Host
- Network interfaces: Dual 200GE, Quad 100GE, 50GE, 25GE, 10GE and
also a single 1GE management port.
- Storage/crypto offloads and 144 programmable P4 cores.
- QSPI and EMMC for SoC storage
- Two SPI interfaces for peripheral management
- I2C bus for platform management
== V13 changes ==
v13-0013-mmc-sdhci-cadence-Add-AMD-Pensando-Elba-SoC-supp
- Use GENMASK(7, 3) in elba_priv_writel() to set all byte enables
- Add a variable 'shift' with GENMASK(1, 0) in elba_write_w() and
elba_write_b() to set the byte enable variable.
v13-0015-soc-amd-Add-support-for-AMD-Pensando-SoC-Control
- Update include list in pensando-ctrl.c
- Change variable spi_dev to spi throughout
- Removed unneeded variable initialization, simplification of
error checks, remove extra castings, and use dev_err_probe()
- Sort the includes in amd-pensando-ctrl.h
- Updates to cleanup if there is an error in penctrl_spi_probe()
== V12 changes ==
v12-0004-dt-bindings-spi-dw-Add-AMD-Pensando-Elba-SoC-SPI
- Correct property amd,pensando-elba-syscon description
v12-0010-spi-dw-Add-support-for-AMD-Pensando-Elba-SoC
- Add a newline in function dw_spi_elba_init()
v12-0015-soc-amd-Add-support-for-AMD-Pensando-SoC-Control
- Fix gcc-12.1.0 warning:
== V11 changes ==
v11-0002-dt-bindings-mmc-cdns-Add-AMD-Pensando-Elba-SoC
- Remove resets description and reset-names
- Add descriptions for amd,pensando-elba-sd4hc reg items
v11-0003-dt-bindings-spi-cdns-Add-compatible-for-AMD-Pens
- Removed redundant if/then for amd,pensando-elba-qspi
v11-0005-dt-bindings-soc-amd-amd-pensando-elba-ctrl-Add-P
- Fixed the compatible which should have stayed as
'amd,pensando-elba-ctrl', the commit message, and the filename.
- Reference spi-peripheral-props
- Delete spi-max-frequency
- Remove num-cs from example
v11-0008-arm64-dts-Add-AMD-Pensando-Elba-SoC-support
- Delete reset-names
- Fix spi0 compatible to be specific 'amd,pensando-elba-ctrl'
v11-0010-spi-dw-Add-support-for-AMD-Pensando-Elba-SoC
- Simplify dw_spi_elb_init by using syscon_regmap_lookup_by_phandle()
v11-0013-mmc-sdhci-cadence-Add-AMD-Pensando-Elba-SoC-supp
- Remove elba-drv_init() call to platform_get_resource() since that
check is done inside devm_platform_ioremap_resource()
- Move spin_lock_init() before error check
- Remove extra parentheses
v11-0015-soc-amd-Add-support-for-AMD-Pensando-SoC-Control
- Fix the compatible to be specific 'amd,pensando-elba-ctrl'
- Cast arguments flagged with a gcc-12.1.0 warning:
Reported-by: kernel test robot <[email protected]>
Link: https://lore.kernel.org/oe-kbuild-all/[email protected]/
== V10 changes ==
Binding property amd,pensando-elba-syscon was merged in 6.2
v10-0002-dt-bindings-mmc-cdns-Add-AMD-Pensando-Elba-SoC
- Move reset-names property definition next to existing resets prop
- Move allOf to the bottom and set resets/reset-names required only for pensando
- Fix reg maxItems for existing, must be 1
v10-0003-dt-bindings-spi-cdns-Add-compatible-for-AMD-Pens
- Fix cdns,fifo-depth, only amd,pensando-elba-qspi is 1024 bytes
v10-0004-dt-bindings-spi-dw-Add-AMD-Pensando-Elba-SoC-SPI
- Move definition of amd,pensando-elba-syscon into properties with a better description
- Add amd,pensando-elba-syscon: false for non elba designs
v10-0005-dt-bindings-soc-amd-amd-pensando-elbasr-Add-AMD-
- Property renamed to amd,pensando-ctrl
- Driver is renamed and moved to soc/drivers/amd affecting binding
- Delete cs property, driver handles device node creation from parent num-cs
fixing schema reg error in a different way
v10-0010-spi-dw-Add-support-for-AMD-Pensando-Elba-SoC
- Delete struct dw_spi_elba, use regmap directly in priv
v10-0011-mmc-sdhci-cadence-Enable-device-specific-overrid
- The 1st patch adding private writel() is unchanged. The 2nd patch is split
into two patches to provide for device specific init in one patch with no
effect on existing designs. Then add the pensando support into the next patch.
Then the 4th patch is mmc hardware reset support which is unchanged.
v10-0012-mmc-sdhci-cadence-Support-device-specific-init-i
- New patch to provide for platform specific init() with no change
to existing designs.
v10-0013-mmc-sdhci-cadence-Add-AMD-Pensando-Elba-SoC-supp
- Add Elba specific support into this 3rd patch. This builds on the private
writel() enabled in patch 1 followed by platform specific init() in patch 2.
- Specify when first used the reason for the spinlock use to order byte-enable
prior to write data.
v10-0015-soc-amd-Add-support-for-AMD-Pensando-SoC-Control
- Different driver implementation specific to this Pensando controller device.
- Moved to soc/amd directory under new name based on guidance. This driver is
of no use to any design other than all Pensando SoC based cards.
- Removed use of builtin_driver, can be built as a module.
== V9 changes ==
v9-0002-dt-bindings-mmc-cdns-Add-AMD-Pensando-Elba-SoC
- Add reset-names and resets properties
- Add if/then on property amd,pensando-elba-sd4hc to set reg property
values for minItems and maxItems
v9-0003-dt-bindings-spi-cdns-Add-compatible-for-AMD-Pensa
- Add 1024 to cdns,fifo-depth property to resolve dtbs_check error
v9-0004-dt-bindings-spi-dw-Add-AMD-Pensando-Elba-SoC-SPI-
- Define property amd,pensando-elba-syscon
- Move compatible amd,pensando-elba-spi ahead of baikal,bt1-ssi
v9-0006-dt-bindings-mfd-amd-pensando-elbasr-Add-AMD-Pensa
- Instead of four nodes, one per chip-select, a single
node is used with reset-cells in the parent.
- No MFD API is used anymore in the driver so it made
sense to move this to drivers/spi.
- This driver is common for all Pensando SoC based designs
so changed the name to pensando-sr.c to not make it Elba
SoC specific.
- Added property cs for the chip-select number which is used
by the driver to create /dev/pensr0.<cs>
v9-0009-arm64-dts-Add-AMD-Pensando-Elba-SoC-support
- Single node for spi0 system-controller and squash
the reset-controller child into parent
v9-0010-spi-cadence-quadspi-Add-compatible-for-AMD-Pensan
- Rebase to linux-next 6.2.0-rc1
v9-0011-spi-dw-Add-support-for-AMD-Pensando-Elba-SoC
- Add use of macros GENMASK() and BIT()
- Change ELBA_SPICS_SHIFT() to ELBA_SPICS_OFFSET()
v9-0012-mmc-sdhci-cadence-Enable-device-specific-override
- No change to this patch but as some patches are deleted and this is
a respin the three successive patches to sdhci-cadence.c are
patches 12, 13, and 14 which do the following:
1. Add ability for Cadence specific design to have priv writel().
2. Add Elba SoC support that requires its own priv writel() for
byte-lane control .
3. Add support for mmc hardware reset.
v9-0014-mmc-sdhci-cadence-Support-mmc-hardware-reset
- Previously patch 17/17
- Changed delay after reset_control_assert() from 9 to 3 usec
- Renamed sdhci_mmc_hw_reset() to sdhci_cdns_mmc_hw_reset()
v9-0015-spi-pensando-sr-Add-AMD-Pensando-SoC-System-Resou
- Previously patch 14/17
- After the change to the device tree node and squashing
reset-cells into the parent simplified this to not use
any MFD API and move it to drivers/spi/pensando-sr.c.
- Change the naming to remove elba since this driver is common
for all Pensando SoC designs .
- Default yes SPI_PENSANDO_SR for ARCH_PENSANDO
== V6 changes ==
- Updated copyright and SPDX
v6-0001-dt-bindings-arm-add-AMD-Pensando-boards
- Delete 'Device Tree Bindings' in title
v6-0002-dt-bindings-mmc-cdns-Add-AMD-Pensando-Elba-SoC
- Change if/then for Elba which has a second reg for byte-lane control
v6-0003-dt-bindings-spi-cdns-Add-compatible-for-AMD-Pensa
- no change
v6-0004-dt-bindings-spi-dw-Add-AMD-Pensando-Elba-SoC-SPI-
- Add amd,pensando-elba-syscon
v6-0005-dt-bindings-mfd-syscon-Add-amd-pensando-elba-sysc
- no change
v6-0006-dt-bindings-mfd-amd-pensando-elbasr-Add-AMD-Pensa
- Expand description, rename nodes and change compatible usage
v6-0007-dt-bindings-reset-amd-pensando-elbasr-reset-Add-A
- Delete nodename pattern and changed spi0 to spi
- File amd,pensando-elba-reset.h is deleted as there is only
one reset used.
- Update example
v6-0008-MAINTAINERS-Add-entry-for-AMD-PENSANDO
- no change
v6-0009-arm64-Add-config-for-AMD-Pensando-SoC-platforms
- no change
v6-0010-arm64-dts-Add-AMD-Pensando-Elba-SoC-support
- Update node names and add amd,pensando-elba-syscon
- Delete use of amd,pensando-elba-reset.h which had a single definition
v6-0011-spi-cadence-quadspi-Add-compatible-for-AMD-Pensan
- Remove (void) cast
v6-0012-spi-dw-Add-support-for-AMD-Pensando-Elba-SoC
- Update use of amd,pensando-elba-syscon
v6-0013-mmc-sdhci-cadence-Enable-device-specific-override
- Change this patch to add a priv_writel() callback where all
existing designs use writel(). This separates the Elba
support into three patches. The second patch is added
to the end of the sequence for Elba support. The third
patch enables mmc hardware reset.
v6-0014-mfd-pensando-elbasr-Add-AMD-Pensando-Elba-System-
- Updates from review comments
- Use spi_message_init_with_transfers instead of init/add_tail API
v6-0015-reset-elbasr-Add-AMD-Pensando-Elba-SR-Reset-Contr
- Remove use of amd,pensando-elba-reset.h and use BIT()
v6-0016-mmc-sdhci-cadence-Add-AMD-Pensando-Elba-SoC-suppo
- Elba sdhci-cadence.c support added in this patch to build on
0013 which just adds a callback to override priv_writel()
v6-0017-mmc-sdhci-cadence-Support-mmc-hardware-reset
- New patch where Elba has a reset-controller for mmc hardware
reset. The reset is implemented by a register in the cpld.
== V5 changes ==
- Change to AMD Pensando instead of Pensando.
- No reference to spidev in the device tree. Add multi-function driver
pensando-elbasr and sub-device reset-elbasr which provides mfd and
/dev interface to the cpld.
- Rebase to linux-next tag next-20220609 5.19.0-rc1
- Redo the email list after rebase and using scripts/get_maintainer.pl
== V4 changes ==
The version of dtschema used is 2022.3.2.
v4-0001-dt-bindings-arm-add-Pensando-boards.patch
- Add description and board compatible
v4-0003-dt-bindings-mmc-Add-Pensando-Elba-SoC-binding.patch
- Change from elba-emmc to elba-sd4hc to match file convention
- Use minItems: 1 and maxItems: 2 to pass schema check
v4-0005-dt-bindings-spi-dw-Add-Pensando-Elba-SoC-SPI-Control.patch
- Add required property pensando,syscon-spics to go with
pensando,elba-spi
v4-0006-MAINTAINERS-Add-entry-for-PENSANDO.patch
- Change Maintained to Supported
v4-0007-arm64-Add-config-for-Pensando-SoC-platforms.patch
- Fix a typo on interface max speed
v4-0008-spi-cadence-quadspi-Add-compatible-for-Pensando-Elba.patch
- Update due to spi-cadence-quadspi.c changes
v4-0009-mmc-sdhci-cadence-Add-Pensando-Elba-SoC-support.patch
- Change from elba-emmc to elba-sd4hc to match file convention
v4-0010-spi-dw-Add-support-for-Pensando-Elba-SoC.patch
- Use more descriptive dt property pensando,syscon-spics
- Minor changes from review input
v4-0011-arm64-dts-Add-Pensando-Elba-SoC-support.patch
- Changed to dual copyright (GPL-2.0+ OR MIT)
- Minor changes from review input
== V3 changes ==
v3-0001-gpio-Add-Elba-SoC-gpio-driver-for-spi-cs-control.patch
- This patch is deleted. Elba SOC specific gpio spics control is
integrated into spi-dw-mmio.c.
v3-0002-spi-cadence-quadspi-Add-QSPI-support-for-Pensando-El.patch
- Changed compatible to "pensando,elba-qspi" to be more descriptive
in spi-cadence-quadspi.c.
- Arnd wondered if moving to DT properties for quirks may be the
way to go. Feedback I've received on other patches was don't
mix two efforts in one patch so I'm currently just adding the
Elba support to the current design.
v3-0003-spi-dw-Add-support-for-Pensando-Elba-SoC-SPI.patch
- Changed the implementation to use existing dw_spi_set_cs() and
integrated Elba specific CS control into spi-dw-mmio.c. The
native designware support is for two chip-selects while Elba
provides 4 chip-selects. Instead of adding a new file for
this support in gpio-elba-spics.c the support is in one
file (spi-dw-mmio.c).
v3-0004-spidev-Add-Pensando-CPLD-compatible.patch
- This patch is deleted. The addition of compatible "pensando,cpld"
to spidev.c is not added and an existing compatible is used
in the device tree to enable.
v3-0005-mmc-sdhci-cadence-Add-Pensando-Elba-SoC-support.patch
- Ulf and Yamada-san agreed the amount of code for this support
is not enough to need a new file. The support is added into
sdhci-cadence.c and new files sdhci-cadence-elba.c and
sdhci-cadence.h are deleted.
- Redundant defines are removed (e.g. use SDHCI_CDNS_HRS04 and
remove SDIO_REG_HRS4).
- Removed phy init function sd4_set_dlyvr() and used existing
sdhci_cdns_phy_init(). Init values are from DT properties.
- Replace devm_ioremap_resource(&pdev->dev, iomem)
with devm_platform_ioremap_resource(pdev, 1)
- Refactored the elba priv_writ_l() and elba_write_l() to
remove a little redundant code.
- The config option CONFIG_MMC_SDHCI_CADENCE_ELBA goes away.
- Only C syntax and Elba functions are prefixed with elba_
v3-0006-arm64-Add-config-for-Pensando-SoC-platforms.patch
- Added a little more info to the platform help text to assist
users to decide on including platform support or not.
v3-0007-arm64-dts-Add-Pensando-Elba-SoC-support.patch
- Node names changed to DT generic names
- Changed from using 'spi@' which is reserved
- The elba-flash-parts.dtsi is kept separate as
it is included in multiple dts files.
- SPDX license tags at the top of each file
- The compatible = "pensando,elba" and 'model' are
now together in the board file.
- UIO nodes removed
- Ordered nodes by increasing unit address
- Removed an unreferenced container node.
- Dropped deprecated 'device_type' for uart0 node.
v3-0010-dt-bindings-spi-cadence-qspi-Add-support-for-Pensand.patch
- Updated since the latest documentation has been converted to yaml
v3-0011-dt-bindings-gpio-Add-Pensando-Elba-SoC-support.patch
- This patch is deleted since the Elba gpio spics is added to
the spi dw driver and documented there.
Because of the deletion of patches and merging of code
the new patchset is not similar. A changelog is added into
the patches for merged code to be helpful on the history.
== V2 changes ==
- 01 Fix typo, return code value and log message.
- 03 Remove else clause, intrinsic DW chip-select is never used.
- 08-11 Split out dts and bindings to sub-patches
- 10 Converted existing cadence-quadspi.txt to YAML schema
- 13 New driver should use <linux/gpio/driver.h>
Brad Larson (15):
dt-bindings: arm: add AMD Pensando boards
dt-bindings: mmc: cdns: Add AMD Pensando Elba SoC
dt-bindings: spi: cdns: Add compatible for AMD Pensando Elba SoC
dt-bindings: spi: dw: Add AMD Pensando Elba SoC SPI Controller
dt-bindings: soc: amd: amd,pensando-elba-ctrl: Add Pensando SoC
Controller
MAINTAINERS: Add entry for AMD PENSANDO
arm64: Add config for AMD Pensando SoC platforms
arm64: dts: Add AMD Pensando Elba SoC support
spi: cadence-quadspi: Add compatible for AMD Pensando Elba SoC
spi: dw: Add support for AMD Pensando Elba SoC
mmc: sdhci-cadence: Enable device specific override of writel()
mmc: sdhci-cadence: Support device specific init during probe
mmc: sdhci-cadence: Add AMD Pensando Elba SoC support
mmc: sdhci-cadence: Support mmc hardware reset
soc: amd: Add support for AMD Pensando SoC Controller
.../devicetree/bindings/arm/amd,pensando.yaml | 26 ++
.../devicetree/bindings/mmc/cdns,sdhci.yaml | 27 +-
.../soc/amd/amd,pensando-elba-ctrl.yaml | 58 +++
.../bindings/spi/cdns,qspi-nor.yaml | 19 +-
.../bindings/spi/snps,dw-apb-ssi.yaml | 19 +
MAINTAINERS | 9 +
arch/arm64/Kconfig.platforms | 12 +
arch/arm64/boot/dts/amd/Makefile | 1 +
arch/arm64/boot/dts/amd/elba-16core.dtsi | 189 +++++++++
arch/arm64/boot/dts/amd/elba-asic-common.dtsi | 80 ++++
arch/arm64/boot/dts/amd/elba-asic.dts | 28 ++
arch/arm64/boot/dts/amd/elba-flash-parts.dtsi | 106 +++++
arch/arm64/boot/dts/amd/elba.dtsi | 191 +++++++++
drivers/mmc/host/Kconfig | 1 +
drivers/mmc/host/sdhci-cadence.c | 175 +++++++-
drivers/soc/Kconfig | 1 +
drivers/soc/Makefile | 1 +
drivers/soc/amd/Kconfig | 16 +
drivers/soc/amd/Makefile | 2 +
drivers/soc/amd/pensando-ctrl.c | 373 ++++++++++++++++++
drivers/spi/spi-cadence-quadspi.c | 19 +
drivers/spi/spi-dw-mmio.c | 58 +++
include/uapi/linux/amd-pensando-ctrl.h | 30 ++
23 files changed, 1421 insertions(+), 20 deletions(-)
create mode 100644 Documentation/devicetree/bindings/arm/amd,pensando.yaml
create mode 100644 Documentation/devicetree/bindings/soc/amd/amd,pensando-elba-ctrl.yaml
create mode 100644 arch/arm64/boot/dts/amd/elba-16core.dtsi
create mode 100644 arch/arm64/boot/dts/amd/elba-asic-common.dtsi
create mode 100644 arch/arm64/boot/dts/amd/elba-asic.dts
create mode 100644 arch/arm64/boot/dts/amd/elba-flash-parts.dtsi
create mode 100644 arch/arm64/boot/dts/amd/elba.dtsi
create mode 100644 drivers/soc/amd/Kconfig
create mode 100644 drivers/soc/amd/Makefile
create mode 100644 drivers/soc/amd/pensando-ctrl.c
create mode 100644 include/uapi/linux/amd-pensando-ctrl.h
base-commit: fe15c26ee26efa11741a7b632e9f23b01aca4cc6
--
2.17.1
Support the AMD Pensando Elba SoC Controller which is a SPI connected
device providing a miscellaneous set of essential board control/status
registers. This device is present in all Pensando SoC based designs.
Signed-off-by: Brad Larson <[email protected]>
Reviewed-by: Krzysztof Kozlowski <[email protected]>
---
v11 changes:
- Fixed the compatible which should have stayed as 'amd,pensando-elba-ctrl',
the commit message, and the filename
- Reference spi-peripheral-props
- Delete spi-max-frequency
- Remove num-cs from example
v10 changes:
- Property renamed to amd,pensando-ctrl
- Driver is renamed and moved to soc/drivers/amd affecting binding
- Delete cs property, driver handles device node creation from parent num-cs
fixing schema reg error in a different way
v9 changes:
- Instead of four nodes, one per chip-select, a single
node is used with reset-cells in the parent.
- No MFD API is used anymore in the driver so it made
sense to move this to drivers/spi.
- This driver is common for all Pensando SoC based designs
so changed the name to pensando-sr.c to not make it Elba
SoC specific.
- Added property cs for the chip-select number which is used
by the driver to create /dev/pensr0.<cs>
---
.../soc/amd/amd,pensando-elba-ctrl.yaml | 58 +++++++++++++++++++
1 file changed, 58 insertions(+)
create mode 100644 Documentation/devicetree/bindings/soc/amd/amd,pensando-elba-ctrl.yaml
diff --git a/Documentation/devicetree/bindings/soc/amd/amd,pensando-elba-ctrl.yaml b/Documentation/devicetree/bindings/soc/amd/amd,pensando-elba-ctrl.yaml
new file mode 100644
index 000000000000..f1d3ed4f519b
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/amd/amd,pensando-elba-ctrl.yaml
@@ -0,0 +1,58 @@
+# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/amd/amd,pensando-elba-ctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: AMD Pensando Elba SoC Controller
+
+description:
+ The AMD Pensando Elba SoC Controller is a SPI connected device with essential
+ control/status registers accessed on chip select 0. This device is present
+ in all Pensando SoC based designs.
+
+maintainers:
+ - Brad Larson <[email protected]>
+
+properties:
+ compatible:
+ enum:
+ - amd,pensando-elba-ctrl
+
+ reg:
+ maxItems: 1
+
+ '#reset-cells':
+ const: 1
+
+ interrupts:
+ maxItems: 1
+
+required:
+ - compatible
+ - '#reset-cells'
+
+allOf:
+ - $ref: /schemas/spi/spi-peripheral-props.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ system-controller@0 {
+ compatible = "amd,pensando-elba-ctrl";
+ reg = <0>;
+ spi-max-frequency = <12000000>;
+ interrupt-parent = <&porta>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+ #reset-cells = <1>;
+ };
+ };
+
+...
--
2.17.1
Add entry for AMD PENSANDO maintainer and files
Signed-off-by: Brad Larson <[email protected]>
---
MAINTAINERS | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 8d5bc223f305..5e39def215c9 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1875,6 +1875,15 @@ N: allwinner
N: sun[x456789]i
N: sun[25]0i
+ARM/AMD PENSANDO ARM64 ARCHITECTURE
+M: Brad Larson <[email protected]>
+L: [email protected] (moderated for non-subscribers)
+S: Supported
+F: Documentation/devicetree/bindings/*/amd,pensando*
+F: Documentation/devicetree/bindings/soc/amd/amd,pensando*
+F: arch/arm64/boot/dts/amd/elba*
+F: drivers/soc/amd/
+
ARM/Amlogic Meson SoC CLOCK FRAMEWORK
M: Neil Armstrong <[email protected]>
M: Jerome Brunet <[email protected]>
--
2.17.1
Add ARCH_PENSANDO configuration option for AMD Pensando SoC
based platforms.
Signed-off-by: Brad Larson <[email protected]>
---
arch/arm64/Kconfig.platforms | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
index 89a0b13b058d..3510daaabe27 100644
--- a/arch/arm64/Kconfig.platforms
+++ b/arch/arm64/Kconfig.platforms
@@ -236,6 +236,18 @@ config ARCH_NPCM
General support for NPCM8xx BMC (Arbel).
Nuvoton NPCM8xx BMC based on the Cortex A35.
+config ARCH_PENSANDO
+ bool "AMD Pensando Platforms"
+ help
+ This enables support for the ARMv8 based AMD Pensando SoC
+ family to include the Elba SoC.
+
+ AMD Pensando SoCs support a range of Distributed Services
+ Cards in PCIe format installed into servers. The Elba
+ SoC includes 16 A-72 CPU cores, 144 programmable P4
+ cores for a minimal latency/jitter datapath, and network
+ interfaces up to 200 Gb/s.
+
config ARCH_QCOM
bool "Qualcomm Platforms"
select GPIOLIB
--
2.17.1
The AMD Pensando Elba SoC has integrated the DW APB SPI Controller
Signed-off-by: Brad Larson <[email protected]>
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Reviewed-by: Serge Semin <[email protected]>
---
v12 changes:
- Correct property amd,pensando-elba-syscon description
v10 changes:
- Move definition of amd,pensando-elba-syscon into properties
with a better description
- Add amd,pensando-elba-syscon: false for non elba designs
v9 changes:
- Define property amd,pensando-elba-syscon
- Move compatible amd,pensando-elba-spi ahead of baikal,bt1-ssi
---
.../bindings/spi/snps,dw-apb-ssi.yaml | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
index a132b5fc56e0..12ca108864c6 100644
--- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
+++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
@@ -37,6 +37,17 @@ allOf:
else:
required:
- interrupts
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: amd,pensando-elba-spi
+ then:
+ required:
+ - amd,pensando-elba-syscon
+ else:
+ properties:
+ amd,pensando-elba-syscon: false
properties:
compatible:
@@ -63,6 +74,8 @@ properties:
const: intel,keembay-ssi
- description: Intel Thunder Bay SPI Controller
const: intel,thunderbay-ssi
+ - description: AMD Pensando Elba SoC SPI Controller
+ const: amd,pensando-elba-spi
- description: Baikal-T1 SPI Controller
const: baikal,bt1-ssi
- description: Baikal-T1 System Boot SPI Controller
@@ -136,6 +149,12 @@ properties:
of the designware controller, and the upper limit is also subject to
controller configuration.
+ amd,pensando-elba-syscon:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description:
+ Block address to control SPI chip-selects. The Elba SoC system controller
+ provides an interface to override the native DWC SSI CS control.
+
patternProperties:
"^.*@[0-9a-f]+$":
type: object
--
2.17.1
The AMD Pensando Elba SoC has the Cadence QSPI controller integrated.
The quirk CQSPI_NEEDS_APB_AHB_HAZARD_WAR is added and if enabled
a dummy readback from the controller is performed to ensure
synchronization.
Signed-off-by: Brad Larson <[email protected]>
---
v9 changes:
- Rebase to linux-next 6.2.0-rc1
---
drivers/spi/spi-cadence-quadspi.c | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c
index 64b6a460d739..ad82d2ab3442 100644
--- a/drivers/spi/spi-cadence-quadspi.c
+++ b/drivers/spi/spi-cadence-quadspi.c
@@ -40,6 +40,7 @@
#define CQSPI_SUPPORT_EXTERNAL_DMA BIT(2)
#define CQSPI_NO_SUPPORT_WR_COMPLETION BIT(3)
#define CQSPI_SLOW_SRAM BIT(4)
+#define CQSPI_NEEDS_APB_AHB_HAZARD_WAR BIT(5)
/* Capabilities */
#define CQSPI_SUPPORTS_OCTAL BIT(0)
@@ -90,6 +91,7 @@ struct cqspi_st {
u32 pd_dev_id;
bool wr_completion;
bool slow_sram;
+ bool apb_ahb_hazard;
};
struct cqspi_driver_platdata {
@@ -1004,6 +1006,13 @@ static int cqspi_indirect_write_execute(struct cqspi_flash_pdata *f_pdata,
if (cqspi->wr_delay)
ndelay(cqspi->wr_delay);
+ /*
+ * If a hazard exists between the APB and AHB interfaces, perform a
+ * dummy readback from the controller to ensure synchronization.
+ */
+ if (cqspi->apb_ahb_hazard)
+ readl(reg_base + CQSPI_REG_INDIRECTWR);
+
while (remaining > 0) {
size_t write_words, mod_bytes;
@@ -1734,6 +1743,8 @@ static int cqspi_probe(struct platform_device *pdev)
cqspi->wr_completion = false;
if (ddata->quirks & CQSPI_SLOW_SRAM)
cqspi->slow_sram = true;
+ if (ddata->quirks & CQSPI_NEEDS_APB_AHB_HAZARD_WAR)
+ cqspi->apb_ahb_hazard = true;
if (of_device_is_compatible(pdev->dev.of_node,
"xlnx,versal-ospi-1.0"))
@@ -1859,6 +1870,10 @@ static const struct cqspi_driver_platdata versal_ospi = {
.get_dma_status = cqspi_get_versal_dma_status,
};
+static const struct cqspi_driver_platdata pensando_cdns_qspi = {
+ .quirks = CQSPI_NEEDS_APB_AHB_HAZARD_WAR | CQSPI_DISABLE_DAC_MODE,
+};
+
static const struct of_device_id cqspi_dt_ids[] = {
{
.compatible = "cdns,qspi-nor",
@@ -1884,6 +1899,10 @@ static const struct of_device_id cqspi_dt_ids[] = {
.compatible = "intel,socfpga-qspi",
.data = &socfpga_qspi,
},
+ {
+ .compatible = "amd,pensando-elba-qspi",
+ .data = &pensando_cdns_qspi,
+ },
{ /* end of table */ }
};
--
2.17.1
The AMD Pensando Elba SoC includes a DW apb_ssi v4 controller
with device specific chip-select control. The Elba SoC
provides four chip-selects where the native DW IP supports
two chip-selects. The Elba DW_SPI instance has two native
CS signals that are always overridden.
Signed-off-by: Brad Larson <[email protected]>
Reviewed-by: Serge Semin <[email protected]>
---
v12 changes:
- Add a newline in function dw_spi_elba_init()
v11 changes:
- Simplify dw_spi_elb_init by using syscon_regmap_lookup_by_phandle()
v10 changes:
- Delete struct dw_spi_elba, use regmap directly in priv
v9 changes:
- Add use of macros GENMASK() and BIT()
- Change ELBA_SPICS_SHIFT() to ELBA_SPICS_OFFSET()
---
drivers/spi/spi-dw-mmio.c | 58 +++++++++++++++++++++++++++++++++++++++
1 file changed, 58 insertions(+)
diff --git a/drivers/spi/spi-dw-mmio.c b/drivers/spi/spi-dw-mmio.c
index 26c40ea6dd12..8cfad64b5463 100644
--- a/drivers/spi/spi-dw-mmio.c
+++ b/drivers/spi/spi-dw-mmio.c
@@ -53,6 +53,20 @@ struct dw_spi_mscc {
void __iomem *spi_mst; /* Not sparx5 */
};
+/*
+ * Elba SoC does not use ssi, pin override is used for cs 0,1 and
+ * gpios for cs 2,3 as defined in the device tree.
+ *
+ * cs: | 1 0
+ * bit: |---3-------2-------1-------0
+ * | cs1 cs1_ovr cs0 cs0_ovr
+ */
+#define ELBA_SPICS_REG 0x2468
+#define ELBA_SPICS_OFFSET(cs) ((cs) << 1)
+#define ELBA_SPICS_MASK(cs) (GENMASK(1, 0) << ELBA_SPICS_OFFSET(cs))
+#define ELBA_SPICS_SET(cs, val) \
+ ((((val) << 1) | BIT(0)) << ELBA_SPICS_OFFSET(cs))
+
/*
* The Designware SPI controller (referred to as master in the documentation)
* automatically deasserts chip select when the tx fifo is empty. The chip
@@ -237,6 +251,49 @@ static int dw_spi_canaan_k210_init(struct platform_device *pdev,
return 0;
}
+static void dw_spi_elba_override_cs(struct regmap *syscon, int cs, int enable)
+{
+ regmap_update_bits(syscon, ELBA_SPICS_REG, ELBA_SPICS_MASK(cs),
+ ELBA_SPICS_SET(cs, enable));
+}
+
+static void dw_spi_elba_set_cs(struct spi_device *spi, bool enable)
+{
+ struct dw_spi *dws = spi_master_get_devdata(spi->master);
+ struct dw_spi_mmio *dwsmmio = container_of(dws, struct dw_spi_mmio, dws);
+ struct regmap *syscon = dwsmmio->priv;
+ u8 cs;
+
+ cs = spi->chip_select;
+ if (cs < 2)
+ dw_spi_elba_override_cs(syscon, spi->chip_select, enable);
+
+ /*
+ * The DW SPI controller needs a native CS bit selected to start
+ * the serial engine.
+ */
+ spi->chip_select = 0;
+ dw_spi_set_cs(spi, enable);
+ spi->chip_select = cs;
+}
+
+static int dw_spi_elba_init(struct platform_device *pdev,
+ struct dw_spi_mmio *dwsmmio)
+{
+ struct regmap *syscon;
+
+ syscon = syscon_regmap_lookup_by_phandle(dev_of_node(&pdev->dev),
+ "amd,pensando-elba-syscon");
+ if (IS_ERR(syscon))
+ return dev_err_probe(&pdev->dev, PTR_ERR(syscon),
+ "syscon regmap lookup failed\n");
+
+ dwsmmio->priv = syscon;
+ dwsmmio->dws.set_cs = dw_spi_elba_set_cs;
+
+ return 0;
+}
+
static int dw_spi_mmio_probe(struct platform_device *pdev)
{
int (*init_func)(struct platform_device *pdev,
@@ -352,6 +409,7 @@ static const struct of_device_id dw_spi_mmio_of_match[] = {
{ .compatible = "intel,thunderbay-ssi", .data = dw_spi_intel_init},
{ .compatible = "microchip,sparx5-spi", dw_spi_mscc_sparx5_init},
{ .compatible = "canaan,k210-spi", dw_spi_canaan_k210_init},
+ { .compatible = "amd,pensando-elba-spi", .data = dw_spi_elba_init},
{ /* end of table */}
};
MODULE_DEVICE_TABLE(of, dw_spi_mmio_of_match);
--
2.17.1
Add AMD Pensando common and Elba SoC specific device nodes
Signed-off-by: Brad Larson <[email protected]>
---
v11 changes:
- Delete reset-names
- Fix spi0 compatible to be specific 'amd,pensando-elba-ctrl'
v9 changes:
- Single node for spi0 system-controller and squash
the reset-controller child into parent
---
arch/arm64/boot/dts/amd/Makefile | 1 +
arch/arm64/boot/dts/amd/elba-16core.dtsi | 189 +++++++++++++++++
arch/arm64/boot/dts/amd/elba-asic-common.dtsi | 80 ++++++++
arch/arm64/boot/dts/amd/elba-asic.dts | 28 +++
arch/arm64/boot/dts/amd/elba-flash-parts.dtsi | 106 ++++++++++
arch/arm64/boot/dts/amd/elba.dtsi | 191 ++++++++++++++++++
6 files changed, 595 insertions(+)
create mode 100644 arch/arm64/boot/dts/amd/elba-16core.dtsi
create mode 100644 arch/arm64/boot/dts/amd/elba-asic-common.dtsi
create mode 100644 arch/arm64/boot/dts/amd/elba-asic.dts
create mode 100644 arch/arm64/boot/dts/amd/elba-flash-parts.dtsi
create mode 100644 arch/arm64/boot/dts/amd/elba.dtsi
diff --git a/arch/arm64/boot/dts/amd/Makefile b/arch/arm64/boot/dts/amd/Makefile
index 68103a8b0ef5..8502cc2afbc5 100644
--- a/arch/arm64/boot/dts/amd/Makefile
+++ b/arch/arm64/boot/dts/amd/Makefile
@@ -1,2 +1,3 @@
# SPDX-License-Identifier: GPL-2.0
+dtb-$(CONFIG_ARCH_PENSANDO) += elba-asic.dtb
dtb-$(CONFIG_ARCH_SEATTLE) += amd-overdrive-rev-b0.dtb amd-overdrive-rev-b1.dtb
diff --git a/arch/arm64/boot/dts/amd/elba-16core.dtsi b/arch/arm64/boot/dts/amd/elba-16core.dtsi
new file mode 100644
index 000000000000..37aadd442db8
--- /dev/null
+++ b/arch/arm64/boot/dts/amd/elba-16core.dtsi
@@ -0,0 +1,189 @@
+// SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
+/*
+ * Copyright 2020-2022 Advanced Micro Devices, Inc.
+ */
+
+/ {
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ cpu-map {
+ cluster0 {
+ core0 { cpu = <&cpu0>; };
+ core1 { cpu = <&cpu1>; };
+ core2 { cpu = <&cpu2>; };
+ core3 { cpu = <&cpu3>; };
+ };
+
+ cluster1 {
+ core0 { cpu = <&cpu4>; };
+ core1 { cpu = <&cpu5>; };
+ core2 { cpu = <&cpu6>; };
+ core3 { cpu = <&cpu7>; };
+ };
+
+ cluster2 {
+ core0 { cpu = <&cpu8>; };
+ core1 { cpu = <&cpu9>; };
+ core2 { cpu = <&cpu10>; };
+ core3 { cpu = <&cpu11>; };
+ };
+
+ cluster3 {
+ core0 { cpu = <&cpu12>; };
+ core1 { cpu = <&cpu13>; };
+ core2 { cpu = <&cpu14>; };
+ core3 { cpu = <&cpu15>; };
+ };
+ };
+
+ /* CLUSTER 0 */
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ reg = <0 0x0>;
+ next-level-cache = <&l2_0>;
+ enable-method = "psci";
+ };
+
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ reg = <0 0x1>;
+ next-level-cache = <&l2_0>;
+ enable-method = "psci";
+ };
+
+ cpu2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ reg = <0 0x2>;
+ next-level-cache = <&l2_0>;
+ enable-method = "psci";
+ };
+
+ cpu3: cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ reg = <0 0x3>;
+ next-level-cache = <&l2_0>;
+ enable-method = "psci";
+ };
+
+ l2_0: l2-cache0 {
+ compatible = "cache";
+ };
+
+ /* CLUSTER 1 */
+ cpu4: cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ reg = <0 0x100>;
+ next-level-cache = <&l2_1>;
+ enable-method = "psci";
+ };
+
+ cpu5: cpu@101 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ reg = <0 0x101>;
+ next-level-cache = <&l2_1>;
+ enable-method = "psci";
+ };
+
+ cpu6: cpu@102 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ reg = <0 0x102>;
+ next-level-cache = <&l2_1>;
+ enable-method = "psci";
+ };
+
+ cpu7: cpu@103 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ reg = <0 0x103>;
+ next-level-cache = <&l2_1>;
+ enable-method = "psci";
+ };
+
+ l2_1: l2-cache1 {
+ compatible = "cache";
+ };
+
+ /* CLUSTER 2 */
+ cpu8: cpu@200 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ reg = <0 0x200>;
+ next-level-cache = <&l2_2>;
+ enable-method = "psci";
+ };
+
+ cpu9: cpu@201 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ reg = <0 0x201>;
+ next-level-cache = <&l2_2>;
+ enable-method = "psci";
+ };
+
+ cpu10: cpu@202 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ reg = <0 0x202>;
+ next-level-cache = <&l2_2>;
+ enable-method = "psci";
+ };
+
+ cpu11: cpu@203 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ reg = <0 0x203>;
+ next-level-cache = <&l2_2>;
+ enable-method = "psci";
+ };
+
+ l2_2: l2-cache2 {
+ compatible = "cache";
+ };
+
+ /* CLUSTER 3 */
+ cpu12: cpu@300 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ reg = <0 0x300>;
+ next-level-cache = <&l2_3>;
+ enable-method = "psci";
+ };
+
+ cpu13: cpu@301 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ reg = <0 0x301>;
+ next-level-cache = <&l2_3>;
+ enable-method = "psci";
+ };
+
+ cpu14: cpu@302 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ reg = <0 0x302>;
+ next-level-cache = <&l2_3>;
+ enable-method = "psci";
+ };
+
+ cpu15: cpu@303 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ reg = <0 0x303>;
+ next-level-cache = <&l2_3>;
+ enable-method = "psci";
+ };
+
+ l2_3: l2-cache3 {
+ compatible = "cache";
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/amd/elba-asic-common.dtsi b/arch/arm64/boot/dts/amd/elba-asic-common.dtsi
new file mode 100644
index 000000000000..1a615788f54e
--- /dev/null
+++ b/arch/arm64/boot/dts/amd/elba-asic-common.dtsi
@@ -0,0 +1,80 @@
+// SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
+/*
+ * Copyright 2020-2022 Advanced Micro Devices, Inc.
+ */
+
+&ahb_clk {
+ clock-frequency = <400000000>;
+};
+
+&emmc_clk {
+ clock-frequency = <200000000>;
+};
+
+&flash_clk {
+ clock-frequency = <400000000>;
+};
+
+&ref_clk {
+ clock-frequency = <156250000>;
+};
+
+&qspi {
+ status = "okay";
+
+ flash0: flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <40000000>;
+ spi-rx-bus-width = <2>;
+ m25p,fast-read;
+ cdns,read-delay = <0>;
+ cdns,tshsl-ns = <0>;
+ cdns,tsd2d-ns = <0>;
+ cdns,tchsh-ns = <0>;
+ cdns,tslch-ns = <0>;
+ };
+};
+
+&gpio0 {
+ status = "okay";
+};
+
+&emmc {
+ bus-width = <8>;
+ cap-mmc-hw-reset;
+ resets = <&rstc 0>;
+ status = "okay";
+};
+
+&wdt0 {
+ status = "okay";
+};
+
+&i2c0 {
+ clock-frequency = <100000>;
+ status = "okay";
+
+ rtc@51 {
+ compatible = "nxp,pcf85263";
+ reg = <0x51>;
+ };
+};
+
+&spi0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ num-cs = <4>;
+ cs-gpios = <0>, <0>, <&porta 1 GPIO_ACTIVE_LOW>,
+ <&porta 7 GPIO_ACTIVE_LOW>;
+ status = "okay";
+
+ rstc: system-controller@0 {
+ compatible = "amd,pensando-elba-ctrl";
+ reg = <0>;
+ spi-max-frequency = <12000000>;
+ interrupt-parent = <&porta>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+ #reset-cells = <1>;
+ };
+};
diff --git a/arch/arm64/boot/dts/amd/elba-asic.dts b/arch/arm64/boot/dts/amd/elba-asic.dts
new file mode 100644
index 000000000000..c3f4da2f7449
--- /dev/null
+++ b/arch/arm64/boot/dts/amd/elba-asic.dts
@@ -0,0 +1,28 @@
+// SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
+/*
+ * Device Tree file for AMD Pensando Elba Board.
+ *
+ * Copyright 2020-2022 Advanced Micro Devices, Inc.
+ */
+
+/dts-v1/;
+
+#include "elba.dtsi"
+#include "elba-16core.dtsi"
+#include "elba-asic-common.dtsi"
+#include "elba-flash-parts.dtsi"
+
+/ {
+ model = "AMD Pensando Elba Board";
+ compatible = "amd,pensando-elba-ortano", "amd,pensando-elba";
+
+ aliases {
+ serial0 = &uart0;
+ spi0 = &spi0;
+ spi1 = &qspi;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
diff --git a/arch/arm64/boot/dts/amd/elba-flash-parts.dtsi b/arch/arm64/boot/dts/amd/elba-flash-parts.dtsi
new file mode 100644
index 000000000000..734893fef2c3
--- /dev/null
+++ b/arch/arm64/boot/dts/amd/elba-flash-parts.dtsi
@@ -0,0 +1,106 @@
+// SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
+/*
+ * Copyright 2020-2022 Advanced Micro Devices, Inc.
+ */
+
+&flash0 {
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ partition@0 {
+ label = "flash";
+ reg = <0x10000 0xfff0000>;
+ };
+
+ partition@f0000 {
+ label = "golduenv";
+ reg = <0xf0000 0x10000>;
+ };
+
+ partition@100000 {
+ label = "boot0";
+ reg = <0x100000 0x80000>;
+ };
+
+ partition@180000 {
+ label = "golduboot";
+ reg = <0x180000 0x200000>;
+ };
+
+ partition@380000 {
+ label = "brdcfg0";
+ reg = <0x380000 0x10000>;
+ };
+
+ partition@390000 {
+ label = "brdcfg1";
+ reg = <0x390000 0x10000>;
+ };
+
+ partition@400000 {
+ label = "goldfw";
+ reg = <0x400000 0x3c00000>;
+ };
+
+ partition@4010000 {
+ label = "fwmap";
+ reg = <0x4010000 0x20000>;
+ };
+
+ partition@4030000 {
+ label = "fwsel";
+ reg = <0x4030000 0x20000>;
+ };
+
+ partition@4090000 {
+ label = "bootlog";
+ reg = <0x4090000 0x20000>;
+ };
+
+ partition@40b0000 {
+ label = "panicbuf";
+ reg = <0x40b0000 0x20000>;
+ };
+
+ partition@40d0000 {
+ label = "uservars";
+ reg = <0x40d0000 0x20000>;
+ };
+
+ partition@4200000 {
+ label = "uboota";
+ reg = <0x4200000 0x400000>;
+ };
+
+ partition@4600000 {
+ label = "ubootb";
+ reg = <0x4600000 0x400000>;
+ };
+
+ partition@4a00000 {
+ label = "mainfwa";
+ reg = <0x4a00000 0x1000000>;
+ };
+
+ partition@5a00000 {
+ label = "mainfwb";
+ reg = <0x5a00000 0x1000000>;
+ };
+
+ partition@6a00000 {
+ label = "diaguboot";
+ reg = <0x6a00000 0x400000>;
+ };
+
+ partition@8000000 {
+ label = "diagfw";
+ reg = <0x8000000 0x7fe0000>;
+ };
+
+ partition@ffe0000 {
+ label = "ubootenv";
+ reg = <0xffe0000 0x10000>;
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/amd/elba.dtsi b/arch/arm64/boot/dts/amd/elba.dtsi
new file mode 100644
index 000000000000..674890cf2a34
--- /dev/null
+++ b/arch/arm64/boot/dts/amd/elba.dtsi
@@ -0,0 +1,191 @@
+// SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
+/*
+ * Copyright 2020-2022 Advanced Micro Devices, Inc.
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include "dt-bindings/interrupt-controller/arm-gic.h"
+
+/ {
+ model = "Elba ASIC Board";
+ compatible = "amd,pensando-elba";
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ dma-coherent;
+
+ ahb_clk: oscillator0 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ };
+
+ emmc_clk: oscillator2 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ };
+
+ flash_clk: oscillator3 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ };
+
+ ref_clk: oscillator4 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ };
+
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
+ };
+
+ pmu {
+ compatible = "arm,cortex-a72-pmu";
+ interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
+ };
+
+ soc: soc {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ i2c0: i2c@400 {
+ compatible = "snps,designware-i2c";
+ reg = <0x0 0x400 0x0 0x100>;
+ clocks = <&ahb_clk>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ i2c-sda-hold-time-ns = <480>;
+ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ wdt0: watchdog@1400 {
+ compatible = "snps,dw-wdt";
+ reg = <0x0 0x1400 0x0 0x100>;
+ clocks = <&ahb_clk>;
+ interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ qspi: spi@2400 {
+ compatible = "amd,pensando-elba-qspi", "cdns,qspi-nor";
+ reg = <0x0 0x2400 0x0 0x400>,
+ <0x0 0x7fff0000 0x0 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&flash_clk>;
+ cdns,fifo-depth = <1024>;
+ cdns,fifo-width = <4>;
+ cdns,trigger-address = <0x7fff0000>;
+ status = "disabled";
+ };
+
+ spi0: spi@2800 {
+ compatible = "amd,pensando-elba-spi";
+ reg = <0x0 0x2800 0x0 0x100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ amd,pensando-elba-syscon = <&syscon>;
+ clocks = <&ahb_clk>;
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ num-cs = <2>;
+ status = "disabled";
+ };
+
+ gpio0: gpio@4000 {
+ compatible = "snps,dw-apb-gpio";
+ reg = <0x0 0x4000 0x0 0x78>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ porta: gpio-port@0 {
+ compatible = "snps,dw-apb-gpio-port";
+ reg = <0>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ ngpios = <8>;
+ interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ interrupt-parent = <&gic>;
+ #interrupt-cells = <2>;
+ };
+
+ portb: gpio-port@1 {
+ compatible = "snps,dw-apb-gpio-port";
+ reg = <1>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ ngpios = <8>;
+ };
+ };
+
+ uart0: serial@4800 {
+ compatible = "ns16550a";
+ reg = <0x0 0x4800 0x0 0x100>;
+ clocks = <&ref_clk>;
+ interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ };
+
+ gic: interrupt-controller@800000 {
+ compatible = "arm,gic-v3";
+ reg = <0x0 0x800000 0x0 0x200000>, /* GICD */
+ <0x0 0xa00000 0x0 0x200000>, /* GICR */
+ <0x0 0x60000000 0x0 0x2000>, /* GICC */
+ <0x0 0x60010000 0x0 0x1000>, /* GICH */
+ <0x0 0x60020000 0x0 0x2000>; /* GICV */
+ #address-cells = <2>;
+ #size-cells = <2>;
+ #interrupt-cells = <3>;
+ ranges;
+ interrupt-controller;
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+
+ /*
+ * Elba specific pre-ITS is enabled using the
+ * existing property socionext,synquacer-pre-its
+ */
+ gic_its: msi-controller@820000 {
+ compatible = "arm,gic-v3-its";
+ reg = <0x0 0x820000 0x0 0x10000>;
+ msi-controller;
+ #msi-cells = <1>;
+ socionext,synquacer-pre-its =
+ <0xc00000 0x1000000>;
+ };
+ };
+
+ emmc: mmc@30440000 {
+ compatible = "amd,pensando-elba-sd4hc", "cdns,sd4hc";
+ reg = <0x0 0x30440000 0x0 0x10000>,
+ <0x0 0x30480044 0x0 0x4>; /* byte-lane ctrl */
+ clocks = <&emmc_clk>;
+ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+ cdns,phy-input-delay-sd-highspeed = <0x4>;
+ cdns,phy-input-delay-legacy = <0x4>;
+ cdns,phy-input-delay-sd-uhs-sdr50 = <0x6>;
+ cdns,phy-input-delay-sd-uhs-ddr50 = <0x16>;
+ mmc-ddr-1_8v;
+ status = "disabled";
+ };
+
+ syscon: syscon@307c0000 {
+ compatible = "amd,pensando-elba-syscon", "syscon";
+ reg = <0x0 0x307c0000 0x0 0x3000>;
+ };
+ };
+};
--
2.17.1
SoCs with device specific Cadence implementation, such as setting
byte-enables before the write, need to override writel(). Add a
callback where the default is writel() for all existing chips.
Signed-off-by: Brad Larson <[email protected]>
Acked-by: Adrian Hunter <[email protected]>
---
v10 changes:
- The 1st patch adding private writel() is unchanged. The 2nd patch is split
into two patches to provide for device specific init in one patch with no
effect on existing designs. Then add the pensando support into the next patch.
Then the 4th patch is mmc hardware reset support which is unchanged.
v9 changes:
- No change to this patch but as some patches are deleted and this is
a respin the three successive patches to sdhci-cadence.c are
patches 12, 13, and 14 which do the following:
1. Add ability for Cadence specific design to have priv writel().
2. Add Elba SoC support that requires its own priv writel() for
byte-lane control .
3. Add support for mmc hardware reset.
---
drivers/mmc/host/sdhci-cadence.c | 18 +++++++++++++-----
1 file changed, 13 insertions(+), 5 deletions(-)
diff --git a/drivers/mmc/host/sdhci-cadence.c b/drivers/mmc/host/sdhci-cadence.c
index 6f2de54a5987..708d4297f241 100644
--- a/drivers/mmc/host/sdhci-cadence.c
+++ b/drivers/mmc/host/sdhci-cadence.c
@@ -67,6 +67,7 @@ struct sdhci_cdns_phy_param {
struct sdhci_cdns_priv {
void __iomem *hrs_addr;
bool enhanced_strobe;
+ void (*priv_writel)(struct sdhci_cdns_priv *priv, u32 val, void __iomem *reg);
unsigned int nr_phy_params;
struct sdhci_cdns_phy_param phy_params[];
};
@@ -90,6 +91,12 @@ static const struct sdhci_cdns_phy_cfg sdhci_cdns_phy_cfgs[] = {
{ "cdns,phy-dll-delay-strobe", SDHCI_CDNS_PHY_DLY_STROBE, },
};
+static inline void cdns_writel(struct sdhci_cdns_priv *priv, u32 val,
+ void __iomem *reg)
+{
+ writel(val, reg);
+}
+
static int sdhci_cdns_write_phy_reg(struct sdhci_cdns_priv *priv,
u8 addr, u8 data)
{
@@ -104,17 +111,17 @@ static int sdhci_cdns_write_phy_reg(struct sdhci_cdns_priv *priv,
tmp = FIELD_PREP(SDHCI_CDNS_HRS04_WDATA, data) |
FIELD_PREP(SDHCI_CDNS_HRS04_ADDR, addr);
- writel(tmp, reg);
+ priv->priv_writel(priv, tmp, reg);
tmp |= SDHCI_CDNS_HRS04_WR;
- writel(tmp, reg);
+ priv->priv_writel(priv, tmp, reg);
ret = readl_poll_timeout(reg, tmp, tmp & SDHCI_CDNS_HRS04_ACK, 0, 10);
if (ret)
return ret;
tmp &= ~SDHCI_CDNS_HRS04_WR;
- writel(tmp, reg);
+ priv->priv_writel(priv, tmp, reg);
ret = readl_poll_timeout(reg, tmp, !(tmp & SDHCI_CDNS_HRS04_ACK),
0, 10);
@@ -191,7 +198,7 @@ static void sdhci_cdns_set_emmc_mode(struct sdhci_cdns_priv *priv, u32 mode)
tmp = readl(priv->hrs_addr + SDHCI_CDNS_HRS06);
tmp &= ~SDHCI_CDNS_HRS06_MODE;
tmp |= FIELD_PREP(SDHCI_CDNS_HRS06_MODE, mode);
- writel(tmp, priv->hrs_addr + SDHCI_CDNS_HRS06);
+ priv->priv_writel(priv, tmp, priv->hrs_addr + SDHCI_CDNS_HRS06);
}
static u32 sdhci_cdns_get_emmc_mode(struct sdhci_cdns_priv *priv)
@@ -223,7 +230,7 @@ static int sdhci_cdns_set_tune_val(struct sdhci_host *host, unsigned int val)
*/
for (i = 0; i < 2; i++) {
tmp |= SDHCI_CDNS_HRS06_TUNE_UP;
- writel(tmp, reg);
+ priv->priv_writel(priv, tmp, reg);
ret = readl_poll_timeout(reg, tmp,
!(tmp & SDHCI_CDNS_HRS06_TUNE_UP),
@@ -386,6 +393,7 @@ static int sdhci_cdns_probe(struct platform_device *pdev)
priv->nr_phy_params = nr_phy_params;
priv->hrs_addr = host->ioaddr;
priv->enhanced_strobe = false;
+ priv->priv_writel = cdns_writel;
host->ioaddr += SDHCI_CDNS_SRS_BASE;
host->mmc_host_ops.hs400_enhanced_strobe =
sdhci_cdns_hs400_enhanced_strobe;
--
2.17.1
Add support for AMD Pensando Elba SoC which explicitly
controls byte-lane enables on writes.
Select MMC_SDHCI_IO_ACCESSORS for MMC_SDHCI_CADENCE which
allows Elba SoC sdhci_elba_ops to overwrite the SDHCI
IO memory accessors
Signed-off-by: Brad Larson <[email protected]>
Acked-by: Adrian Hunter <[email protected]>
---
v13 changes:
- Use GENMASK(7, 3) in elba_priv_writel() to set all byte enables
- Add a variable 'shift' with GENMASK(1, 0) in elba_write_w() and
elba_write_b() to set the byte enable variable.
v11 changes:
- Remove elba-drv_init() call to platform_get_resource() since that
check is done inside devm_platform_ioremap_resource()
- Move spin_lock_init() before error check
- Remove extra parentheses
v10 changes:
- Add Elba specific support into this 3rd patch. This builds on the private
writel() enabled in patch 1 followed by platform specific init() in patch 2.
- Specify when first used the reason for the spinlock use to order byte-enable
prior to write data.
---
drivers/mmc/host/Kconfig | 1 +
drivers/mmc/host/sdhci-cadence.c | 98 ++++++++++++++++++++++++++++++++
2 files changed, 99 insertions(+)
diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
index 4745fe217ade..9f793892123c 100644
--- a/drivers/mmc/host/Kconfig
+++ b/drivers/mmc/host/Kconfig
@@ -255,6 +255,7 @@ config MMC_SDHCI_CADENCE
tristate "SDHCI support for the Cadence SD/SDIO/eMMC controller"
depends on MMC_SDHCI_PLTFM
depends on OF
+ select MMC_SDHCI_IO_ACCESSORS
help
This selects the Cadence SD/SDIO/eMMC driver.
diff --git a/drivers/mmc/host/sdhci-cadence.c b/drivers/mmc/host/sdhci-cadence.c
index c528a25f48b8..5d1e9cef74f5 100644
--- a/drivers/mmc/host/sdhci-cadence.c
+++ b/drivers/mmc/host/sdhci-cadence.c
@@ -66,6 +66,8 @@ struct sdhci_cdns_phy_param {
struct sdhci_cdns_priv {
void __iomem *hrs_addr;
+ void __iomem *ctl_addr; /* write control */
+ spinlock_t wrlock; /* write lock */
bool enhanced_strobe;
void (*priv_writel)(struct sdhci_cdns_priv *priv, u32 val, void __iomem *reg);
unsigned int nr_phy_params;
@@ -321,6 +323,91 @@ static void sdhci_cdns_set_uhs_signaling(struct sdhci_host *host,
sdhci_set_uhs_signaling(host, timing);
}
+/* Elba control register bits [6:3] are byte-lane enables */
+#define ELBA_BYTE_ENABLE_MASK(x) ((x) << 3)
+
+/*
+ * The Pensando Elba SoC explicitly controls byte-lane enabling on writes
+ * which includes writes to the HRS registers. The write lock (wrlock)
+ * is used to ensure byte-lane enable, using write control (ctl_addr),
+ * occurs before the data write.
+ */
+static void elba_priv_writel(struct sdhci_cdns_priv *priv, u32 val,
+ void __iomem *reg)
+{
+ unsigned long flags;
+
+ spin_lock_irqsave(&priv->wrlock, flags);
+ writel(GENMASK(7, 3), priv->ctl_addr);
+ writel(val, reg);
+ spin_unlock_irqrestore(&priv->wrlock, flags);
+}
+
+static void elba_write_l(struct sdhci_host *host, u32 val, int reg)
+{
+ elba_priv_writel(sdhci_cdns_priv(host), val, host->ioaddr + reg);
+}
+
+static void elba_write_w(struct sdhci_host *host, u16 val, int reg)
+{
+ struct sdhci_cdns_priv *priv = sdhci_cdns_priv(host);
+ u32 shift = reg & GENMASK(1, 0);
+ unsigned long flags;
+ u32 byte_enables;
+
+ byte_enables = GENMASK(1, 0) << shift;
+ spin_lock_irqsave(&priv->wrlock, flags);
+ writel(ELBA_BYTE_ENABLE_MASK(byte_enables), priv->ctl_addr);
+ writew(val, host->ioaddr + reg);
+ spin_unlock_irqrestore(&priv->wrlock, flags);
+}
+
+static void elba_write_b(struct sdhci_host *host, u8 val, int reg)
+{
+ struct sdhci_cdns_priv *priv = sdhci_cdns_priv(host);
+ u32 shift = reg & GENMASK(1, 0);
+ unsigned long flags;
+ u32 byte_enables;
+
+ byte_enables = BIT(0) << shift;
+ spin_lock_irqsave(&priv->wrlock, flags);
+ writel(ELBA_BYTE_ENABLE_MASK(byte_enables), priv->ctl_addr);
+ writeb(val, host->ioaddr + reg);
+ spin_unlock_irqrestore(&priv->wrlock, flags);
+}
+
+static const struct sdhci_ops sdhci_elba_ops = {
+ .write_l = elba_write_l,
+ .write_w = elba_write_w,
+ .write_b = elba_write_b,
+ .set_clock = sdhci_set_clock,
+ .get_timeout_clock = sdhci_cdns_get_timeout_clock,
+ .set_bus_width = sdhci_set_bus_width,
+ .reset = sdhci_reset,
+ .set_uhs_signaling = sdhci_cdns_set_uhs_signaling,
+};
+
+static int elba_drv_init(struct platform_device *pdev)
+{
+ struct sdhci_host *host = platform_get_drvdata(pdev);
+ struct sdhci_cdns_priv *priv = sdhci_cdns_priv(host);
+ void __iomem *ioaddr;
+
+ host->mmc->caps |= MMC_CAP_1_8V_DDR | MMC_CAP_8_BIT_DATA;
+ spin_lock_init(&priv->wrlock);
+
+ /* Byte-lane control register */
+ ioaddr = devm_platform_ioremap_resource(pdev, 1);
+ if (IS_ERR(ioaddr))
+ return PTR_ERR(ioaddr);
+
+ priv->ctl_addr = ioaddr;
+ priv->priv_writel = elba_priv_writel;
+ writel(ELBA_BYTE_ENABLE_MASK(0xf), priv->ctl_addr);
+
+ return 0;
+}
+
static const struct sdhci_ops sdhci_cdns_ops = {
.set_clock = sdhci_set_clock,
.get_timeout_clock = sdhci_cdns_get_timeout_clock,
@@ -337,6 +424,13 @@ static const struct sdhci_cdns_drv_data sdhci_cdns_uniphier_drv_data = {
},
};
+static const struct sdhci_cdns_drv_data sdhci_elba_drv_data = {
+ .init = elba_drv_init,
+ .pltfm_data = {
+ .ops = &sdhci_elba_ops,
+ },
+};
+
static const struct sdhci_cdns_drv_data sdhci_cdns_drv_data = {
.pltfm_data = {
.ops = &sdhci_cdns_ops,
@@ -477,6 +571,10 @@ static const struct of_device_id sdhci_cdns_match[] = {
.compatible = "socionext,uniphier-sd4hc",
.data = &sdhci_cdns_uniphier_drv_data,
},
+ {
+ .compatible = "amd,pensando-elba-sd4hc",
+ .data = &sdhci_elba_drv_data,
+ },
{ .compatible = "cdns,sd4hc" },
{ /* sentinel */ }
};
--
2.17.1
Add support for mmc hardware reset using a reset-controller
that would need to be enabled in the device tree with
a supporting driver. The default is disabled for all
existing designs.
Signed-off-by: Brad Larson <[email protected]>
Acked-by: Adrian Hunter <[email protected]>
Reviewed-by: Philipp Zabel <[email protected]>
---
v9 changes:
- Previously patch 17/17
- Changed delay after reset_control_assert() from 9 to 3 usec
- Renamed sdhci_mmc_hw_reset() to sdhci_cdns_mmc_hw_reset()
---
drivers/mmc/host/sdhci-cadence.c | 27 +++++++++++++++++++++++++++
1 file changed, 27 insertions(+)
diff --git a/drivers/mmc/host/sdhci-cadence.c b/drivers/mmc/host/sdhci-cadence.c
index 5d1e9cef74f5..b24aa27da50c 100644
--- a/drivers/mmc/host/sdhci-cadence.c
+++ b/drivers/mmc/host/sdhci-cadence.c
@@ -12,6 +12,7 @@
#include <linux/mmc/mmc.h>
#include <linux/of.h>
#include <linux/of_device.h>
+#include <linux/reset.h>
#include "sdhci-pltfm.h"
@@ -70,6 +71,7 @@ struct sdhci_cdns_priv {
spinlock_t wrlock; /* write lock */
bool enhanced_strobe;
void (*priv_writel)(struct sdhci_cdns_priv *priv, u32 val, void __iomem *reg);
+ struct reset_control *rst_hw;
unsigned int nr_phy_params;
struct sdhci_cdns_phy_param phy_params[];
};
@@ -457,6 +459,22 @@ static void sdhci_cdns_hs400_enhanced_strobe(struct mmc_host *mmc,
SDHCI_CDNS_HRS06_MODE_MMC_HS400);
}
+static void sdhci_cdns_mmc_hw_reset(struct mmc_host *mmc)
+{
+ struct sdhci_host *host = mmc_priv(mmc);
+ struct sdhci_cdns_priv *priv = sdhci_cdns_priv(host);
+
+ dev_dbg(mmc_dev(host->mmc), "emmc hardware reset\n");
+
+ reset_control_assert(priv->rst_hw);
+ /* For eMMC, minimum is 1us but give it 3us for good measure */
+ udelay(3);
+
+ reset_control_deassert(priv->rst_hw);
+ /* For eMMC, minimum is 200us but give it 300us for good measure */
+ usleep_range(300, 1000);
+}
+
static int sdhci_cdns_probe(struct platform_device *pdev)
{
struct sdhci_host *host;
@@ -520,6 +538,15 @@ static int sdhci_cdns_probe(struct platform_device *pdev)
if (ret)
goto free;
+ if (host->mmc->caps & MMC_CAP_HW_RESET) {
+ priv->rst_hw = devm_reset_control_get_optional_exclusive(dev, NULL);
+ if (IS_ERR(priv->rst_hw))
+ return dev_err_probe(mmc_dev(host->mmc), PTR_ERR(priv->rst_hw),
+ "reset controller error\n");
+ if (priv->rst_hw)
+ host->mmc_host_ops.card_hw_reset = sdhci_cdns_mmc_hw_reset;
+ }
+
ret = sdhci_add_host(host);
if (ret)
goto free;
--
2.17.1
Move struct sdhci_pltfm_data under new struct sdhci_cdns_drv_data.
Add an init() into sdhci_cdns_drv_data for platform specific device
initialization in the device probe which is not used for existing devices.
Signed-off-by: Brad Larson <[email protected]>
Acked-by: Adrian Hunter <[email protected]>
---
v10 changes:
- New patch to provide for platform specific init() with no change
to existing designs.
---
drivers/mmc/host/sdhci-cadence.c | 32 +++++++++++++++++++++++---------
1 file changed, 23 insertions(+), 9 deletions(-)
diff --git a/drivers/mmc/host/sdhci-cadence.c b/drivers/mmc/host/sdhci-cadence.c
index 708d4297f241..c528a25f48b8 100644
--- a/drivers/mmc/host/sdhci-cadence.c
+++ b/drivers/mmc/host/sdhci-cadence.c
@@ -77,6 +77,11 @@ struct sdhci_cdns_phy_cfg {
u8 addr;
};
+struct sdhci_cdns_drv_data {
+ int (*init)(struct platform_device *pdev);
+ const struct sdhci_pltfm_data pltfm_data;
+};
+
static const struct sdhci_cdns_phy_cfg sdhci_cdns_phy_cfgs[] = {
{ "cdns,phy-input-delay-sd-highspeed", SDHCI_CDNS_PHY_DLY_SD_HS, },
{ "cdns,phy-input-delay-legacy", SDHCI_CDNS_PHY_DLY_SD_DEFAULT, },
@@ -325,13 +330,17 @@ static const struct sdhci_ops sdhci_cdns_ops = {
.set_uhs_signaling = sdhci_cdns_set_uhs_signaling,
};
-static const struct sdhci_pltfm_data sdhci_cdns_uniphier_pltfm_data = {
- .ops = &sdhci_cdns_ops,
- .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
+static const struct sdhci_cdns_drv_data sdhci_cdns_uniphier_drv_data = {
+ .pltfm_data = {
+ .ops = &sdhci_cdns_ops,
+ .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
+ },
};
-static const struct sdhci_pltfm_data sdhci_cdns_pltfm_data = {
- .ops = &sdhci_cdns_ops,
+static const struct sdhci_cdns_drv_data sdhci_cdns_drv_data = {
+ .pltfm_data = {
+ .ops = &sdhci_cdns_ops,
+ },
};
static void sdhci_cdns_hs400_enhanced_strobe(struct mmc_host *mmc,
@@ -357,7 +366,7 @@ static void sdhci_cdns_hs400_enhanced_strobe(struct mmc_host *mmc,
static int sdhci_cdns_probe(struct platform_device *pdev)
{
struct sdhci_host *host;
- const struct sdhci_pltfm_data *data;
+ const struct sdhci_cdns_drv_data *data;
struct sdhci_pltfm_host *pltfm_host;
struct sdhci_cdns_priv *priv;
struct clk *clk;
@@ -376,10 +385,10 @@ static int sdhci_cdns_probe(struct platform_device *pdev)
data = of_device_get_match_data(dev);
if (!data)
- data = &sdhci_cdns_pltfm_data;
+ data = &sdhci_cdns_drv_data;
nr_phy_params = sdhci_cdns_phy_param_count(dev->of_node);
- host = sdhci_pltfm_init(pdev, data,
+ host = sdhci_pltfm_init(pdev, &data->pltfm_data,
struct_size(priv, phy_params, nr_phy_params));
if (IS_ERR(host)) {
ret = PTR_ERR(host);
@@ -397,6 +406,11 @@ static int sdhci_cdns_probe(struct platform_device *pdev)
host->ioaddr += SDHCI_CDNS_SRS_BASE;
host->mmc_host_ops.hs400_enhanced_strobe =
sdhci_cdns_hs400_enhanced_strobe;
+ if (data->init) {
+ ret = data->init(pdev);
+ if (ret)
+ goto free;
+ }
sdhci_enable_v4_mode(host);
__sdhci_read_caps(host, &version, NULL, NULL);
@@ -461,7 +475,7 @@ static const struct dev_pm_ops sdhci_cdns_pm_ops = {
static const struct of_device_id sdhci_cdns_match[] = {
{
.compatible = "socionext,uniphier-sd4hc",
- .data = &sdhci_cdns_uniphier_pltfm_data,
+ .data = &sdhci_cdns_uniphier_drv_data,
},
{ .compatible = "cdns,sd4hc" },
{ /* sentinel */ }
--
2.17.1
The Pensando SoC controller is a SPI connected companion device
that is present in all Pensando SoC board designs. The essential
board management registers are accessed on chip select 0 with
board mgmt IO support accessed using additional chip selects.
Signed-off-by: Brad Larson <[email protected]>
---
v13 changes:
- Update include list in pensando-ctrl.c
- Change variable spi_dev to spi throughout
- Removed unneeded variable initialization, simplification of
error checks, remove extra castings, and use dev_err_probe()
- Sort the includes in amd-pensando-ctrl.h
- Updates to cleanup if there is an error in penctrl_spi_probe()
v12 changes:
- Fix gcc-12.1.0 warning:
Reported-by: kernel test robot <[email protected]>
Link: https://lore.kernel.org/oe-kbuild-all/[email protected]/
v11 changes:
- Fix the compatible to be specific 'amd,pensando-elba-ctrl'
v10 changes:
- Different driver implementation specific to this Pensando controller device.
- Moved to soc/amd directory under new name based on guidance. This driver is
of no use to any design other than all Pensando SoC based cards.
- Removed use of builtin_driver, can be built as a module.
v9 changes:
- Previously patch 14/17
- After the change to the device tree node and squashing
reset-cells into the parent simplified this to not use
any MFD API and move it to drivers/spi/pensando-sr.c.
- Change the naming to remove elba since this driver is common
for all Pensando SoC designs .
- Default yes SPI_PENSANDO_SR for ARCH_PENSANDO
---
drivers/soc/Kconfig | 1 +
drivers/soc/Makefile | 1 +
drivers/soc/amd/Kconfig | 16 ++
drivers/soc/amd/Makefile | 2 +
drivers/soc/amd/pensando-ctrl.c | 373 +++++++++++++++++++++++++
include/uapi/linux/amd-pensando-ctrl.h | 30 ++
6 files changed, 423 insertions(+)
create mode 100644 drivers/soc/amd/Kconfig
create mode 100644 drivers/soc/amd/Makefile
create mode 100644 drivers/soc/amd/pensando-ctrl.c
create mode 100644 include/uapi/linux/amd-pensando-ctrl.h
diff --git a/drivers/soc/Kconfig b/drivers/soc/Kconfig
index 4e176280113a..9e023f74e47c 100644
--- a/drivers/soc/Kconfig
+++ b/drivers/soc/Kconfig
@@ -2,6 +2,7 @@
menu "SOC (System On Chip) specific Drivers"
source "drivers/soc/actions/Kconfig"
+source "drivers/soc/amd/Kconfig"
source "drivers/soc/amlogic/Kconfig"
source "drivers/soc/apple/Kconfig"
source "drivers/soc/aspeed/Kconfig"
diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile
index 3b0f9fb3b5c8..8914530f2721 100644
--- a/drivers/soc/Makefile
+++ b/drivers/soc/Makefile
@@ -4,6 +4,7 @@
#
obj-$(CONFIG_ARCH_ACTIONS) += actions/
+obj-y += amd/
obj-y += apple/
obj-y += aspeed/
obj-$(CONFIG_ARCH_AT91) += atmel/
diff --git a/drivers/soc/amd/Kconfig b/drivers/soc/amd/Kconfig
new file mode 100644
index 000000000000..011d5339d14e
--- /dev/null
+++ b/drivers/soc/amd/Kconfig
@@ -0,0 +1,16 @@
+# SPDX-License-Identifier: GPL-2.0-only
+menu "AMD Pensando SoC drivers"
+
+config AMD_PENSANDO_CTRL
+ tristate "AMD Pensando SoC Controller"
+ depends on SPI_MASTER=y
+ depends on (ARCH_PENSANDO && OF) || COMPILE_TEST
+ default ARCH_PENSANDO
+ select REGMAP_SPI
+ select MFD_SYSCON
+ help
+ Enables AMD Pensando SoC controller device support. This is a SPI
+ attached companion device in all Pensando SoC board designs which
+ provides essential board control/status registers and management IO
+ support.
+endmenu
diff --git a/drivers/soc/amd/Makefile b/drivers/soc/amd/Makefile
new file mode 100644
index 000000000000..a2de0424f68d
--- /dev/null
+++ b/drivers/soc/amd/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0-only
+obj-$(CONFIG_AMD_PENSANDO_CTRL) += pensando-ctrl.o
diff --git a/drivers/soc/amd/pensando-ctrl.c b/drivers/soc/amd/pensando-ctrl.c
new file mode 100644
index 000000000000..6e4066564684
--- /dev/null
+++ b/drivers/soc/amd/pensando-ctrl.c
@@ -0,0 +1,373 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * AMD Pensando SoC Controller
+ *
+ * Userspace interface and reset driver support for SPI connected Pensando SoC
+ * controller device. This device is present in all Pensando SoC designs and
+ * contains board control/status registers and management IO support.
+ *
+ * Copyright 2023 Advanced Micro Devices, Inc.
+ */
+
+#include <linux/cdev.h>
+#include <linux/device.h>
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/mod_devicetable.h>
+#include <linux/module.h>
+#include <linux/mutex.h>
+#include <linux/of.h>
+#include <linux/reset-controller.h>
+#include <linux/spi/spi.h>
+#include <linux/amd-pensando-ctrl.h>
+
+struct penctrl_device {
+ struct spi_device *spi;
+ struct reset_controller_dev rcdev;
+};
+
+static DEFINE_MUTEX(spi_lock);
+static dev_t penctrl_devt;
+static struct penctrl_device *penctrl;
+static struct class *penctrl_class;
+
+static long
+penctrl_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
+{
+ void __user *in_arg = (void __user *)arg;
+ struct penctrl_device *penctrl;
+ u8 tx_buf[PENCTRL_MAX_MSG_LEN];
+ u8 rx_buf[PENCTRL_MAX_MSG_LEN];
+ struct spi_transfer t[2] = {};
+ struct penctrl_spi_xfer *msg;
+ struct spi_device *spi;
+ unsigned int num_msgs;
+ struct spi_message m;
+ u32 size;
+ int ret;
+
+ /* Check for a valid command */
+ if (_IOC_TYPE(cmd) != PENCTRL_IOC_MAGIC)
+ return -ENOTTY;
+
+ if (_IOC_NR(cmd) > PENCTRL_IOC_MAXNR)
+ return -ENOTTY;
+
+ if (_IOC_DIR(cmd) & _IOC_READ)
+ ret = !access_ok(in_arg, _IOC_SIZE(cmd));
+ else if (_IOC_DIR(cmd) & _IOC_WRITE)
+ ret = !access_ok(in_arg, _IOC_SIZE(cmd));
+
+ if (ret)
+ return -EFAULT;
+
+ /* Get a reference to the SPI device */
+ penctrl = filp->private_data;
+ if (!penctrl)
+ return -ESHUTDOWN;
+
+ spi = spi_dev_get(penctrl->spi);
+ if (!spi)
+ return -ESHUTDOWN;
+
+ /* Verify and prepare SPI message */
+ size = _IOC_SIZE(cmd);
+ num_msgs = size / sizeof(struct penctrl_spi_xfer);
+ if (size == 0 || size % sizeof(struct penctrl_spi_xfer)) {
+ ret = -EINVAL;
+ goto done;
+ }
+ msg = memdup_user((struct penctrl_spi_xfer *)arg, size);
+ if (!msg) {
+ ret = PTR_ERR(msg);
+ goto done;
+ }
+ if (msg->len > PENCTRL_MAX_MSG_LEN) {
+ ret = -EINVAL;
+ goto done;
+ }
+
+ t[0].tx_buf = tx_buf;
+ t[0].len = msg->len;
+ if (copy_from_user(tx_buf, (void __user *)msg->tx_buf, msg->len)) {
+ ret = -EFAULT;
+ goto done;
+ }
+ if (num_msgs > 1) {
+ msg++;
+ if (msg->len > PENCTRL_MAX_MSG_LEN) {
+ ret = -EINVAL;
+ goto done;
+ }
+ t[1].rx_buf = rx_buf;
+ t[1].len = msg->len;
+ }
+ spi_message_init_with_transfers(&m, t, num_msgs);
+
+ /* Perform the transfer */
+ mutex_lock(&spi_lock);
+ ret = spi_sync(spi, &m);
+ mutex_unlock(&spi_lock);
+
+ if (ret || (num_msgs == 1))
+ goto done;
+
+ if (copy_to_user((void __user *)msg->rx_buf, rx_buf, msg->len))
+ ret = -EFAULT;
+
+done:
+ spi_dev_put(spi);
+ return ret;
+}
+
+static int penctrl_open(struct inode *inode, struct file *filp)
+{
+ struct spi_device *spi;
+ u8 current_cs;
+
+ if (!penctrl)
+ return -ENODEV;
+
+ filp->private_data = penctrl;
+ current_cs = iminor(inode);
+ spi = penctrl->spi;
+ spi->chip_select = current_cs;
+ spi->cs_gpiod = spi->controller->cs_gpiods[current_cs];
+ spi_setup(spi);
+ return stream_open(inode, filp);
+}
+
+static int penctrl_release(struct inode *inode, struct file *filp)
+{
+ filp->private_data = NULL;
+ return 0;
+}
+
+static const struct file_operations penctrl_fops = {
+ .owner = THIS_MODULE,
+ .unlocked_ioctl = penctrl_ioctl,
+ .open = penctrl_open,
+ .release = penctrl_release,
+ .llseek = no_llseek,
+};
+
+static int penctrl_regs_read(struct penctrl_device *penctrl, u32 reg, u32 *val)
+{
+ struct spi_device *spi = penctrl->spi;
+ struct spi_transfer t[2] = {};
+ struct spi_message m;
+ u8 txbuf[3];
+ u8 rxbuf[1];
+ int ret;
+
+ txbuf[0] = PENCTRL_SPI_CMD_REGRD;
+ txbuf[1] = reg;
+ txbuf[2] = 0;
+ t[0].tx_buf = txbuf;
+ t[0].len = 3;
+
+ rxbuf[0] = 0;
+ t[1].rx_buf = rxbuf;
+ t[1].len = 1;
+
+ spi_message_init_with_transfers(&m, t, ARRAY_SIZE(t));
+ ret = spi_sync(spi, &m);
+ if (ret == 0)
+ *val = rxbuf[0];
+
+ return ret;
+}
+
+static int penctrl_regs_write(struct penctrl_device *penctrl, u32 reg, u32 val)
+{
+ struct spi_device *spi = penctrl->spi;
+ struct spi_transfer t;
+ struct spi_message m;
+ u8 txbuf[4];
+
+ txbuf[0] = PENCTRL_SPI_CMD_REGWR;
+ txbuf[1] = reg;
+ txbuf[2] = val;
+ txbuf[3] = 0;
+
+ t.tx_buf = txbuf;
+ t.len = 4;
+ spi_message_init_with_transfers(&m, &t, 1);
+ return spi_sync(spi, &m);
+}
+
+static int penctrl_reset_assert(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+ struct penctrl_device *penctrl =
+ container_of(rcdev, struct penctrl_device, rcdev);
+ struct spi_device *spi = penctrl->spi;
+ unsigned int val;
+ int ret;
+
+ mutex_lock(&spi_lock);
+ spi->chip_select = 0;
+ spi->cs_gpiod = spi->controller->cs_gpiods[0];
+ spi_setup(spi);
+ ret = penctrl_regs_read(penctrl, PENCTRL_REG_CTRL0, &val);
+ if (ret) {
+ dev_err(&spi->dev, "error reading ctrl0 reg\n");
+ goto done;
+ }
+
+ val |= BIT(6);
+ ret = penctrl_regs_write(penctrl, PENCTRL_REG_CTRL0, val);
+ if (ret)
+ dev_err(&spi->dev, "error writing ctrl0 reg\n");
+
+done:
+ mutex_unlock(&spi_lock);
+ return ret;
+}
+
+static int penctrl_reset_deassert(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+ struct penctrl_device *penctrl =
+ container_of(rcdev, struct penctrl_device, rcdev);
+ struct spi_device *spi = penctrl->spi;
+ unsigned int val;
+ int ret;
+
+ mutex_lock(&spi_lock);
+ spi->chip_select = 0;
+ spi->cs_gpiod = spi->controller->cs_gpiods[0];
+ spi_setup(spi);
+ ret = penctrl_regs_read(penctrl, PENCTRL_REG_CTRL0, &val);
+ if (ret) {
+ dev_err(&spi->dev, "error reading ctrl0 reg\n");
+ goto done;
+ }
+
+ val &= ~BIT(6);
+ ret = penctrl_regs_write(penctrl, PENCTRL_REG_CTRL0, val);
+ if (ret)
+ dev_err(&spi->dev, "error writing ctrl0 reg\n");
+
+done:
+ mutex_unlock(&spi_lock);
+ return ret;
+}
+
+static const struct reset_control_ops penctrl_reset_ops = {
+ .assert = penctrl_reset_assert,
+ .deassert = penctrl_reset_deassert,
+};
+
+static int penctrl_spi_probe(struct spi_device *spi)
+{
+ struct device *dev;
+ struct cdev *cdev;
+ u32 num_cs;
+ int ret;
+ u32 cs;
+
+ ret = device_property_read_u32(spi->dev.parent, "num-cs", &num_cs);
+ if (ret)
+ return dev_err_probe(&spi->dev, ret,
+ "number of chip-selects not defined\n");
+
+ ret = alloc_chrdev_region(&penctrl_devt, 0, num_cs, "penctrl");
+ if (ret)
+ return dev_err_probe(&spi->dev, ret,
+ "failed to alloc chrdev region\n");
+
+ penctrl_class = class_create(THIS_MODULE, "penctrl");
+ if (IS_ERR(penctrl_class)) {
+ ret = dev_err_probe(&spi->dev, PTR_ERR(penctrl_class),
+ "failed to create class\n");
+ goto unregister_chrdev;
+ }
+
+ cdev = cdev_alloc();
+ if (!cdev) {
+ ret = dev_err_probe(&spi->dev, -ENOMEM,
+ "allocation of cdev failed\n");
+ goto destroy_class;
+ }
+ cdev->owner = THIS_MODULE;
+ cdev_init(cdev, &penctrl_fops);
+
+ ret = cdev_add(cdev, penctrl_devt, num_cs);
+ if (ret) {
+ ret = dev_err_probe(&spi->dev, ret,
+ "register of cdev failed\n");
+ goto free_cdev;
+ }
+
+ /* Allocate driver data */
+ penctrl = kzalloc(sizeof(*penctrl), GFP_KERNEL);
+ if (!penctrl) {
+ ret = -ENOMEM;
+ goto free_cdev;
+ }
+ penctrl->spi = spi;
+ mutex_init(&spi_lock);
+
+ /* Create a device for each chip select */
+ for (cs = 0; cs < num_cs; cs++) {
+ dev = device_create(penctrl_class,
+ &spi->dev,
+ MKDEV(MAJOR(penctrl_devt), cs),
+ penctrl,
+ "penctrl0.%d",
+ cs);
+ if (IS_ERR(dev)) {
+ ret = dev_err_probe(&spi->dev, PTR_ERR(dev),
+ "error creating device\n");
+ goto destroy_device;
+ }
+ dev_dbg(&spi->dev, "created device major %u, minor %d\n",
+ MAJOR(penctrl_devt), cs);
+ }
+
+ /* Register emmc hardware reset */
+ penctrl->rcdev.nr_resets = 1;
+ penctrl->rcdev.owner = THIS_MODULE;
+ penctrl->rcdev.dev = &spi->dev;
+ penctrl->rcdev.ops = &penctrl_reset_ops;
+ penctrl->rcdev.of_node = spi->dev.of_node;
+ device_set_node(&spi->dev, dev_fwnode(dev));
+
+ ret = reset_controller_register(&penctrl->rcdev);
+ if (ret)
+ return dev_err_probe(&spi->dev, ret,
+ "failed to register reset controller\n");
+ return 0;
+
+destroy_device:
+ for (cs = 0; cs < num_cs; cs++)
+ device_destroy(penctrl_class, MKDEV(MAJOR(penctrl_devt), cs));
+ kfree(penctrl);
+free_cdev:
+ cdev_del(cdev);
+destroy_class:
+ class_destroy(penctrl_class);
+unregister_chrdev:
+ unregister_chrdev(MAJOR(penctrl_devt), "penctrl");
+
+ return ret;
+}
+
+static const struct of_device_id penctrl_dt_match[] = {
+ { .compatible = "amd,pensando-elba-ctrl" },
+ { /* sentinel */ }
+};
+
+static struct spi_driver penctrl_spi_driver = {
+ .probe = penctrl_spi_probe,
+ .driver = {
+ .name = "pensando-ctrl",
+ .of_match_table = penctrl_dt_match,
+ },
+};
+module_spi_driver(penctrl_spi_driver);
+
+MODULE_AUTHOR("Brad Larson <[email protected]>");
+MODULE_DESCRIPTION("AMD Pensando SoC Controller via SPI");
+MODULE_LICENSE("GPL");
diff --git a/include/uapi/linux/amd-pensando-ctrl.h b/include/uapi/linux/amd-pensando-ctrl.h
new file mode 100644
index 000000000000..2508a1aef22c
--- /dev/null
+++ b/include/uapi/linux/amd-pensando-ctrl.h
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
+/*
+ * Userspace interface for /dev/penctrl
+ *
+ * This file can be used by applications that need to communicate
+ * with the AMD Pensando SoC controller device via the ioctl interface.
+ */
+#ifndef _UAPI_LINUX_AMD_PENSANDO_CTRL_H
+#define _UAPI_LINUX_AMD_PENSANDO_CTRL_H
+
+#include <linux/ioctl.h>
+#include <linux/types.h>
+
+#define PENCTRL_SPI_CMD_REGRD 0x0b
+#define PENCTRL_SPI_CMD_REGWR 0x02
+#define PENCTRL_IOC_MAGIC 'k'
+#define PENCTRL_IOC_MAXNR 0
+#define PENCTRL_MAX_MSG_LEN 16
+#define PENCTRL_MAX_REG 0xff
+#define PENCTRL_REG_CTRL0 0x10
+
+struct penctrl_spi_xfer {
+ __u64 tx_buf;
+ __u64 rx_buf;
+ __u32 len;
+ __u32 speed_hz;
+ __u64 compat;
+};
+
+#endif /* _UAPI_LINUX_AMD_PENSANDO_CTRL_H */
--
2.17.1
On Mon, Apr 10, 2023 at 9:48 PM Brad Larson <[email protected]> wrote:
>
> The Pensando SoC controller is a SPI connected companion device
> that is present in all Pensando SoC board designs. The essential
> board management registers are accessed on chip select 0 with
> board mgmt IO support accessed using additional chip selects.
...
> +#include <linux/cdev.h>
> +#include <linux/device.h>
> +#include <linux/err.h>
> +#include <linux/init.h>
> +#include <linux/mod_devicetable.h>
> +#include <linux/module.h>
> +#include <linux/mutex.h>
> +#include <linux/of.h>
> +#include <linux/reset-controller.h>
> +#include <linux/spi/spi.h>
+ Blank line?
> +#include <linux/amd-pensando-ctrl.h>
...
> +struct penctrl_device {
> + struct spi_device *spi;
> + struct reset_controller_dev rcdev;
Try to swap them and check if the code will be smaller (it depends on
how often one or another member is being used),
> +};
...
> +static long
> +penctrl_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
> +{
> + void __user *in_arg = (void __user *)arg;
> + struct penctrl_device *penctrl;
> + u8 tx_buf[PENCTRL_MAX_MSG_LEN];
> + u8 rx_buf[PENCTRL_MAX_MSG_LEN];
> + struct spi_transfer t[2] = {};
> + struct penctrl_spi_xfer *msg;
> + struct spi_device *spi;
> + unsigned int num_msgs;
> + struct spi_message m;
> + u32 size;
> + int ret;
> +
> + /* Check for a valid command */
> + if (_IOC_TYPE(cmd) != PENCTRL_IOC_MAGIC)
> + return -ENOTTY;
> +
> + if (_IOC_NR(cmd) > PENCTRL_IOC_MAXNR)
> + return -ENOTTY;
> +
> + if (_IOC_DIR(cmd) & _IOC_READ)
> + ret = !access_ok(in_arg, _IOC_SIZE(cmd));
> + else if (_IOC_DIR(cmd) & _IOC_WRITE)
> + ret = !access_ok(in_arg, _IOC_SIZE(cmd));
> +
Unneeded blank line.
> + if (ret)
> + return -EFAULT;
But it seems you can actually rewrite above in less lines:
if ((_IOC_DIR(cmd) & _IOC_READ) && !access_ok(in_arg, _IOC_SIZE(cmd)))
return -EFAULT;
if ((_IOC_DIR(cmd) & _IOC_WRITE) && !access_ok(in_arg, _IOC_SIZE(cmd)))
return -EFAULT;
> + /* Get a reference to the SPI device */
> + penctrl = filp->private_data;
> + if (!penctrl)
> + return -ESHUTDOWN;
> +
> + spi = spi_dev_get(penctrl->spi);
> + if (!spi)
> + return -ESHUTDOWN;
> +
> + /* Verify and prepare SPI message */
> + size = _IOC_SIZE(cmd);
> + num_msgs = size / sizeof(struct penctrl_spi_xfer);
> + if (size == 0 || size % sizeof(struct penctrl_spi_xfer)) {
> + ret = -EINVAL;
> + goto done;
> + }
> + msg = memdup_user((struct penctrl_spi_xfer *)arg, size);
> + if (!msg) {
> + ret = PTR_ERR(msg);
This is strange.
> + goto done;
> + }
> + if (msg->len > PENCTRL_MAX_MSG_LEN) {
> + ret = -EINVAL;
> + goto done;
> + }
> +
> + t[0].tx_buf = tx_buf;
> + t[0].len = msg->len;
> + if (copy_from_user(tx_buf, (void __user *)msg->tx_buf, msg->len)) {
> + ret = -EFAULT;
> + goto done;
> + }
> + if (num_msgs > 1) {
> + msg++;
> + if (msg->len > PENCTRL_MAX_MSG_LEN) {
> + ret = -EINVAL;
> + goto done;
> + }
> + t[1].rx_buf = rx_buf;
> + t[1].len = msg->len;
> + }
> + spi_message_init_with_transfers(&m, t, num_msgs);
It seems there is no validation for the messages 3+.
> + /* Perform the transfer */
> + mutex_lock(&spi_lock);
> + ret = spi_sync(spi, &m);
> + mutex_unlock(&spi_lock);
> +
> + if (ret || (num_msgs == 1))
> + goto done;
> +
> + if (copy_to_user((void __user *)msg->rx_buf, rx_buf, msg->len))
> + ret = -EFAULT;
> +done:
out_unlock: ?
> + spi_dev_put(spi);
> + return ret;
> +}
> +
> +static int penctrl_open(struct inode *inode, struct file *filp)
> +{
> + struct spi_device *spi;
> + u8 current_cs;
> + if (!penctrl)
> + return -ENODEV;
Is it possible?
> + filp->private_data = penctrl;
> + current_cs = iminor(inode);
> + spi = penctrl->spi;
> + spi->chip_select = current_cs;
> + spi->cs_gpiod = spi->controller->cs_gpiods[current_cs];
Hmm... Why do you need this one? Isn't it a job of SPI core?
> + spi_setup(spi);
> + return stream_open(inode, filp);
> +}
> +static int penctrl_regs_read(struct penctrl_device *penctrl, u32 reg, u32 *val)
> +{
> + struct spi_device *spi = penctrl->spi;
> + struct spi_transfer t[2] = {};
> + struct spi_message m;
> + u8 txbuf[3];
> + u8 rxbuf[1];
> + int ret;
> +
> + txbuf[0] = PENCTRL_SPI_CMD_REGRD;
> + txbuf[1] = reg;
> + txbuf[2] = 0;
> + t[0].tx_buf = txbuf;
> + t[0].len = 3;
sizeof(txbuf) ?
> + rxbuf[0] = 0;
> + t[1].rx_buf = rxbuf;
> + t[1].len = 1;
sizeof(rxbuf) ?
> + spi_message_init_with_transfers(&m, t, ARRAY_SIZE(t));
> + ret = spi_sync(spi, &m);
> + if (ret == 0)
> + *val = rxbuf[0];
> +
> + return ret;
> +}
> +
> +static int penctrl_regs_write(struct penctrl_device *penctrl, u32 reg, u32 val)
> +{
> + struct spi_device *spi = penctrl->spi;
> + struct spi_transfer t;
> + struct spi_message m;
> + u8 txbuf[4];
> +
> + txbuf[0] = PENCTRL_SPI_CMD_REGWR;
> + txbuf[1] = reg;
> + txbuf[2] = val;
> + txbuf[3] = 0;
> +
> + t.tx_buf = txbuf;
> + t.len = 4;
sizeof(txbuf) ?
> + spi_message_init_with_transfers(&m, &t, 1);
> + return spi_sync(spi, &m);
> +}
> +
> +static int penctrl_reset_assert(struct reset_controller_dev *rcdev,
> + unsigned long id)
> +{
> + struct penctrl_device *penctrl =
> + container_of(rcdev, struct penctrl_device, rcdev);
> + struct spi_device *spi = penctrl->spi;
> + unsigned int val;
> + int ret;
> +
> + mutex_lock(&spi_lock);
> + spi->chip_select = 0;
> + spi->cs_gpiod = spi->controller->cs_gpiods[0];
> + spi_setup(spi);
> + ret = penctrl_regs_read(penctrl, PENCTRL_REG_CTRL0, &val);
> + if (ret) {
> + dev_err(&spi->dev, "error reading ctrl0 reg\n");
> + goto done;
> + }
> +
> + val |= BIT(6);
> + ret = penctrl_regs_write(penctrl, PENCTRL_REG_CTRL0, val);
> + if (ret)
> + dev_err(&spi->dev, "error writing ctrl0 reg\n");
> +done:
out_unlock: ?
> + mutex_unlock(&spi_lock);
> + return ret;
> +}
> +
> +static int penctrl_reset_deassert(struct reset_controller_dev *rcdev,
> + unsigned long id)
> +{
> + struct penctrl_device *penctrl =
> + container_of(rcdev, struct penctrl_device, rcdev);
> + struct spi_device *spi = penctrl->spi;
> + unsigned int val;
> + int ret;
> +
> + mutex_lock(&spi_lock);
> + spi->chip_select = 0;
> + spi->cs_gpiod = spi->controller->cs_gpiods[0];
> + spi_setup(spi);
> + ret = penctrl_regs_read(penctrl, PENCTRL_REG_CTRL0, &val);
> + if (ret) {
> + dev_err(&spi->dev, "error reading ctrl0 reg\n");
> + goto done;
> + }
> +
> + val &= ~BIT(6);
> + ret = penctrl_regs_write(penctrl, PENCTRL_REG_CTRL0, val);
> + if (ret)
> + dev_err(&spi->dev, "error writing ctrl0 reg\n");
> +done:
out_unlock: ?
> + mutex_unlock(&spi_lock);
> + return ret;
> +}
> +static int penctrl_spi_probe(struct spi_device *spi)
> +{
> + struct device *dev;
> + struct cdev *cdev;
> + u32 num_cs;
> + int ret;
> + u32 cs;
> +
> + ret = device_property_read_u32(spi->dev.parent, "num-cs", &num_cs);
> + if (ret)
> + return dev_err_probe(&spi->dev, ret,
> + "number of chip-selects not defined\n");
> +
> + ret = alloc_chrdev_region(&penctrl_devt, 0, num_cs, "penctrl");
> + if (ret)
> + return dev_err_probe(&spi->dev, ret,
> + "failed to alloc chrdev region\n");
> +
> + penctrl_class = class_create(THIS_MODULE, "penctrl");
> + if (IS_ERR(penctrl_class)) {
> + ret = dev_err_probe(&spi->dev, PTR_ERR(penctrl_class),
> + "failed to create class\n");
> + goto unregister_chrdev;
> + }
> +
> + cdev = cdev_alloc();
> + if (!cdev) {
> + ret = dev_err_probe(&spi->dev, -ENOMEM,
> + "allocation of cdev failed\n");
> + goto destroy_class;
> + }
> + cdev->owner = THIS_MODULE;
> + cdev_init(cdev, &penctrl_fops);
> +
> + ret = cdev_add(cdev, penctrl_devt, num_cs);
> + if (ret) {
> + ret = dev_err_probe(&spi->dev, ret,
> + "register of cdev failed\n");
> + goto free_cdev;
> + }
> +
> + /* Allocate driver data */
> + penctrl = kzalloc(sizeof(*penctrl), GFP_KERNEL);
> + if (!penctrl) {
> + ret = -ENOMEM;
> + goto free_cdev;
> + }
> + penctrl->spi = spi;
> + mutex_init(&spi_lock);
> +
> + /* Create a device for each chip select */
> + for (cs = 0; cs < num_cs; cs++) {
> + dev = device_create(penctrl_class,
> + &spi->dev,
> + MKDEV(MAJOR(penctrl_devt), cs),
> + penctrl,
> + "penctrl0.%d",
> + cs);
> + if (IS_ERR(dev)) {
> + ret = dev_err_probe(&spi->dev, PTR_ERR(dev),
> + "error creating device\n");
> + goto destroy_device;
> + }
> + dev_dbg(&spi->dev, "created device major %u, minor %d\n",
> + MAJOR(penctrl_devt), cs);
> + }
> +
> + /* Register emmc hardware reset */
> + penctrl->rcdev.nr_resets = 1;
> + penctrl->rcdev.owner = THIS_MODULE;
> + penctrl->rcdev.dev = &spi->dev;
> + penctrl->rcdev.ops = &penctrl_reset_ops;
> + penctrl->rcdev.of_node = spi->dev.of_node;
Either redundant or wrong. Shouldn't you first have the firmware node
to be set for spi->dev?
> + device_set_node(&spi->dev, dev_fwnode(dev));
> +
> + ret = reset_controller_register(&penctrl->rcdev);
> + if (ret)
> + return dev_err_probe(&spi->dev, ret,
> + "failed to register reset controller\n");
> + return 0;
> +
> +destroy_device:
> + for (cs = 0; cs < num_cs; cs++)
> + device_destroy(penctrl_class, MKDEV(MAJOR(penctrl_devt), cs));
> + kfree(penctrl);
> +free_cdev:
> + cdev_del(cdev);
> +destroy_class:
> + class_destroy(penctrl_class);
> +unregister_chrdev:
> + unregister_chrdev(MAJOR(penctrl_devt), "penctrl");
> +
> + return ret;
> +}
...
> +++ b/include/uapi/linux/amd-pensando-ctrl.h
> @@ -0,0 +1,30 @@
> +/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
> +/*
> + * Userspace interface for /dev/penctrl
> + *
> + * This file can be used by applications that need to communicate
> + * with the AMD Pensando SoC controller device via the ioctl interface.
> + */
> +#ifndef _UAPI_LINUX_AMD_PENSANDO_CTRL_H
> +#define _UAPI_LINUX_AMD_PENSANDO_CTRL_H
> +#include <linux/ioctl.h>
Not used header.
> +#include <linux/types.h>
> +
> +#define PENCTRL_SPI_CMD_REGRD 0x0b
> +#define PENCTRL_SPI_CMD_REGWR 0x02
> +#define PENCTRL_IOC_MAGIC 'k'
> +#define PENCTRL_IOC_MAXNR 0
> +#define PENCTRL_MAX_MSG_LEN 16
> +#define PENCTRL_MAX_REG 0xff
> +#define PENCTRL_REG_CTRL0 0x10
> +
> +struct penctrl_spi_xfer {
> + __u64 tx_buf;
> + __u64 rx_buf;
> + __u32 len;
> + __u32 speed_hz;
> + __u64 compat;
> +};
> +
> +#endif /* _UAPI_LINUX_AMD_PENSANDO_CTRL_H */
--
With Best Regards,
Andy Shevchenko
On Mon, Apr 10, 2023 at 11:45:19AM -0700, Brad Larson wrote:
> Add AMD Pensando common and Elba SoC specific device nodes
>
> Signed-off-by: Brad Larson <[email protected]>
> ---
>
> v11 changes:
> - Delete reset-names
> - Fix spi0 compatible to be specific 'amd,pensando-elba-ctrl'
>
> v9 changes:
> - Single node for spi0 system-controller and squash
> the reset-controller child into parent
Have you run this thru 'make dtbs_check'? I see at least one issue that
should report.
> ---
> arch/arm64/boot/dts/amd/Makefile | 1 +
> arch/arm64/boot/dts/amd/elba-16core.dtsi | 189 +++++++++++++++++
> arch/arm64/boot/dts/amd/elba-asic-common.dtsi | 80 ++++++++
> arch/arm64/boot/dts/amd/elba-asic.dts | 28 +++
> arch/arm64/boot/dts/amd/elba-flash-parts.dtsi | 106 ++++++++++
> arch/arm64/boot/dts/amd/elba.dtsi | 191 ++++++++++++++++++
> 6 files changed, 595 insertions(+)
> create mode 100644 arch/arm64/boot/dts/amd/elba-16core.dtsi
> create mode 100644 arch/arm64/boot/dts/amd/elba-asic-common.dtsi
> create mode 100644 arch/arm64/boot/dts/amd/elba-asic.dts
> create mode 100644 arch/arm64/boot/dts/amd/elba-flash-parts.dtsi
> create mode 100644 arch/arm64/boot/dts/amd/elba.dtsi
>
> diff --git a/arch/arm64/boot/dts/amd/Makefile b/arch/arm64/boot/dts/amd/Makefile
> index 68103a8b0ef5..8502cc2afbc5 100644
> --- a/arch/arm64/boot/dts/amd/Makefile
> +++ b/arch/arm64/boot/dts/amd/Makefile
> @@ -1,2 +1,3 @@
> # SPDX-License-Identifier: GPL-2.0
> +dtb-$(CONFIG_ARCH_PENSANDO) += elba-asic.dtb
> dtb-$(CONFIG_ARCH_SEATTLE) += amd-overdrive-rev-b0.dtb amd-overdrive-rev-b1.dtb
> diff --git a/arch/arm64/boot/dts/amd/elba-16core.dtsi b/arch/arm64/boot/dts/amd/elba-16core.dtsi
> new file mode 100644
> index 000000000000..37aadd442db8
> --- /dev/null
> +++ b/arch/arm64/boot/dts/amd/elba-16core.dtsi
> @@ -0,0 +1,189 @@
> +// SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
> +/*
> + * Copyright 2020-2022 Advanced Micro Devices, Inc.
> + */
> +
> +/ {
> + cpus {
> + #address-cells = <2>;
> + #size-cells = <0>;
> +
> + cpu-map {
> + cluster0 {
> + core0 { cpu = <&cpu0>; };
> + core1 { cpu = <&cpu1>; };
> + core2 { cpu = <&cpu2>; };
> + core3 { cpu = <&cpu3>; };
> + };
> +
> + cluster1 {
> + core0 { cpu = <&cpu4>; };
> + core1 { cpu = <&cpu5>; };
> + core2 { cpu = <&cpu6>; };
> + core3 { cpu = <&cpu7>; };
> + };
> +
> + cluster2 {
> + core0 { cpu = <&cpu8>; };
> + core1 { cpu = <&cpu9>; };
> + core2 { cpu = <&cpu10>; };
> + core3 { cpu = <&cpu11>; };
> + };
> +
> + cluster3 {
> + core0 { cpu = <&cpu12>; };
> + core1 { cpu = <&cpu13>; };
> + core2 { cpu = <&cpu14>; };
> + core3 { cpu = <&cpu15>; };
> + };
> + };
> +
> + /* CLUSTER 0 */
> + cpu0: cpu@0 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a72";
> + reg = <0 0x0>;
> + next-level-cache = <&l2_0>;
> + enable-method = "psci";
> + };
> +
> + cpu1: cpu@1 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a72";
> + reg = <0 0x1>;
> + next-level-cache = <&l2_0>;
> + enable-method = "psci";
> + };
> +
> + cpu2: cpu@2 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a72";
> + reg = <0 0x2>;
> + next-level-cache = <&l2_0>;
> + enable-method = "psci";
> + };
> +
> + cpu3: cpu@3 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a72";
> + reg = <0 0x3>;
> + next-level-cache = <&l2_0>;
> + enable-method = "psci";
> + };
> +
> + l2_0: l2-cache0 {
> + compatible = "cache";
> + };
> +
> + /* CLUSTER 1 */
> + cpu4: cpu@100 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a72";
> + reg = <0 0x100>;
> + next-level-cache = <&l2_1>;
> + enable-method = "psci";
> + };
> +
> + cpu5: cpu@101 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a72";
> + reg = <0 0x101>;
> + next-level-cache = <&l2_1>;
> + enable-method = "psci";
> + };
> +
> + cpu6: cpu@102 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a72";
> + reg = <0 0x102>;
> + next-level-cache = <&l2_1>;
> + enable-method = "psci";
> + };
> +
> + cpu7: cpu@103 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a72";
> + reg = <0 0x103>;
> + next-level-cache = <&l2_1>;
> + enable-method = "psci";
> + };
> +
> + l2_1: l2-cache1 {
> + compatible = "cache";
This is missing properties. If you don't see warnings, update dtschema.
Rob
Hi Rob,
On Tue, Apr 11, 2023 at 08:55:18, Rob Herring wrote:
> On Mon, Apr 10, 2023 at 11:45:19AM -0700, Brad Larson wrote:
>> Add AMD Pensando common and Elba SoC specific device nodes
>>
>> Signed-off-by: Brad Larson <[email protected]>
>> ---
>>
>> v11 changes:
>> - Delete reset-names
>> - Fix spi0 compatible to be specific 'amd,pensando-elba-ctrl'
>>
>> v9 changes:
>> - Single node for spi0 system-controller and squash
>> the reset-controller child into parent
>
> Have you run this thru 'make dtbs_check'? I see at least one issue that
> should report.
Yes and no warnings or errors with these checks
make ARCH=arm64 dtbs_check
make DT_CHECKER_FLAGS=-m dt_binding_check
but I did find a couple relevant packages have been updated
dtschema Version: 2023.1 ==> 2023.4
yamllint Version: 1.26.3 ==> 1.30.0
and then running again I get below
$ make ARCH=arm64 dtbs_check
...
/home/brad/linux.v13/arch/arm64/boot/dts/amd/elba-asic.dtb: l2-cache0: 'cache-level' is a required property
/home/brad/linux.v13/arch/arm64/boot/dts/amd/elba-asic.dtb: l2-cache0: 'cache-level' is a required property
/home/brad/linux.v13/arch/arm64/boot/dts/amd/elba-asic.dtb: l2-cache0: 'cache-unified' is a required property
/home/brad/linux.v13/arch/arm64/boot/dts/amd/elba-asic.dtb: l2-cache1: 'cache-level' is a required property
/home/brad/linux.v13/arch/arm64/boot/dts/amd/elba-asic.dtb: l2-cache1: 'cache-level' is a required property
/home/brad/linux.v13/arch/arm64/boot/dts/amd/elba-asic.dtb: l2-cache1: 'cache-unified' is a required property
/home/brad/linux.v13/arch/arm64/boot/dts/amd/elba-asic.dtb: l2-cache2: 'cache-level' is a required property
/home/brad/linux.v13/arch/arm64/boot/dts/amd/elba-asic.dtb: l2-cache2: 'cache-level' is a required property
/home/brad/linux.v13/arch/arm64/boot/dts/amd/elba-asic.dtb: l2-cache2: 'cache-unified' is a required property
/home/brad/linux.v13/arch/arm64/boot/dts/amd/elba-asic.dtb: l2-cache3: 'cache-level' is a required property
/home/brad/linux.v13/arch/arm64/boot/dts/amd/elba-asic.dtb: l2-cache3: 'cache-level' is a required property
/home/brad/linux.v13/arch/arm64/boot/dts/amd/elba-asic.dtb: l2-cache3: 'cache-unified' is a required property
I'll fix this in the next spin.
Regards,
Brad
On Mon, 10 Apr 2023 at 20:47, Brad Larson <[email protected]> wrote:
>
> SoCs with device specific Cadence implementation, such as setting
> byte-enables before the write, need to override writel(). Add a
> callback where the default is writel() for all existing chips.
>
> Signed-off-by: Brad Larson <[email protected]>
> Acked-by: Adrian Hunter <[email protected]>
Applied for next, thanks!
Kind regards
Uffe
> ---
>
> v10 changes:
> - The 1st patch adding private writel() is unchanged. The 2nd patch is split
> into two patches to provide for device specific init in one patch with no
> effect on existing designs. Then add the pensando support into the next patch.
> Then the 4th patch is mmc hardware reset support which is unchanged.
>
> v9 changes:
> - No change to this patch but as some patches are deleted and this is
> a respin the three successive patches to sdhci-cadence.c are
> patches 12, 13, and 14 which do the following:
>
> 1. Add ability for Cadence specific design to have priv writel().
> 2. Add Elba SoC support that requires its own priv writel() for
> byte-lane control .
> 3. Add support for mmc hardware reset.
>
> ---
> drivers/mmc/host/sdhci-cadence.c | 18 +++++++++++++-----
> 1 file changed, 13 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/mmc/host/sdhci-cadence.c b/drivers/mmc/host/sdhci-cadence.c
> index 6f2de54a5987..708d4297f241 100644
> --- a/drivers/mmc/host/sdhci-cadence.c
> +++ b/drivers/mmc/host/sdhci-cadence.c
> @@ -67,6 +67,7 @@ struct sdhci_cdns_phy_param {
> struct sdhci_cdns_priv {
> void __iomem *hrs_addr;
> bool enhanced_strobe;
> + void (*priv_writel)(struct sdhci_cdns_priv *priv, u32 val, void __iomem *reg);
> unsigned int nr_phy_params;
> struct sdhci_cdns_phy_param phy_params[];
> };
> @@ -90,6 +91,12 @@ static const struct sdhci_cdns_phy_cfg sdhci_cdns_phy_cfgs[] = {
> { "cdns,phy-dll-delay-strobe", SDHCI_CDNS_PHY_DLY_STROBE, },
> };
>
> +static inline void cdns_writel(struct sdhci_cdns_priv *priv, u32 val,
> + void __iomem *reg)
> +{
> + writel(val, reg);
> +}
> +
> static int sdhci_cdns_write_phy_reg(struct sdhci_cdns_priv *priv,
> u8 addr, u8 data)
> {
> @@ -104,17 +111,17 @@ static int sdhci_cdns_write_phy_reg(struct sdhci_cdns_priv *priv,
>
> tmp = FIELD_PREP(SDHCI_CDNS_HRS04_WDATA, data) |
> FIELD_PREP(SDHCI_CDNS_HRS04_ADDR, addr);
> - writel(tmp, reg);
> + priv->priv_writel(priv, tmp, reg);
>
> tmp |= SDHCI_CDNS_HRS04_WR;
> - writel(tmp, reg);
> + priv->priv_writel(priv, tmp, reg);
>
> ret = readl_poll_timeout(reg, tmp, tmp & SDHCI_CDNS_HRS04_ACK, 0, 10);
> if (ret)
> return ret;
>
> tmp &= ~SDHCI_CDNS_HRS04_WR;
> - writel(tmp, reg);
> + priv->priv_writel(priv, tmp, reg);
>
> ret = readl_poll_timeout(reg, tmp, !(tmp & SDHCI_CDNS_HRS04_ACK),
> 0, 10);
> @@ -191,7 +198,7 @@ static void sdhci_cdns_set_emmc_mode(struct sdhci_cdns_priv *priv, u32 mode)
> tmp = readl(priv->hrs_addr + SDHCI_CDNS_HRS06);
> tmp &= ~SDHCI_CDNS_HRS06_MODE;
> tmp |= FIELD_PREP(SDHCI_CDNS_HRS06_MODE, mode);
> - writel(tmp, priv->hrs_addr + SDHCI_CDNS_HRS06);
> + priv->priv_writel(priv, tmp, priv->hrs_addr + SDHCI_CDNS_HRS06);
> }
>
> static u32 sdhci_cdns_get_emmc_mode(struct sdhci_cdns_priv *priv)
> @@ -223,7 +230,7 @@ static int sdhci_cdns_set_tune_val(struct sdhci_host *host, unsigned int val)
> */
> for (i = 0; i < 2; i++) {
> tmp |= SDHCI_CDNS_HRS06_TUNE_UP;
> - writel(tmp, reg);
> + priv->priv_writel(priv, tmp, reg);
>
> ret = readl_poll_timeout(reg, tmp,
> !(tmp & SDHCI_CDNS_HRS06_TUNE_UP),
> @@ -386,6 +393,7 @@ static int sdhci_cdns_probe(struct platform_device *pdev)
> priv->nr_phy_params = nr_phy_params;
> priv->hrs_addr = host->ioaddr;
> priv->enhanced_strobe = false;
> + priv->priv_writel = cdns_writel;
> host->ioaddr += SDHCI_CDNS_SRS_BASE;
> host->mmc_host_ops.hs400_enhanced_strobe =
> sdhci_cdns_hs400_enhanced_strobe;
> --
> 2.17.1
>
On Mon, 10 Apr 2023 at 20:47, Brad Larson <[email protected]> wrote:
>
> Add support for AMD Pensando Elba SoC which explicitly
> controls byte-lane enables on writes.
>
> Select MMC_SDHCI_IO_ACCESSORS for MMC_SDHCI_CADENCE which
> allows Elba SoC sdhci_elba_ops to overwrite the SDHCI
> IO memory accessors
>
> Signed-off-by: Brad Larson <[email protected]>
> Acked-by: Adrian Hunter <[email protected]>
Applied for next, thanks!
Kind regards
Uffe
> ---
>
> v13 changes:
> - Use GENMASK(7, 3) in elba_priv_writel() to set all byte enables
> - Add a variable 'shift' with GENMASK(1, 0) in elba_write_w() and
> elba_write_b() to set the byte enable variable.
>
> v11 changes:
> - Remove elba-drv_init() call to platform_get_resource() since that
> check is done inside devm_platform_ioremap_resource()
> - Move spin_lock_init() before error check
> - Remove extra parentheses
>
> v10 changes:
> - Add Elba specific support into this 3rd patch. This builds on the private
> writel() enabled in patch 1 followed by platform specific init() in patch 2.
> - Specify when first used the reason for the spinlock use to order byte-enable
> prior to write data.
>
> ---
> drivers/mmc/host/Kconfig | 1 +
> drivers/mmc/host/sdhci-cadence.c | 98 ++++++++++++++++++++++++++++++++
> 2 files changed, 99 insertions(+)
>
> diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
> index 4745fe217ade..9f793892123c 100644
> --- a/drivers/mmc/host/Kconfig
> +++ b/drivers/mmc/host/Kconfig
> @@ -255,6 +255,7 @@ config MMC_SDHCI_CADENCE
> tristate "SDHCI support for the Cadence SD/SDIO/eMMC controller"
> depends on MMC_SDHCI_PLTFM
> depends on OF
> + select MMC_SDHCI_IO_ACCESSORS
> help
> This selects the Cadence SD/SDIO/eMMC driver.
>
> diff --git a/drivers/mmc/host/sdhci-cadence.c b/drivers/mmc/host/sdhci-cadence.c
> index c528a25f48b8..5d1e9cef74f5 100644
> --- a/drivers/mmc/host/sdhci-cadence.c
> +++ b/drivers/mmc/host/sdhci-cadence.c
> @@ -66,6 +66,8 @@ struct sdhci_cdns_phy_param {
>
> struct sdhci_cdns_priv {
> void __iomem *hrs_addr;
> + void __iomem *ctl_addr; /* write control */
> + spinlock_t wrlock; /* write lock */
> bool enhanced_strobe;
> void (*priv_writel)(struct sdhci_cdns_priv *priv, u32 val, void __iomem *reg);
> unsigned int nr_phy_params;
> @@ -321,6 +323,91 @@ static void sdhci_cdns_set_uhs_signaling(struct sdhci_host *host,
> sdhci_set_uhs_signaling(host, timing);
> }
>
> +/* Elba control register bits [6:3] are byte-lane enables */
> +#define ELBA_BYTE_ENABLE_MASK(x) ((x) << 3)
> +
> +/*
> + * The Pensando Elba SoC explicitly controls byte-lane enabling on writes
> + * which includes writes to the HRS registers. The write lock (wrlock)
> + * is used to ensure byte-lane enable, using write control (ctl_addr),
> + * occurs before the data write.
> + */
> +static void elba_priv_writel(struct sdhci_cdns_priv *priv, u32 val,
> + void __iomem *reg)
> +{
> + unsigned long flags;
> +
> + spin_lock_irqsave(&priv->wrlock, flags);
> + writel(GENMASK(7, 3), priv->ctl_addr);
> + writel(val, reg);
> + spin_unlock_irqrestore(&priv->wrlock, flags);
> +}
> +
> +static void elba_write_l(struct sdhci_host *host, u32 val, int reg)
> +{
> + elba_priv_writel(sdhci_cdns_priv(host), val, host->ioaddr + reg);
> +}
> +
> +static void elba_write_w(struct sdhci_host *host, u16 val, int reg)
> +{
> + struct sdhci_cdns_priv *priv = sdhci_cdns_priv(host);
> + u32 shift = reg & GENMASK(1, 0);
> + unsigned long flags;
> + u32 byte_enables;
> +
> + byte_enables = GENMASK(1, 0) << shift;
> + spin_lock_irqsave(&priv->wrlock, flags);
> + writel(ELBA_BYTE_ENABLE_MASK(byte_enables), priv->ctl_addr);
> + writew(val, host->ioaddr + reg);
> + spin_unlock_irqrestore(&priv->wrlock, flags);
> +}
> +
> +static void elba_write_b(struct sdhci_host *host, u8 val, int reg)
> +{
> + struct sdhci_cdns_priv *priv = sdhci_cdns_priv(host);
> + u32 shift = reg & GENMASK(1, 0);
> + unsigned long flags;
> + u32 byte_enables;
> +
> + byte_enables = BIT(0) << shift;
> + spin_lock_irqsave(&priv->wrlock, flags);
> + writel(ELBA_BYTE_ENABLE_MASK(byte_enables), priv->ctl_addr);
> + writeb(val, host->ioaddr + reg);
> + spin_unlock_irqrestore(&priv->wrlock, flags);
> +}
> +
> +static const struct sdhci_ops sdhci_elba_ops = {
> + .write_l = elba_write_l,
> + .write_w = elba_write_w,
> + .write_b = elba_write_b,
> + .set_clock = sdhci_set_clock,
> + .get_timeout_clock = sdhci_cdns_get_timeout_clock,
> + .set_bus_width = sdhci_set_bus_width,
> + .reset = sdhci_reset,
> + .set_uhs_signaling = sdhci_cdns_set_uhs_signaling,
> +};
> +
> +static int elba_drv_init(struct platform_device *pdev)
> +{
> + struct sdhci_host *host = platform_get_drvdata(pdev);
> + struct sdhci_cdns_priv *priv = sdhci_cdns_priv(host);
> + void __iomem *ioaddr;
> +
> + host->mmc->caps |= MMC_CAP_1_8V_DDR | MMC_CAP_8_BIT_DATA;
> + spin_lock_init(&priv->wrlock);
> +
> + /* Byte-lane control register */
> + ioaddr = devm_platform_ioremap_resource(pdev, 1);
> + if (IS_ERR(ioaddr))
> + return PTR_ERR(ioaddr);
> +
> + priv->ctl_addr = ioaddr;
> + priv->priv_writel = elba_priv_writel;
> + writel(ELBA_BYTE_ENABLE_MASK(0xf), priv->ctl_addr);
> +
> + return 0;
> +}
> +
> static const struct sdhci_ops sdhci_cdns_ops = {
> .set_clock = sdhci_set_clock,
> .get_timeout_clock = sdhci_cdns_get_timeout_clock,
> @@ -337,6 +424,13 @@ static const struct sdhci_cdns_drv_data sdhci_cdns_uniphier_drv_data = {
> },
> };
>
> +static const struct sdhci_cdns_drv_data sdhci_elba_drv_data = {
> + .init = elba_drv_init,
> + .pltfm_data = {
> + .ops = &sdhci_elba_ops,
> + },
> +};
> +
> static const struct sdhci_cdns_drv_data sdhci_cdns_drv_data = {
> .pltfm_data = {
> .ops = &sdhci_cdns_ops,
> @@ -477,6 +571,10 @@ static const struct of_device_id sdhci_cdns_match[] = {
> .compatible = "socionext,uniphier-sd4hc",
> .data = &sdhci_cdns_uniphier_drv_data,
> },
> + {
> + .compatible = "amd,pensando-elba-sd4hc",
> + .data = &sdhci_elba_drv_data,
> + },
> { .compatible = "cdns,sd4hc" },
> { /* sentinel */ }
> };
> --
> 2.17.1
>
On Mon, 10 Apr 2023 at 20:47, Brad Larson <[email protected]> wrote:
>
> Move struct sdhci_pltfm_data under new struct sdhci_cdns_drv_data.
> Add an init() into sdhci_cdns_drv_data for platform specific device
> initialization in the device probe which is not used for existing devices.
>
> Signed-off-by: Brad Larson <[email protected]>
> Acked-by: Adrian Hunter <[email protected]>
Applied for next, thanks!
Kind regards
Uffe
> ---
>
> v10 changes:
> - New patch to provide for platform specific init() with no change
> to existing designs.
>
> ---
> drivers/mmc/host/sdhci-cadence.c | 32 +++++++++++++++++++++++---------
> 1 file changed, 23 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/mmc/host/sdhci-cadence.c b/drivers/mmc/host/sdhci-cadence.c
> index 708d4297f241..c528a25f48b8 100644
> --- a/drivers/mmc/host/sdhci-cadence.c
> +++ b/drivers/mmc/host/sdhci-cadence.c
> @@ -77,6 +77,11 @@ struct sdhci_cdns_phy_cfg {
> u8 addr;
> };
>
> +struct sdhci_cdns_drv_data {
> + int (*init)(struct platform_device *pdev);
> + const struct sdhci_pltfm_data pltfm_data;
> +};
> +
> static const struct sdhci_cdns_phy_cfg sdhci_cdns_phy_cfgs[] = {
> { "cdns,phy-input-delay-sd-highspeed", SDHCI_CDNS_PHY_DLY_SD_HS, },
> { "cdns,phy-input-delay-legacy", SDHCI_CDNS_PHY_DLY_SD_DEFAULT, },
> @@ -325,13 +330,17 @@ static const struct sdhci_ops sdhci_cdns_ops = {
> .set_uhs_signaling = sdhci_cdns_set_uhs_signaling,
> };
>
> -static const struct sdhci_pltfm_data sdhci_cdns_uniphier_pltfm_data = {
> - .ops = &sdhci_cdns_ops,
> - .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
> +static const struct sdhci_cdns_drv_data sdhci_cdns_uniphier_drv_data = {
> + .pltfm_data = {
> + .ops = &sdhci_cdns_ops,
> + .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
> + },
> };
>
> -static const struct sdhci_pltfm_data sdhci_cdns_pltfm_data = {
> - .ops = &sdhci_cdns_ops,
> +static const struct sdhci_cdns_drv_data sdhci_cdns_drv_data = {
> + .pltfm_data = {
> + .ops = &sdhci_cdns_ops,
> + },
> };
>
> static void sdhci_cdns_hs400_enhanced_strobe(struct mmc_host *mmc,
> @@ -357,7 +366,7 @@ static void sdhci_cdns_hs400_enhanced_strobe(struct mmc_host *mmc,
> static int sdhci_cdns_probe(struct platform_device *pdev)
> {
> struct sdhci_host *host;
> - const struct sdhci_pltfm_data *data;
> + const struct sdhci_cdns_drv_data *data;
> struct sdhci_pltfm_host *pltfm_host;
> struct sdhci_cdns_priv *priv;
> struct clk *clk;
> @@ -376,10 +385,10 @@ static int sdhci_cdns_probe(struct platform_device *pdev)
>
> data = of_device_get_match_data(dev);
> if (!data)
> - data = &sdhci_cdns_pltfm_data;
> + data = &sdhci_cdns_drv_data;
>
> nr_phy_params = sdhci_cdns_phy_param_count(dev->of_node);
> - host = sdhci_pltfm_init(pdev, data,
> + host = sdhci_pltfm_init(pdev, &data->pltfm_data,
> struct_size(priv, phy_params, nr_phy_params));
> if (IS_ERR(host)) {
> ret = PTR_ERR(host);
> @@ -397,6 +406,11 @@ static int sdhci_cdns_probe(struct platform_device *pdev)
> host->ioaddr += SDHCI_CDNS_SRS_BASE;
> host->mmc_host_ops.hs400_enhanced_strobe =
> sdhci_cdns_hs400_enhanced_strobe;
> + if (data->init) {
> + ret = data->init(pdev);
> + if (ret)
> + goto free;
> + }
> sdhci_enable_v4_mode(host);
> __sdhci_read_caps(host, &version, NULL, NULL);
>
> @@ -461,7 +475,7 @@ static const struct dev_pm_ops sdhci_cdns_pm_ops = {
> static const struct of_device_id sdhci_cdns_match[] = {
> {
> .compatible = "socionext,uniphier-sd4hc",
> - .data = &sdhci_cdns_uniphier_pltfm_data,
> + .data = &sdhci_cdns_uniphier_drv_data,
> },
> { .compatible = "cdns,sd4hc" },
> { /* sentinel */ }
> --
> 2.17.1
>
On Mon, 10 Apr 2023 at 20:48, Brad Larson <[email protected]> wrote:
>
> Add support for mmc hardware reset using a reset-controller
> that would need to be enabled in the device tree with
> a supporting driver. The default is disabled for all
> existing designs.
>
> Signed-off-by: Brad Larson <[email protected]>
> Acked-by: Adrian Hunter <[email protected]>
> Reviewed-by: Philipp Zabel <[email protected]>
Applied for next, thanks!
Kind regards
Uffe
> ---
>
> v9 changes:
> - Previously patch 17/17
> - Changed delay after reset_control_assert() from 9 to 3 usec
> - Renamed sdhci_mmc_hw_reset() to sdhci_cdns_mmc_hw_reset()
>
> ---
> drivers/mmc/host/sdhci-cadence.c | 27 +++++++++++++++++++++++++++
> 1 file changed, 27 insertions(+)
>
> diff --git a/drivers/mmc/host/sdhci-cadence.c b/drivers/mmc/host/sdhci-cadence.c
> index 5d1e9cef74f5..b24aa27da50c 100644
> --- a/drivers/mmc/host/sdhci-cadence.c
> +++ b/drivers/mmc/host/sdhci-cadence.c
> @@ -12,6 +12,7 @@
> #include <linux/mmc/mmc.h>
> #include <linux/of.h>
> #include <linux/of_device.h>
> +#include <linux/reset.h>
>
> #include "sdhci-pltfm.h"
>
> @@ -70,6 +71,7 @@ struct sdhci_cdns_priv {
> spinlock_t wrlock; /* write lock */
> bool enhanced_strobe;
> void (*priv_writel)(struct sdhci_cdns_priv *priv, u32 val, void __iomem *reg);
> + struct reset_control *rst_hw;
> unsigned int nr_phy_params;
> struct sdhci_cdns_phy_param phy_params[];
> };
> @@ -457,6 +459,22 @@ static void sdhci_cdns_hs400_enhanced_strobe(struct mmc_host *mmc,
> SDHCI_CDNS_HRS06_MODE_MMC_HS400);
> }
>
> +static void sdhci_cdns_mmc_hw_reset(struct mmc_host *mmc)
> +{
> + struct sdhci_host *host = mmc_priv(mmc);
> + struct sdhci_cdns_priv *priv = sdhci_cdns_priv(host);
> +
> + dev_dbg(mmc_dev(host->mmc), "emmc hardware reset\n");
> +
> + reset_control_assert(priv->rst_hw);
> + /* For eMMC, minimum is 1us but give it 3us for good measure */
> + udelay(3);
> +
> + reset_control_deassert(priv->rst_hw);
> + /* For eMMC, minimum is 200us but give it 300us for good measure */
> + usleep_range(300, 1000);
> +}
> +
> static int sdhci_cdns_probe(struct platform_device *pdev)
> {
> struct sdhci_host *host;
> @@ -520,6 +538,15 @@ static int sdhci_cdns_probe(struct platform_device *pdev)
> if (ret)
> goto free;
>
> + if (host->mmc->caps & MMC_CAP_HW_RESET) {
> + priv->rst_hw = devm_reset_control_get_optional_exclusive(dev, NULL);
> + if (IS_ERR(priv->rst_hw))
> + return dev_err_probe(mmc_dev(host->mmc), PTR_ERR(priv->rst_hw),
> + "reset controller error\n");
> + if (priv->rst_hw)
> + host->mmc_host_ops.card_hw_reset = sdhci_cdns_mmc_hw_reset;
> + }
> +
> ret = sdhci_add_host(host);
> if (ret)
> goto free;
> --
> 2.17.1
>
On Mon, 10 Apr 2023 11:45:11 -0700, Brad Larson wrote:
> This series enables support for AMD Pensando Elba SoC based platforms.
>
> The Elba SoC has the following features:
> - Sixteen ARM64 A72 cores
> - Dual DDR 4/5 memory controllers
> - 32 lanes of PCIe Gen3/4 to the Host
> - Network interfaces: Dual 200GE, Quad 100GE, 50GE, 25GE, 10GE and
> also a single 1GE management port.
> - Storage/crypto offloads and 144 programmable P4 cores.
> - QSPI and EMMC for SoC storage
> - Two SPI interfaces for peripheral management
> - I2C bus for platform management
>
> [...]
Applied to
https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git for-next
Thanks!
[03/15] dt-bindings: spi: cdns: Add compatible for AMD Pensando Elba SoC
(no commit info)
[04/15] dt-bindings: spi: dw: Add AMD Pensando Elba SoC SPI Controller
commit: 6282a6ceef62f5732082f691de8f82fcd49d4fb4
[09/15] spi: cadence-quadspi: Add compatible for AMD Pensando Elba SoC
(no commit info)
[10/15] spi: dw: Add support for AMD Pensando Elba SoC
commit: 2c8606040a808aa01d2d9e4f5b9332e87bb66377
All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to Linus during
the next merge window (or sooner if it is a bug fix), however if
problems are discovered then the patch may be dropped or reverted.
You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.
If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.
Please add any relevant lists and maintainers to the CCs when replying
to this mail.
Thanks,
Mark
Hi Andy,
Thanks for the additional review.
On Tue, Apr 11, 2023 at 12:20:43 Andy Shevchenko <[email protected]> wrote:
> On Mon, Apr 10, 2023 at 9:48 PM Brad Larson <[email protected]> wrote:
>>
>> The Pensando SoC controller is a SPI connected companion device
>> that is present in all Pensando SoC board designs. The essential
>> board management registers are accessed on chip select 0 with
>> board mgmt IO support accessed using additional chip selects.
>
> ...
>
>> +#include <linux/cdev.h>
>> +#include <linux/device.h>
>> +#include <linux/err.h>
>> +#include <linux/init.h>
>> +#include <linux/mod_devicetable.h>
>> +#include <linux/module.h>
>> +#include <linux/mutex.h>
>> +#include <linux/of.h>
>> +#include <linux/reset-controller.h>
>> +#include <linux/spi/spi.h>
>
> + Blank line?
Added blank line
>> +#include <linux/amd-pensando-ctrl.h>
>
> ...
>
>> +struct penctrl_device {
>> + struct spi_device *spi;
>> + struct reset_controller_dev rcdev;
>
> Try to swap them and check if the code will be smaller (it depends on
> how often one or another member is being used),
Reversed the order to reduced code size by 8 bytes.
>> +};
>
> ...
>
>> +static long
>> +penctrl_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
>> +{
>> + void __user *in_arg = (void __user *)arg;
>> + struct penctrl_device *penctrl;
>> + u8 tx_buf[PENCTRL_MAX_MSG_LEN];
>> + u8 rx_buf[PENCTRL_MAX_MSG_LEN];
>> + struct spi_transfer t[2] = {};
>> + struct penctrl_spi_xfer *msg;
>> + struct spi_device *spi;
>> + unsigned int num_msgs;
>> + struct spi_message m;
>> + u32 size;
>> + int ret;
>> +
>> + /* Check for a valid command */
>> + if (_IOC_TYPE(cmd) != PENCTRL_IOC_MAGIC)
>> + return -ENOTTY;
>> +
>> + if (_IOC_NR(cmd) > PENCTRL_IOC_MAXNR)
>> + return -ENOTTY;
>> +
>> + if (_IOC_DIR(cmd) & _IOC_READ)
>> + ret = !access_ok(in_arg, _IOC_SIZE(cmd));
>> + else if (_IOC_DIR(cmd) & _IOC_WRITE)
>> + ret = !access_ok(in_arg, _IOC_SIZE(cmd));
>
>> +
>
> Unneeded blank line.
>
>> + if (ret)
>> + return -EFAULT;
>
> But it seems you can actually rewrite above in less lines:
>
> if ((_IOC_DIR(cmd) & _IOC_READ) && !access_ok(in_arg, _IOC_SIZE(cmd)))
> return -EFAULT;
>
> if ((_IOC_DIR(cmd) & _IOC_WRITE) && !access_ok(in_arg, _IOC_SIZE(cmd)))
> return -EFAULT;
Yes, changed to save a line.
>> + /* Get a reference to the SPI device */
>> + penctrl = filp->private_data;
>> + if (!penctrl)
>> + return -ESHUTDOWN;
>> +
>> + spi = spi_dev_get(penctrl->spi);
>> + if (!spi)
>> + return -ESHUTDOWN;
>> +
>> + /* Verify and prepare SPI message */
>> + size = _IOC_SIZE(cmd);
>> + num_msgs = size / sizeof(struct penctrl_spi_xfer);
>> + if (size == 0 || size % sizeof(struct penctrl_spi_xfer)) {
>> + ret = -EINVAL;
>> + goto done;
>> + }
>> + msg = memdup_user((struct penctrl_spi_xfer *)arg, size);
>
>> + if (!msg) {
>> + ret = PTR_ERR(msg);
>
> This is strange.
Yes, changed to
msg = memdup_user((struct penctrl_spi_xfer *)arg, size);
if (IS_ERR(msg)) {
ret = PTR_ERR(msg);
goto out_unlock;
}
>> + goto done;
>> + }
>> + if (msg->len > PENCTRL_MAX_MSG_LEN) {
>> + ret = -EINVAL;
>> + goto done;
>> + }
>> +
>> + t[0].tx_buf = tx_buf;
>> + t[0].len = msg->len;
>> + if (copy_from_user(tx_buf, (void __user *)msg->tx_buf, msg->len)) {
>> + ret = -EFAULT;
>> + goto done;
>> + }
>> + if (num_msgs > 1) {
>> + msg++;
>> + if (msg->len > PENCTRL_MAX_MSG_LEN) {
>> + ret = -EINVAL;
>> + goto done;
>> + }
>> + t[1].rx_buf = rx_buf;
>> + t[1].len = msg->len;
>> + }
>> + spi_message_init_with_transfers(&m, t, num_msgs);
>
> It seems there is no validation for the messages 3+.
The device doesn't support and applications don't use num_msgs > 2, added this check here
/* Verify and prepare SPI message */
size = _IOC_SIZE(cmd);
num_msgs = size / sizeof(struct penctrl_spi_xfer);
if (num_msgs > 2 || size == 0 || size % sizeof(struct penctrl_spi_xfer)) {
ret = -EINVAL;
goto out_unlock;
}
>> + /* Perform the transfer */
>> + mutex_lock(&spi_lock);
>> + ret = spi_sync(spi, &m);
>> + mutex_unlock(&spi_lock);
>> +
>> + if (ret || (num_msgs == 1))
>> + goto done;
>> +
>> + if (copy_to_user((void __user *)msg->rx_buf, rx_buf, msg->len))
>> + ret = -EFAULT;
>
>> +done:
>
> out_unlock: ?
Changed to out_unlock
>> + spi_dev_put(spi);
>> + return ret;
>> +}
>> +
>> +static int penctrl_open(struct inode *inode, struct file *filp)
>> +{
>> + struct spi_device *spi;
>> + u8 current_cs;
>
>> + if (!penctrl)
>> + return -ENODEV;
>
> Is it possible?
No, removed as a non-existent device can't be opened.
>> + filp->private_data = penctrl;
>> + current_cs = iminor(inode);
>> + spi = penctrl->spi;
>> + spi->chip_select = current_cs;
>
>> + spi->cs_gpiod = spi->controller->cs_gpiods[current_cs];
>
> Hmm... Why do you need this one? Isn't it a job of SPI core?
When the four device tree nodes, one per cs, was squashed into the parent the
SPI core no longer handles this and the driver needs to do it.
>> + spi_setup(spi);
>> + return stream_open(inode, filp);
>> +}
>
>> +static int penctrl_regs_read(struct penctrl_device *penctrl, u32 reg, u32 *val)
>> +{
>> + struct spi_device *spi = penctrl->spi;
>> + struct spi_transfer t[2] = {};
>> + struct spi_message m;
>> + u8 txbuf[3];
>> + u8 rxbuf[1];
>> + int ret;
>> +
>> + txbuf[0] = PENCTRL_SPI_CMD_REGRD;
>> + txbuf[1] = reg;
>> + txbuf[2] = 0;
>> + t[0].tx_buf = txbuf;
>> + t[0].len = 3;
>
> sizeof(txbuf) ?
Changed to sizeof()
>> + rxbuf[0] = 0;
>> + t[1].rx_buf = rxbuf;
>> + t[1].len = 1;
>
> sizeof(rxbuf) ?
Changed to sizeof()
>> + spi_message_init_with_transfers(&m, t, ARRAY_SIZE(t));
>> + ret = spi_sync(spi, &m);
>> + if (ret == 0)
>> + *val = rxbuf[0];
>> +
>> + return ret;
>> +}
>> +
>> +static int penctrl_regs_write(struct penctrl_device *penctrl, u32 reg, u32 val)
>> +{
>> + struct spi_device *spi = penctrl->spi;
>> + struct spi_transfer t;
>> + struct spi_message m;
>> + u8 txbuf[4];
>> +
>> + txbuf[0] = PENCTRL_SPI_CMD_REGWR;
>> + txbuf[1] = reg;
>> + txbuf[2] = val;
>> + txbuf[3] = 0;
>> +
>> + t.tx_buf = txbuf;
>> + t.len = 4;
>
> sizeof(txbuf) ?
Changed to sizeof()
>> + spi_message_init_with_transfers(&m, &t, 1);
>> + return spi_sync(spi, &m);
>> +}
>> +
>> +static int penctrl_reset_assert(struct reset_controller_dev *rcdev,
>> + unsigned long id)
>> +{
>> + struct penctrl_device *penctrl =
>> + container_of(rcdev, struct penctrl_device, rcdev);
>> + struct spi_device *spi = penctrl->spi;
>> + unsigned int val;
>> + int ret;
>> +
>> + mutex_lock(&spi_lock);
>> + spi->chip_select = 0;
>> + spi->cs_gpiod = spi->controller->cs_gpiods[0];
>> + spi_setup(spi);
>> + ret = penctrl_regs_read(penctrl, PENCTRL_REG_CTRL0, &val);
>> + if (ret) {
>> + dev_err(&spi->dev, "error reading ctrl0 reg\n");
>> + goto done;
>> + }
>> +
>> + val |= BIT(6);
>> + ret = penctrl_regs_write(penctrl, PENCTRL_REG_CTRL0, val);
>> + if (ret)
>> + dev_err(&spi->dev, "error writing ctrl0 reg\n");
>
>> +done:
>
> out_unlock: ?
Changed to out_unlock
>> + mutex_unlock(&spi_lock);
>> + return ret;
>> +}
>> +
>> +static int penctrl_reset_deassert(struct reset_controller_dev *rcdev,
>> + unsigned long id)
>> +{
>> + struct penctrl_device *penctrl =
>> + container_of(rcdev, struct penctrl_device, rcdev);
>> + struct spi_device *spi = penctrl->spi;
>> + unsigned int val;
>> + int ret;
>> +
>> + mutex_lock(&spi_lock);
>> + spi->chip_select = 0;
>> + spi->cs_gpiod = spi->controller->cs_gpiods[0];
>> + spi_setup(spi);
>> + ret = penctrl_regs_read(penctrl, PENCTRL_REG_CTRL0, &val);
>> + if (ret) {
>> + dev_err(&spi->dev, "error reading ctrl0 reg\n");
>> + goto done;
>> + }
>> +
>> + val &= ~BIT(6);
>> + ret = penctrl_regs_write(penctrl, PENCTRL_REG_CTRL0, val);
>> + if (ret)
>> + dev_err(&spi->dev, "error writing ctrl0 reg\n");
>
>> +done:
>
> out_unlock: ?
Changed to out_unlock
>> + mutex_unlock(&spi_lock);
>> + return ret;
>> +}
>
>> +static int penctrl_spi_probe(struct spi_device *spi)
>> +{
>> + struct device *dev;
>> + struct cdev *cdev;
>> + u32 num_cs;
>> + int ret;
>> + u32 cs;
>> +
>> + ret = device_property_read_u32(spi->dev.parent, "num-cs", &num_cs);
>> + if (ret)
>> + return dev_err_probe(&spi->dev, ret,
>> + "number of chip-selects not defined\n");
>> +
>> + ret = alloc_chrdev_region(&penctrl_devt, 0, num_cs, "penctrl");
>> + if (ret)
>> + return dev_err_probe(&spi->dev, ret,
>> + "failed to alloc chrdev region\n");
>> +
>> + penctrl_class = class_create(THIS_MODULE, "penctrl");
>> + if (IS_ERR(penctrl_class)) {
>> + ret = dev_err_probe(&spi->dev, PTR_ERR(penctrl_class),
>> + "failed to create class\n");
>> + goto unregister_chrdev;
>> + }
>> +
>> + cdev = cdev_alloc();
>> + if (!cdev) {
>> + ret = dev_err_probe(&spi->dev, -ENOMEM,
>> + "allocation of cdev failed\n");
>> + goto destroy_class;
>> + }
>> + cdev->owner = THIS_MODULE;
>> + cdev_init(cdev, &penctrl_fops);
>> +
>> + ret = cdev_add(cdev, penctrl_devt, num_cs);
>> + if (ret) {
>> + ret = dev_err_probe(&spi->dev, ret,
>> + "register of cdev failed\n");
>> + goto free_cdev;
>> + }
>> +
>> + /* Allocate driver data */
>> + penctrl = kzalloc(sizeof(*penctrl), GFP_KERNEL);
>> + if (!penctrl) {
>> + ret = -ENOMEM;
>> + goto free_cdev;
>> + }
>> + penctrl->spi = spi;
>> + mutex_init(&spi_lock);
>> +
>> + /* Create a device for each chip select */
>> + for (cs = 0; cs < num_cs; cs++) {
>> + dev = device_create(penctrl_class,
>> + &spi->dev,
>> + MKDEV(MAJOR(penctrl_devt), cs),
>> + penctrl,
>> + "penctrl0.%d",
>> + cs);
>> + if (IS_ERR(dev)) {
>> + ret = dev_err_probe(&spi->dev, PTR_ERR(dev),
>> + "error creating device\n");
>> + goto destroy_device;
>> + }
>> + dev_dbg(&spi->dev, "created device major %u, minor %d\n",
>> + MAJOR(penctrl_devt), cs);
>> + }
>> +
>> + /* Register emmc hardware reset */
>> + penctrl->rcdev.nr_resets = 1;
>> + penctrl->rcdev.owner = THIS_MODULE;
>> + penctrl->rcdev.dev = &spi->dev;
>> + penctrl->rcdev.ops = &penctrl_reset_ops;
>
>> + penctrl->rcdev.of_node = spi->dev.of_node;
>
> Either redundant or wrong. Shouldn't you first have the firmware node
> to be set for spi->dev?
The spi device firmware node is set on entry to penctrl_spi_probe(). Just the
reset controller of_node needs to be set like this
penctrl->rcdev.dev = &spi->dev;
penctrl->rcdev.ops = &penctrl_reset_ops;
penctrl->rcdev.owner = THIS_MODULE;
penctrl->rcdev.of_node = spi->dev.of_node;
penctrl->rcdev.nr_resets = 1;
ret = reset_controller_register(&penctrl->rcdev);
which is similar to other reset controllers for example reset-sunplus.c:
static int sp_reset_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
...
reset->rcdev.ops = &sp_reset_ops;
reset->rcdev.owner = THIS_MODULE;
reset->rcdev.of_node = dev->of_node;
reset->rcdev.nr_resets = resource_size(res) / 4 * BITS_PER_HWM_REG;
ret = devm_reset_controller_register(dev, &reset->rcdev);
}
for of_node at the same level as dev in reset_controller_dev
struct reset_controller_dev {
const struct reset_control_ops *ops;
...
struct device *dev;
struct device_node *of_node;
...
};
>> + device_set_node(&spi->dev, dev_fwnode(dev));
>> +
>> + ret = reset_controller_register(&penctrl->rcdev);
>> + if (ret)
>> + return dev_err_probe(&spi->dev, ret,
>> + "failed to register reset controller\n");
>> + return 0;
>> +
>> +destroy_device:
>> + for (cs = 0; cs < num_cs; cs++)
>> + device_destroy(penctrl_class, MKDEV(MAJOR(penctrl_devt), cs));
>> + kfree(penctrl);
>> +free_cdev:
>> + cdev_del(cdev);
>> +destroy_class:
>> + class_destroy(penctrl_class);
>> +unregister_chrdev:
>> + unregister_chrdev(MAJOR(penctrl_devt), "penctrl");
>> +
>> + return ret;
>> +}
>
> ...
>
>> +++ b/include/uapi/linux/amd-pensando-ctrl.h
>> @@ -0,0 +1,30 @@
>> +/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
>> +/*
>> + * Userspace interface for /dev/penctrl
>> + *
>> + * This file can be used by applications that need to communicate
>> + * with the AMD Pensando SoC controller device via the ioctl interface.
>> + */
>> +#ifndef _UAPI_LINUX_AMD_PENSANDO_CTRL_H
>> +#define _UAPI_LINUX_AMD_PENSANDO_CTRL_H
>
>> +#include <linux/ioctl.h>
>
> Not used header.
Removed
>> +#include <linux/types.h>
>> +
>> +#define PENCTRL_SPI_CMD_REGRD 0x0b
>> +#define PENCTRL_SPI_CMD_REGWR 0x02
>> +#define PENCTRL_IOC_MAGIC 'k'
>> +#define PENCTRL_IOC_MAXNR 0
>> +#define PENCTRL_MAX_MSG_LEN 16
>> +#define PENCTRL_MAX_REG 0xff
>> +#define PENCTRL_REG_CTRL0 0x10
>> +
>> +struct penctrl_spi_xfer {
>> + __u64 tx_buf;
>> + __u64 rx_buf;
>> + __u32 len;
>> + __u32 speed_hz;
>> + __u64 compat;
>> +};
>> +
>> +#endif /* _UAPI_LINUX_AMD_PENSANDO_CTRL_H */
Add AMD Pensando common and Elba SoC specific device nodes
Signed-off-by: Brad Larson <[email protected]>
---
v14 changes:
- Fix dtbs_check l2-cache* property issue by adding required
cache-level and cache-unified properties
- Observed the issue after updating dtschema from 2023.1 to 2023.4
and yamllint from 1.26.3 to 1.30.0
v11 changes:
- Delete reset-names
- Fix spi0 compatible to be specific 'amd,pensando-elba-ctrl'
v9 changes:
- Single node for spi0 system-controller and squash
the reset-controller child into parent
---
arch/arm64/boot/dts/amd/Makefile | 1 +
arch/arm64/boot/dts/amd/elba-16core.dtsi | 197 ++++++++++++++++++
arch/arm64/boot/dts/amd/elba-asic-common.dtsi | 80 +++++++
arch/arm64/boot/dts/amd/elba-asic.dts | 28 +++
arch/arm64/boot/dts/amd/elba-flash-parts.dtsi | 106 ++++++++++
arch/arm64/boot/dts/amd/elba.dtsi | 191 +++++++++++++++++
6 files changed, 603 insertions(+)
create mode 100644 arch/arm64/boot/dts/amd/elba-16core.dtsi
create mode 100644 arch/arm64/boot/dts/amd/elba-asic-common.dtsi
create mode 100644 arch/arm64/boot/dts/amd/elba-asic.dts
create mode 100644 arch/arm64/boot/dts/amd/elba-flash-parts.dtsi
create mode 100644 arch/arm64/boot/dts/amd/elba.dtsi
diff --git a/arch/arm64/boot/dts/amd/Makefile b/arch/arm64/boot/dts/amd/Makefile
index 68103a8b0ef5..8502cc2afbc5 100644
--- a/arch/arm64/boot/dts/amd/Makefile
+++ b/arch/arm64/boot/dts/amd/Makefile
@@ -1,2 +1,3 @@
# SPDX-License-Identifier: GPL-2.0
+dtb-$(CONFIG_ARCH_PENSANDO) += elba-asic.dtb
dtb-$(CONFIG_ARCH_SEATTLE) += amd-overdrive-rev-b0.dtb amd-overdrive-rev-b1.dtb
diff --git a/arch/arm64/boot/dts/amd/elba-16core.dtsi b/arch/arm64/boot/dts/amd/elba-16core.dtsi
new file mode 100644
index 000000000000..f9f9f5fd5f69
--- /dev/null
+++ b/arch/arm64/boot/dts/amd/elba-16core.dtsi
@@ -0,0 +1,197 @@
+// SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
+/*
+ * Copyright 2020-2022 Advanced Micro Devices, Inc.
+ */
+
+/ {
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ cpu-map {
+ cluster0 {
+ core0 { cpu = <&cpu0>; };
+ core1 { cpu = <&cpu1>; };
+ core2 { cpu = <&cpu2>; };
+ core3 { cpu = <&cpu3>; };
+ };
+
+ cluster1 {
+ core0 { cpu = <&cpu4>; };
+ core1 { cpu = <&cpu5>; };
+ core2 { cpu = <&cpu6>; };
+ core3 { cpu = <&cpu7>; };
+ };
+
+ cluster2 {
+ core0 { cpu = <&cpu8>; };
+ core1 { cpu = <&cpu9>; };
+ core2 { cpu = <&cpu10>; };
+ core3 { cpu = <&cpu11>; };
+ };
+
+ cluster3 {
+ core0 { cpu = <&cpu12>; };
+ core1 { cpu = <&cpu13>; };
+ core2 { cpu = <&cpu14>; };
+ core3 { cpu = <&cpu15>; };
+ };
+ };
+
+ /* CLUSTER 0 */
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ reg = <0 0x0>;
+ next-level-cache = <&l2_0>;
+ enable-method = "psci";
+ };
+
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ reg = <0 0x1>;
+ next-level-cache = <&l2_0>;
+ enable-method = "psci";
+ };
+
+ cpu2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ reg = <0 0x2>;
+ next-level-cache = <&l2_0>;
+ enable-method = "psci";
+ };
+
+ cpu3: cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ reg = <0 0x3>;
+ next-level-cache = <&l2_0>;
+ enable-method = "psci";
+ };
+
+ l2_0: l2-cache0 {
+ compatible = "cache";
+ cache-unified;
+ cache-level = <2>;
+ };
+
+ /* CLUSTER 1 */
+ cpu4: cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ reg = <0 0x100>;
+ next-level-cache = <&l2_1>;
+ enable-method = "psci";
+ };
+
+ cpu5: cpu@101 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ reg = <0 0x101>;
+ next-level-cache = <&l2_1>;
+ enable-method = "psci";
+ };
+
+ cpu6: cpu@102 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ reg = <0 0x102>;
+ next-level-cache = <&l2_1>;
+ enable-method = "psci";
+ };
+
+ cpu7: cpu@103 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ reg = <0 0x103>;
+ next-level-cache = <&l2_1>;
+ enable-method = "psci";
+ };
+
+ l2_1: l2-cache1 {
+ compatible = "cache";
+ cache-unified;
+ cache-level = <2>;
+ };
+
+ /* CLUSTER 2 */
+ cpu8: cpu@200 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ reg = <0 0x200>;
+ next-level-cache = <&l2_2>;
+ enable-method = "psci";
+ };
+
+ cpu9: cpu@201 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ reg = <0 0x201>;
+ next-level-cache = <&l2_2>;
+ enable-method = "psci";
+ };
+
+ cpu10: cpu@202 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ reg = <0 0x202>;
+ next-level-cache = <&l2_2>;
+ enable-method = "psci";
+ };
+
+ cpu11: cpu@203 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ reg = <0 0x203>;
+ next-level-cache = <&l2_2>;
+ enable-method = "psci";
+ };
+
+ l2_2: l2-cache2 {
+ compatible = "cache";
+ cache-unified;
+ cache-level = <2>;
+ };
+
+ /* CLUSTER 3 */
+ cpu12: cpu@300 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ reg = <0 0x300>;
+ next-level-cache = <&l2_3>;
+ enable-method = "psci";
+ };
+
+ cpu13: cpu@301 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ reg = <0 0x301>;
+ next-level-cache = <&l2_3>;
+ enable-method = "psci";
+ };
+
+ cpu14: cpu@302 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ reg = <0 0x302>;
+ next-level-cache = <&l2_3>;
+ enable-method = "psci";
+ };
+
+ cpu15: cpu@303 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ reg = <0 0x303>;
+ next-level-cache = <&l2_3>;
+ enable-method = "psci";
+ };
+
+ l2_3: l2-cache3 {
+ compatible = "cache";
+ cache-unified;
+ cache-level = <2>;
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/amd/elba-asic-common.dtsi b/arch/arm64/boot/dts/amd/elba-asic-common.dtsi
new file mode 100644
index 000000000000..1a615788f54e
--- /dev/null
+++ b/arch/arm64/boot/dts/amd/elba-asic-common.dtsi
@@ -0,0 +1,80 @@
+// SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
+/*
+ * Copyright 2020-2022 Advanced Micro Devices, Inc.
+ */
+
+&ahb_clk {
+ clock-frequency = <400000000>;
+};
+
+&emmc_clk {
+ clock-frequency = <200000000>;
+};
+
+&flash_clk {
+ clock-frequency = <400000000>;
+};
+
+&ref_clk {
+ clock-frequency = <156250000>;
+};
+
+&qspi {
+ status = "okay";
+
+ flash0: flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <40000000>;
+ spi-rx-bus-width = <2>;
+ m25p,fast-read;
+ cdns,read-delay = <0>;
+ cdns,tshsl-ns = <0>;
+ cdns,tsd2d-ns = <0>;
+ cdns,tchsh-ns = <0>;
+ cdns,tslch-ns = <0>;
+ };
+};
+
+&gpio0 {
+ status = "okay";
+};
+
+&emmc {
+ bus-width = <8>;
+ cap-mmc-hw-reset;
+ resets = <&rstc 0>;
+ status = "okay";
+};
+
+&wdt0 {
+ status = "okay";
+};
+
+&i2c0 {
+ clock-frequency = <100000>;
+ status = "okay";
+
+ rtc@51 {
+ compatible = "nxp,pcf85263";
+ reg = <0x51>;
+ };
+};
+
+&spi0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ num-cs = <4>;
+ cs-gpios = <0>, <0>, <&porta 1 GPIO_ACTIVE_LOW>,
+ <&porta 7 GPIO_ACTIVE_LOW>;
+ status = "okay";
+
+ rstc: system-controller@0 {
+ compatible = "amd,pensando-elba-ctrl";
+ reg = <0>;
+ spi-max-frequency = <12000000>;
+ interrupt-parent = <&porta>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+ #reset-cells = <1>;
+ };
+};
diff --git a/arch/arm64/boot/dts/amd/elba-asic.dts b/arch/arm64/boot/dts/amd/elba-asic.dts
new file mode 100644
index 000000000000..c3f4da2f7449
--- /dev/null
+++ b/arch/arm64/boot/dts/amd/elba-asic.dts
@@ -0,0 +1,28 @@
+// SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
+/*
+ * Device Tree file for AMD Pensando Elba Board.
+ *
+ * Copyright 2020-2022 Advanced Micro Devices, Inc.
+ */
+
+/dts-v1/;
+
+#include "elba.dtsi"
+#include "elba-16core.dtsi"
+#include "elba-asic-common.dtsi"
+#include "elba-flash-parts.dtsi"
+
+/ {
+ model = "AMD Pensando Elba Board";
+ compatible = "amd,pensando-elba-ortano", "amd,pensando-elba";
+
+ aliases {
+ serial0 = &uart0;
+ spi0 = &spi0;
+ spi1 = &qspi;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
diff --git a/arch/arm64/boot/dts/amd/elba-flash-parts.dtsi b/arch/arm64/boot/dts/amd/elba-flash-parts.dtsi
new file mode 100644
index 000000000000..734893fef2c3
--- /dev/null
+++ b/arch/arm64/boot/dts/amd/elba-flash-parts.dtsi
@@ -0,0 +1,106 @@
+// SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
+/*
+ * Copyright 2020-2022 Advanced Micro Devices, Inc.
+ */
+
+&flash0 {
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ partition@0 {
+ label = "flash";
+ reg = <0x10000 0xfff0000>;
+ };
+
+ partition@f0000 {
+ label = "golduenv";
+ reg = <0xf0000 0x10000>;
+ };
+
+ partition@100000 {
+ label = "boot0";
+ reg = <0x100000 0x80000>;
+ };
+
+ partition@180000 {
+ label = "golduboot";
+ reg = <0x180000 0x200000>;
+ };
+
+ partition@380000 {
+ label = "brdcfg0";
+ reg = <0x380000 0x10000>;
+ };
+
+ partition@390000 {
+ label = "brdcfg1";
+ reg = <0x390000 0x10000>;
+ };
+
+ partition@400000 {
+ label = "goldfw";
+ reg = <0x400000 0x3c00000>;
+ };
+
+ partition@4010000 {
+ label = "fwmap";
+ reg = <0x4010000 0x20000>;
+ };
+
+ partition@4030000 {
+ label = "fwsel";
+ reg = <0x4030000 0x20000>;
+ };
+
+ partition@4090000 {
+ label = "bootlog";
+ reg = <0x4090000 0x20000>;
+ };
+
+ partition@40b0000 {
+ label = "panicbuf";
+ reg = <0x40b0000 0x20000>;
+ };
+
+ partition@40d0000 {
+ label = "uservars";
+ reg = <0x40d0000 0x20000>;
+ };
+
+ partition@4200000 {
+ label = "uboota";
+ reg = <0x4200000 0x400000>;
+ };
+
+ partition@4600000 {
+ label = "ubootb";
+ reg = <0x4600000 0x400000>;
+ };
+
+ partition@4a00000 {
+ label = "mainfwa";
+ reg = <0x4a00000 0x1000000>;
+ };
+
+ partition@5a00000 {
+ label = "mainfwb";
+ reg = <0x5a00000 0x1000000>;
+ };
+
+ partition@6a00000 {
+ label = "diaguboot";
+ reg = <0x6a00000 0x400000>;
+ };
+
+ partition@8000000 {
+ label = "diagfw";
+ reg = <0x8000000 0x7fe0000>;
+ };
+
+ partition@ffe0000 {
+ label = "ubootenv";
+ reg = <0xffe0000 0x10000>;
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/amd/elba.dtsi b/arch/arm64/boot/dts/amd/elba.dtsi
new file mode 100644
index 000000000000..674890cf2a34
--- /dev/null
+++ b/arch/arm64/boot/dts/amd/elba.dtsi
@@ -0,0 +1,191 @@
+// SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
+/*
+ * Copyright 2020-2022 Advanced Micro Devices, Inc.
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include "dt-bindings/interrupt-controller/arm-gic.h"
+
+/ {
+ model = "Elba ASIC Board";
+ compatible = "amd,pensando-elba";
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ dma-coherent;
+
+ ahb_clk: oscillator0 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ };
+
+ emmc_clk: oscillator2 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ };
+
+ flash_clk: oscillator3 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ };
+
+ ref_clk: oscillator4 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ };
+
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
+ };
+
+ pmu {
+ compatible = "arm,cortex-a72-pmu";
+ interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
+ };
+
+ soc: soc {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ i2c0: i2c@400 {
+ compatible = "snps,designware-i2c";
+ reg = <0x0 0x400 0x0 0x100>;
+ clocks = <&ahb_clk>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ i2c-sda-hold-time-ns = <480>;
+ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ wdt0: watchdog@1400 {
+ compatible = "snps,dw-wdt";
+ reg = <0x0 0x1400 0x0 0x100>;
+ clocks = <&ahb_clk>;
+ interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ qspi: spi@2400 {
+ compatible = "amd,pensando-elba-qspi", "cdns,qspi-nor";
+ reg = <0x0 0x2400 0x0 0x400>,
+ <0x0 0x7fff0000 0x0 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&flash_clk>;
+ cdns,fifo-depth = <1024>;
+ cdns,fifo-width = <4>;
+ cdns,trigger-address = <0x7fff0000>;
+ status = "disabled";
+ };
+
+ spi0: spi@2800 {
+ compatible = "amd,pensando-elba-spi";
+ reg = <0x0 0x2800 0x0 0x100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ amd,pensando-elba-syscon = <&syscon>;
+ clocks = <&ahb_clk>;
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ num-cs = <2>;
+ status = "disabled";
+ };
+
+ gpio0: gpio@4000 {
+ compatible = "snps,dw-apb-gpio";
+ reg = <0x0 0x4000 0x0 0x78>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ porta: gpio-port@0 {
+ compatible = "snps,dw-apb-gpio-port";
+ reg = <0>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ ngpios = <8>;
+ interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ interrupt-parent = <&gic>;
+ #interrupt-cells = <2>;
+ };
+
+ portb: gpio-port@1 {
+ compatible = "snps,dw-apb-gpio-port";
+ reg = <1>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ ngpios = <8>;
+ };
+ };
+
+ uart0: serial@4800 {
+ compatible = "ns16550a";
+ reg = <0x0 0x4800 0x0 0x100>;
+ clocks = <&ref_clk>;
+ interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ };
+
+ gic: interrupt-controller@800000 {
+ compatible = "arm,gic-v3";
+ reg = <0x0 0x800000 0x0 0x200000>, /* GICD */
+ <0x0 0xa00000 0x0 0x200000>, /* GICR */
+ <0x0 0x60000000 0x0 0x2000>, /* GICC */
+ <0x0 0x60010000 0x0 0x1000>, /* GICH */
+ <0x0 0x60020000 0x0 0x2000>; /* GICV */
+ #address-cells = <2>;
+ #size-cells = <2>;
+ #interrupt-cells = <3>;
+ ranges;
+ interrupt-controller;
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+
+ /*
+ * Elba specific pre-ITS is enabled using the
+ * existing property socionext,synquacer-pre-its
+ */
+ gic_its: msi-controller@820000 {
+ compatible = "arm,gic-v3-its";
+ reg = <0x0 0x820000 0x0 0x10000>;
+ msi-controller;
+ #msi-cells = <1>;
+ socionext,synquacer-pre-its =
+ <0xc00000 0x1000000>;
+ };
+ };
+
+ emmc: mmc@30440000 {
+ compatible = "amd,pensando-elba-sd4hc", "cdns,sd4hc";
+ reg = <0x0 0x30440000 0x0 0x10000>,
+ <0x0 0x30480044 0x0 0x4>; /* byte-lane ctrl */
+ clocks = <&emmc_clk>;
+ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+ cdns,phy-input-delay-sd-highspeed = <0x4>;
+ cdns,phy-input-delay-legacy = <0x4>;
+ cdns,phy-input-delay-sd-uhs-sdr50 = <0x6>;
+ cdns,phy-input-delay-sd-uhs-ddr50 = <0x16>;
+ mmc-ddr-1_8v;
+ status = "disabled";
+ };
+
+ syscon: syscon@307c0000 {
+ compatible = "amd,pensando-elba-syscon", "syscon";
+ reg = <0x0 0x307c0000 0x0 0x3000>;
+ };
+ };
+};
base-commit: fe15c26ee26efa11741a7b632e9f23b01aca4cc6
--
2.17.1
The Pensando SoC controller is a SPI connected companion device
that is present in all Pensando SoC board designs. The essential
board management registers are accessed on chip select 0 with
board mgmt IO support accessed using additional chip selects.
Signed-off-by: Brad Larson <[email protected]>
---
v14 changes:
- Save 8 bytes of code size by swapping spi_device and reset_controller_dev
in penctrl_device
- Code simplification and clarity from review inputs
- Set penctrl_spi_driver.driver.name to match compatible pensando-elba-ctrl
- Remove unused include in amd-pensando-ctrl.h
v13 changes:
- Update include list in pensando-ctrl.c
- Change variable spi_dev to spi throughout
- Removed unneeded variable initialization, simplification of
error checks, remove extra castings, and use dev_err_probe()
- Sort the includes in amd-pensando-ctrl.h
- Updates to cleanup if there is an error in penctrl_spi_probe()
v12 changes:
- Fix gcc-12.1.0 warning:
Reported-by: kernel test robot <[email protected]>
Link: https://lore.kernel.org/oe-kbuild-all/[email protected]/
v11 changes:
- Fix the compatible to be specific 'amd,pensando-elba-ctrl'
v10 changes:
- Different driver implementation specific to this Pensando controller device.
- Moved to soc/amd directory under new name based on guidance. This driver is
of no use to any design other than all Pensando SoC based cards.
- Removed use of builtin_driver, can be built as a module.
v9 changes:
- Previously patch 14/17
- After the change to the device tree node and squashing
reset-cells into the parent simplified this to not use
any MFD API and move it to drivers/spi/pensando-sr.c.
- Change the naming to remove elba since this driver is common
for all Pensando SoC designs .
- Default yes SPI_PENSANDO_SR for ARCH_PENSANDO
---
drivers/soc/Kconfig | 1 +
drivers/soc/Makefile | 1 +
drivers/soc/amd/Kconfig | 16 ++
drivers/soc/amd/Makefile | 2 +
drivers/soc/amd/pensando-ctrl.c | 368 +++++++++++++++++++++++++
include/uapi/linux/amd-pensando-ctrl.h | 29 ++
6 files changed, 417 insertions(+)
create mode 100644 drivers/soc/amd/Kconfig
create mode 100644 drivers/soc/amd/Makefile
create mode 100644 drivers/soc/amd/pensando-ctrl.c
create mode 100644 include/uapi/linux/amd-pensando-ctrl.h
diff --git a/drivers/soc/Kconfig b/drivers/soc/Kconfig
index 4e176280113a..9e023f74e47c 100644
--- a/drivers/soc/Kconfig
+++ b/drivers/soc/Kconfig
@@ -2,6 +2,7 @@
menu "SOC (System On Chip) specific Drivers"
source "drivers/soc/actions/Kconfig"
+source "drivers/soc/amd/Kconfig"
source "drivers/soc/amlogic/Kconfig"
source "drivers/soc/apple/Kconfig"
source "drivers/soc/aspeed/Kconfig"
diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile
index 3b0f9fb3b5c8..8914530f2721 100644
--- a/drivers/soc/Makefile
+++ b/drivers/soc/Makefile
@@ -4,6 +4,7 @@
#
obj-$(CONFIG_ARCH_ACTIONS) += actions/
+obj-y += amd/
obj-y += apple/
obj-y += aspeed/
obj-$(CONFIG_ARCH_AT91) += atmel/
diff --git a/drivers/soc/amd/Kconfig b/drivers/soc/amd/Kconfig
new file mode 100644
index 000000000000..011d5339d14e
--- /dev/null
+++ b/drivers/soc/amd/Kconfig
@@ -0,0 +1,16 @@
+# SPDX-License-Identifier: GPL-2.0-only
+menu "AMD Pensando SoC drivers"
+
+config AMD_PENSANDO_CTRL
+ tristate "AMD Pensando SoC Controller"
+ depends on SPI_MASTER=y
+ depends on (ARCH_PENSANDO && OF) || COMPILE_TEST
+ default ARCH_PENSANDO
+ select REGMAP_SPI
+ select MFD_SYSCON
+ help
+ Enables AMD Pensando SoC controller device support. This is a SPI
+ attached companion device in all Pensando SoC board designs which
+ provides essential board control/status registers and management IO
+ support.
+endmenu
diff --git a/drivers/soc/amd/Makefile b/drivers/soc/amd/Makefile
new file mode 100644
index 000000000000..a2de0424f68d
--- /dev/null
+++ b/drivers/soc/amd/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0-only
+obj-$(CONFIG_AMD_PENSANDO_CTRL) += pensando-ctrl.o
diff --git a/drivers/soc/amd/pensando-ctrl.c b/drivers/soc/amd/pensando-ctrl.c
new file mode 100644
index 000000000000..ba37c8328853
--- /dev/null
+++ b/drivers/soc/amd/pensando-ctrl.c
@@ -0,0 +1,368 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * AMD Pensando SoC Controller
+ *
+ * Userspace interface and reset driver support for SPI connected Pensando SoC
+ * controller device. This device is present in all Pensando SoC designs and
+ * contains board control/status registers and management IO support.
+ *
+ * Copyright 2023 Advanced Micro Devices, Inc.
+ */
+
+#include <linux/cdev.h>
+#include <linux/device.h>
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/mod_devicetable.h>
+#include <linux/module.h>
+#include <linux/mutex.h>
+#include <linux/of.h>
+#include <linux/reset-controller.h>
+#include <linux/spi/spi.h>
+
+#include <linux/amd-pensando-ctrl.h>
+
+struct penctrl_device {
+ struct reset_controller_dev rcdev;
+ struct spi_device *spi;
+};
+
+static DEFINE_MUTEX(spi_lock);
+static dev_t penctrl_devt;
+static struct penctrl_device *penctrl;
+static struct class *penctrl_class;
+
+static long
+penctrl_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
+{
+ void __user *in_arg = (void __user *)arg;
+ struct penctrl_device *penctrl;
+ u8 tx_buf[PENCTRL_MAX_MSG_LEN];
+ u8 rx_buf[PENCTRL_MAX_MSG_LEN];
+ struct spi_transfer t[2] = {};
+ struct penctrl_spi_xfer *msg;
+ struct spi_device *spi;
+ unsigned int num_msgs;
+ struct spi_message m;
+ u32 size;
+ int ret;
+
+ /* Check for a valid command */
+ if (_IOC_TYPE(cmd) != PENCTRL_IOC_MAGIC)
+ return -ENOTTY;
+
+ if (_IOC_NR(cmd) > PENCTRL_IOC_MAXNR)
+ return -ENOTTY;
+
+ if (((_IOC_DIR(cmd) & _IOC_READ)) && !access_ok(in_arg, _IOC_SIZE(cmd)))
+ return -EFAULT;
+
+ if (((_IOC_DIR(cmd) & _IOC_WRITE)) && !access_ok(in_arg, _IOC_SIZE(cmd)))
+ return -EFAULT;
+
+ /* Get a reference to the SPI device */
+ penctrl = filp->private_data;
+ if (!penctrl)
+ return -ESHUTDOWN;
+
+ spi = spi_dev_get(penctrl->spi);
+ if (!spi)
+ return -ESHUTDOWN;
+
+ /* Verify and prepare SPI message */
+ size = _IOC_SIZE(cmd);
+ num_msgs = size / sizeof(struct penctrl_spi_xfer);
+ if (num_msgs > 2 || size == 0 || size % sizeof(struct penctrl_spi_xfer)) {
+ ret = -EINVAL;
+ goto out_unlock;
+ }
+ msg = memdup_user((struct penctrl_spi_xfer *)arg, size);
+ if (IS_ERR(msg)) {
+ ret = PTR_ERR(msg);
+ goto out_unlock;
+ }
+ if (msg->len > PENCTRL_MAX_MSG_LEN) {
+ ret = -EINVAL;
+ goto out_unlock;
+ }
+
+ t[0].tx_buf = tx_buf;
+ t[0].len = msg->len;
+ if (copy_from_user(tx_buf, (void __user *)msg->tx_buf, msg->len)) {
+ ret = -EFAULT;
+ goto out_unlock;
+ }
+ if (num_msgs > 1) {
+ msg++;
+ if (msg->len > PENCTRL_MAX_MSG_LEN) {
+ ret = -EINVAL;
+ goto out_unlock;
+ }
+ t[1].rx_buf = rx_buf;
+ t[1].len = msg->len;
+ }
+ spi_message_init_with_transfers(&m, t, num_msgs);
+
+ /* Perform the transfer */
+ mutex_lock(&spi_lock);
+ ret = spi_sync(spi, &m);
+ mutex_unlock(&spi_lock);
+
+ if (ret || (num_msgs == 1))
+ goto out_unlock;
+
+ if (copy_to_user((void __user *)msg->rx_buf, rx_buf, msg->len))
+ ret = -EFAULT;
+
+out_unlock:
+ spi_dev_put(spi);
+ return ret;
+}
+
+static int penctrl_open(struct inode *inode, struct file *filp)
+{
+ struct spi_device *spi;
+ u8 current_cs;
+
+ filp->private_data = penctrl;
+ current_cs = iminor(inode);
+ spi = penctrl->spi;
+ spi->chip_select = current_cs;
+ spi->cs_gpiod = spi->controller->cs_gpiods[current_cs];
+ spi_setup(spi);
+ return stream_open(inode, filp);
+}
+
+static int penctrl_release(struct inode *inode, struct file *filp)
+{
+ filp->private_data = NULL;
+ return 0;
+}
+
+static const struct file_operations penctrl_fops = {
+ .owner = THIS_MODULE,
+ .unlocked_ioctl = penctrl_ioctl,
+ .open = penctrl_open,
+ .release = penctrl_release,
+ .llseek = no_llseek,
+};
+
+static int penctrl_regs_read(struct penctrl_device *penctrl, u32 reg, u32 *val)
+{
+ struct spi_device *spi = penctrl->spi;
+ struct spi_transfer t[2] = {};
+ struct spi_message m;
+ u8 txbuf[3];
+ u8 rxbuf[1];
+ int ret;
+
+ txbuf[0] = PENCTRL_SPI_CMD_REGRD;
+ txbuf[1] = reg;
+ txbuf[2] = 0;
+ t[0].tx_buf = txbuf;
+ t[0].len = sizeof(txbuf);
+
+ rxbuf[0] = 0;
+ t[1].rx_buf = rxbuf;
+ t[1].len = sizeof(rxbuf);
+
+ spi_message_init_with_transfers(&m, t, ARRAY_SIZE(t));
+ ret = spi_sync(spi, &m);
+ if (ret == 0)
+ *val = rxbuf[0];
+
+ return ret;
+}
+
+static int penctrl_regs_write(struct penctrl_device *penctrl, u32 reg, u32 val)
+{
+ struct spi_device *spi = penctrl->spi;
+ struct spi_transfer t;
+ struct spi_message m;
+ u8 txbuf[4];
+
+ txbuf[0] = PENCTRL_SPI_CMD_REGWR;
+ txbuf[1] = reg;
+ txbuf[2] = val;
+ txbuf[3] = 0;
+
+ t.tx_buf = txbuf;
+ t.len = sizeof(txbuf);
+ spi_message_init_with_transfers(&m, &t, 1);
+ return spi_sync(spi, &m);
+}
+
+static int penctrl_reset_assert(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+ struct penctrl_device *penctrl =
+ container_of(rcdev, struct penctrl_device, rcdev);
+ struct spi_device *spi = penctrl->spi;
+ unsigned int val;
+ int ret;
+
+ mutex_lock(&spi_lock);
+ spi->chip_select = 0;
+ spi->cs_gpiod = spi->controller->cs_gpiods[0];
+ spi_setup(spi);
+ ret = penctrl_regs_read(penctrl, PENCTRL_REG_CTRL0, &val);
+ if (ret) {
+ dev_err(&spi->dev, "error reading ctrl0 reg\n");
+ goto out_unlock;
+ }
+
+ val |= BIT(6);
+ ret = penctrl_regs_write(penctrl, PENCTRL_REG_CTRL0, val);
+ if (ret)
+ dev_err(&spi->dev, "error writing ctrl0 reg\n");
+
+out_unlock:
+ mutex_unlock(&spi_lock);
+ return ret;
+}
+
+static int penctrl_reset_deassert(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+ struct penctrl_device *penctrl =
+ container_of(rcdev, struct penctrl_device, rcdev);
+ struct spi_device *spi = penctrl->spi;
+ unsigned int val;
+ int ret;
+
+ mutex_lock(&spi_lock);
+ spi->chip_select = 0;
+ spi->cs_gpiod = spi->controller->cs_gpiods[0];
+ spi_setup(spi);
+ ret = penctrl_regs_read(penctrl, PENCTRL_REG_CTRL0, &val);
+ if (ret) {
+ dev_err(&spi->dev, "error reading ctrl0 reg\n");
+ goto out_unlock;
+ }
+
+ val &= ~BIT(6);
+ ret = penctrl_regs_write(penctrl, PENCTRL_REG_CTRL0, val);
+ if (ret)
+ dev_err(&spi->dev, "error writing ctrl0 reg\n");
+
+out_unlock:
+ mutex_unlock(&spi_lock);
+ return ret;
+}
+
+static const struct reset_control_ops penctrl_reset_ops = {
+ .assert = penctrl_reset_assert,
+ .deassert = penctrl_reset_deassert,
+};
+
+static int penctrl_spi_probe(struct spi_device *spi)
+{
+ struct device *dev;
+ struct cdev *cdev;
+ u32 num_cs;
+ int ret;
+ u32 cs;
+
+ ret = device_property_read_u32(spi->dev.parent, "num-cs", &num_cs);
+ if (ret)
+ return dev_err_probe(&spi->dev, ret,
+ "number of chip-selects not defined\n");
+
+ ret = alloc_chrdev_region(&penctrl_devt, 0, num_cs, "penctrl");
+ if (ret)
+ return dev_err_probe(&spi->dev, ret,
+ "failed to alloc chrdev region\n");
+
+ penctrl_class = class_create(THIS_MODULE, "penctrl");
+ if (IS_ERR(penctrl_class)) {
+ ret = dev_err_probe(&spi->dev, PTR_ERR(penctrl_class),
+ "failed to create class\n");
+ goto unregister_chrdev;
+ }
+
+ cdev = cdev_alloc();
+ if (!cdev) {
+ ret = dev_err_probe(&spi->dev, -ENOMEM,
+ "allocation of cdev failed\n");
+ goto destroy_class;
+ }
+ cdev->owner = THIS_MODULE;
+ cdev_init(cdev, &penctrl_fops);
+
+ ret = cdev_add(cdev, penctrl_devt, num_cs);
+ if (ret) {
+ ret = dev_err_probe(&spi->dev, ret,
+ "register of cdev failed\n");
+ goto free_cdev;
+ }
+
+ /* Allocate driver data */
+ penctrl = kzalloc(sizeof(*penctrl), GFP_KERNEL);
+ if (!penctrl) {
+ ret = -ENOMEM;
+ goto free_cdev;
+ }
+ penctrl->spi = spi;
+ mutex_init(&spi_lock);
+
+ /* Create a device for each chip select */
+ for (cs = 0; cs < num_cs; cs++) {
+ dev = device_create(penctrl_class,
+ &spi->dev,
+ MKDEV(MAJOR(penctrl_devt), cs),
+ penctrl,
+ "penctrl0.%d",
+ cs);
+ if (IS_ERR(dev)) {
+ ret = dev_err_probe(&spi->dev, PTR_ERR(dev),
+ "error creating device\n");
+ goto destroy_device;
+ }
+ dev_dbg(&spi->dev, "created device major %u, minor %d\n",
+ MAJOR(penctrl_devt), cs);
+ }
+
+ /* Register reset controller */
+ penctrl->rcdev.dev = &spi->dev;
+ penctrl->rcdev.ops = &penctrl_reset_ops;
+ penctrl->rcdev.owner = THIS_MODULE;
+ penctrl->rcdev.of_node = spi->dev.of_node;
+ penctrl->rcdev.nr_resets = 1;
+
+ ret = reset_controller_register(&penctrl->rcdev);
+ if (ret)
+ return dev_err_probe(&spi->dev, ret,
+ "failed to register reset controller\n");
+ return 0;
+
+destroy_device:
+ for (cs = 0; cs < num_cs; cs++)
+ device_destroy(penctrl_class, MKDEV(MAJOR(penctrl_devt), cs));
+ kfree(penctrl);
+free_cdev:
+ cdev_del(cdev);
+destroy_class:
+ class_destroy(penctrl_class);
+unregister_chrdev:
+ unregister_chrdev(MAJOR(penctrl_devt), "penctrl");
+
+ return ret;
+}
+
+static const struct of_device_id penctrl_dt_match[] = {
+ { .compatible = "amd,pensando-elba-ctrl" },
+ { /* sentinel */ }
+};
+
+static struct spi_driver penctrl_spi_driver = {
+ .probe = penctrl_spi_probe,
+ .driver = {
+ .name = "pensando-elba-ctrl",
+ .of_match_table = penctrl_dt_match,
+ },
+};
+module_spi_driver(penctrl_spi_driver);
+
+MODULE_AUTHOR("Brad Larson <[email protected]>");
+MODULE_DESCRIPTION("AMD Pensando SoC Controller via SPI");
+MODULE_LICENSE("GPL");
diff --git a/include/uapi/linux/amd-pensando-ctrl.h b/include/uapi/linux/amd-pensando-ctrl.h
new file mode 100644
index 000000000000..e5f9f0dfe146
--- /dev/null
+++ b/include/uapi/linux/amd-pensando-ctrl.h
@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
+/*
+ * Userspace interface for /dev/penctrl
+ *
+ * This file can be used by applications that need to communicate
+ * with the AMD Pensando SoC controller device via the ioctl interface.
+ */
+#ifndef _UAPI_LINUX_AMD_PENSANDO_CTRL_H
+#define _UAPI_LINUX_AMD_PENSANDO_CTRL_H
+
+#include <linux/types.h>
+
+#define PENCTRL_SPI_CMD_REGRD 0x0b
+#define PENCTRL_SPI_CMD_REGWR 0x02
+#define PENCTRL_IOC_MAGIC 'k'
+#define PENCTRL_IOC_MAXNR 0
+#define PENCTRL_MAX_MSG_LEN 16
+#define PENCTRL_MAX_REG 0xff
+#define PENCTRL_REG_CTRL0 0x10
+
+struct penctrl_spi_xfer {
+ __u64 tx_buf;
+ __u64 rx_buf;
+ __u32 len;
+ __u32 speed_hz;
+ __u64 compat;
+};
+
+#endif /* _UAPI_LINUX_AMD_PENSANDO_CTRL_H */
base-commit: fe15c26ee26efa11741a7b632e9f23b01aca4cc6
--
2.17.1