This series introduces an optional utmi clock that is used on stm32mp15,
in particular when using integrated full-speed PHY, managed by GGPIO
register.
A pre-cursor change improves error handling in the platform code.
Fabrice Gasnier (4):
usb: dwc2: improve error handling in __dwc2_lowlevel_hw_enable
dt-bindings: usb: dwc2: add utmi optional clock
usb: dwc2: platform: add support for utmi optional clock
ARM: dts: stm32: add USB OTG UTMI clock on stm32mp151
.../devicetree/bindings/usb/dwc2.yaml | 5 ++-
arch/arm/boot/dts/stm32mp151.dtsi | 4 +-
drivers/usb/dwc2/core.h | 2 +
drivers/usb/dwc2/platform.c | 37 ++++++++++++++++++-
4 files changed, 43 insertions(+), 5 deletions(-)
--
2.25.1
Add error handling in __dwc2_lowlevel_hw_enable() that may leave the
clocks and regulators enabled upon error.
Signed-off-by: Fabrice Gasnier <[email protected]>
---
drivers/usb/dwc2/platform.c | 19 +++++++++++++++++--
1 file changed, 17 insertions(+), 2 deletions(-)
diff --git a/drivers/usb/dwc2/platform.c b/drivers/usb/dwc2/platform.c
index d1589ba7d322..c431ce6c119f 100644
--- a/drivers/usb/dwc2/platform.c
+++ b/drivers/usb/dwc2/platform.c
@@ -104,7 +104,7 @@ static int __dwc2_lowlevel_hw_enable(struct dwc2_hsotg *hsotg)
if (hsotg->clk) {
ret = clk_prepare_enable(hsotg->clk);
if (ret)
- return ret;
+ goto err_dis_reg;
}
if (hsotg->uphy) {
@@ -113,10 +113,25 @@ static int __dwc2_lowlevel_hw_enable(struct dwc2_hsotg *hsotg)
ret = hsotg->plat->phy_init(pdev, hsotg->plat->phy_type);
} else {
ret = phy_init(hsotg->phy);
- if (ret == 0)
+ if (ret == 0) {
ret = phy_power_on(hsotg->phy);
+ if (ret)
+ phy_exit(hsotg->phy);
+ }
}
+ if (ret)
+ goto err_dis_clk;
+
+ return 0;
+
+err_dis_clk:
+ if (hsotg->clk)
+ clk_disable_unprepare(hsotg->clk);
+
+err_dis_reg:
+ regulator_bulk_disable(ARRAY_SIZE(hsotg->supplies), hsotg->supplies);
+
return ret;
}
--
2.25.1