I noticed some very msm-downstream-y bugs in the QCM2290 dispcc..
Let's fix them up..
Signed-off-by: Konrad Dybcio <[email protected]>
---
Konrad Dybcio (3):
clk: qcom: dispcc-qcm2290: Fix BI_TCXO_AO handling
clk: qcom: dispcc-qcm2290: Remove inexistent DSI1PHY clk
clk: qcom: dispcc-qcm2290: Fix GPLL0_OUT_DIV handling
drivers/clk/qcom/dispcc-qcm2290.c | 15 +++++++--------
1 file changed, 7 insertions(+), 8 deletions(-)
---
base-commit: 7d8214bba44c1aa6a75921a09a691945d26a8d43
change-id: 20230412-topic-qcm_dispcc-f46cbdeaeb90
Best regards,
--
Konrad Dybcio <[email protected]>
BI_TCXO_AO was previously shoved in under the name of its non-AO
sibling in parent_map_2. Resolve it.
Fixes: cc517ea3333f ("clk: qcom: Add display clock controller driver for QCM2290")
Signed-off-by: Konrad Dybcio <[email protected]>
---
drivers/clk/qcom/dispcc-qcm2290.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/qcom/dispcc-qcm2290.c b/drivers/clk/qcom/dispcc-qcm2290.c
index cbb5f1ec6a54..0f516c72e624 100644
--- a/drivers/clk/qcom/dispcc-qcm2290.c
+++ b/drivers/clk/qcom/dispcc-qcm2290.c
@@ -24,6 +24,7 @@
enum {
P_BI_TCXO,
+ P_BI_TCXO_AO,
P_DISP_CC_PLL0_OUT_MAIN,
P_DSI0_PHY_PLL_OUT_BYTECLK,
P_DSI0_PHY_PLL_OUT_DSICLK,
@@ -83,7 +84,7 @@ static const struct clk_parent_data disp_cc_parent_data_1[] = {
};
static const struct parent_map disp_cc_parent_map_2[] = {
- { P_BI_TCXO, 0 },
+ { P_BI_TCXO_AO, 0 },
{ P_GPLL0_OUT_MAIN, 4 },
};
@@ -154,7 +155,7 @@ static struct clk_regmap_div disp_cc_mdss_byte0_div_clk_src = {
};
static const struct freq_tbl ftbl_disp_cc_mdss_ahb_clk_src[] = {
- F(19200000, P_BI_TCXO, 1, 0, 0),
+ F(19200000, P_BI_TCXO_AO, 1, 0, 0),
F(37500000, P_GPLL0_OUT_MAIN, 8, 0, 0),
F(75000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
{ }
--
2.40.0
There's only one DSI PHY on this SoC. Remove the ghost entry for the
clock produced by a secondary one.
Fixes: cc517ea3333f ("clk: qcom: Add display clock controller driver for QCM2290")
Signed-off-by: Konrad Dybcio <[email protected]>
---
drivers/clk/qcom/dispcc-qcm2290.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/clk/qcom/dispcc-qcm2290.c b/drivers/clk/qcom/dispcc-qcm2290.c
index 0f516c72e624..ee62aca4e5bb 100644
--- a/drivers/clk/qcom/dispcc-qcm2290.c
+++ b/drivers/clk/qcom/dispcc-qcm2290.c
@@ -28,7 +28,6 @@ enum {
P_DISP_CC_PLL0_OUT_MAIN,
P_DSI0_PHY_PLL_OUT_BYTECLK,
P_DSI0_PHY_PLL_OUT_DSICLK,
- P_DSI1_PHY_PLL_OUT_DSICLK,
P_GPLL0_OUT_MAIN,
P_SLEEP_CLK,
};
@@ -108,13 +107,11 @@ static const struct clk_parent_data disp_cc_parent_data_3[] = {
static const struct parent_map disp_cc_parent_map_4[] = {
{ P_BI_TCXO, 0 },
{ P_DSI0_PHY_PLL_OUT_DSICLK, 1 },
- { P_DSI1_PHY_PLL_OUT_DSICLK, 2 },
};
static const struct clk_parent_data disp_cc_parent_data_4[] = {
{ .fw_name = "bi_tcxo" },
{ .fw_name = "dsi0_phy_pll_out_dsiclk" },
- { .fw_name = "dsi1_phy_pll_out_dsiclk" },
};
static const struct parent_map disp_cc_parent_map_5[] = {
--
2.40.0
GPLL0_OUT_DIV was previously shoved in under the name of its undivided
sibling in parent_map_2. Resolve it.
Fixes: cc517ea3333f ("clk: qcom: Add display clock controller driver for QCM2290")
Signed-off-by: Konrad Dybcio <[email protected]>
---
drivers/clk/qcom/dispcc-qcm2290.c | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/qcom/dispcc-qcm2290.c b/drivers/clk/qcom/dispcc-qcm2290.c
index ee62aca4e5bb..44dd5cfcc150 100644
--- a/drivers/clk/qcom/dispcc-qcm2290.c
+++ b/drivers/clk/qcom/dispcc-qcm2290.c
@@ -28,6 +28,7 @@ enum {
P_DISP_CC_PLL0_OUT_MAIN,
P_DSI0_PHY_PLL_OUT_BYTECLK,
P_DSI0_PHY_PLL_OUT_DSICLK,
+ P_GPLL0_OUT_DIV,
P_GPLL0_OUT_MAIN,
P_SLEEP_CLK,
};
@@ -84,7 +85,7 @@ static const struct clk_parent_data disp_cc_parent_data_1[] = {
static const struct parent_map disp_cc_parent_map_2[] = {
{ P_BI_TCXO_AO, 0 },
- { P_GPLL0_OUT_MAIN, 4 },
+ { P_GPLL0_OUT_DIV, 4 },
};
static const struct clk_parent_data disp_cc_parent_data_2[] = {
@@ -153,8 +154,8 @@ static struct clk_regmap_div disp_cc_mdss_byte0_div_clk_src = {
static const struct freq_tbl ftbl_disp_cc_mdss_ahb_clk_src[] = {
F(19200000, P_BI_TCXO_AO, 1, 0, 0),
- F(37500000, P_GPLL0_OUT_MAIN, 8, 0, 0),
- F(75000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
+ F(37500000, P_GPLL0_OUT_DIV, 8, 0, 0),
+ F(75000000, P_GPLL0_OUT_DIV, 4, 0, 0),
{ }
};
--
2.40.0
On Wed, Apr 12, 2023 at 04:53:07PM +0200, Konrad Dybcio wrote:
> GPLL0_OUT_DIV was previously shoved in under the name of its undivided
> sibling in parent_map_2. Resolve it.
>
I'm afraid I don't understand what you're saying here, can you please
rework it?
Thanks,
Bjorn
> Fixes: cc517ea3333f ("clk: qcom: Add display clock controller driver for QCM2290")
> Signed-off-by: Konrad Dybcio <[email protected]>
> ---
> drivers/clk/qcom/dispcc-qcm2290.c | 7 ++++---
> 1 file changed, 4 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/clk/qcom/dispcc-qcm2290.c b/drivers/clk/qcom/dispcc-qcm2290.c
> index ee62aca4e5bb..44dd5cfcc150 100644
> --- a/drivers/clk/qcom/dispcc-qcm2290.c
> +++ b/drivers/clk/qcom/dispcc-qcm2290.c
> @@ -28,6 +28,7 @@ enum {
> P_DISP_CC_PLL0_OUT_MAIN,
> P_DSI0_PHY_PLL_OUT_BYTECLK,
> P_DSI0_PHY_PLL_OUT_DSICLK,
> + P_GPLL0_OUT_DIV,
> P_GPLL0_OUT_MAIN,
> P_SLEEP_CLK,
> };
> @@ -84,7 +85,7 @@ static const struct clk_parent_data disp_cc_parent_data_1[] = {
>
> static const struct parent_map disp_cc_parent_map_2[] = {
> { P_BI_TCXO_AO, 0 },
> - { P_GPLL0_OUT_MAIN, 4 },
> + { P_GPLL0_OUT_DIV, 4 },
> };
>
> static const struct clk_parent_data disp_cc_parent_data_2[] = {
> @@ -153,8 +154,8 @@ static struct clk_regmap_div disp_cc_mdss_byte0_div_clk_src = {
>
> static const struct freq_tbl ftbl_disp_cc_mdss_ahb_clk_src[] = {
> F(19200000, P_BI_TCXO_AO, 1, 0, 0),
> - F(37500000, P_GPLL0_OUT_MAIN, 8, 0, 0),
> - F(75000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
> + F(37500000, P_GPLL0_OUT_DIV, 8, 0, 0),
> + F(75000000, P_GPLL0_OUT_DIV, 4, 0, 0),
> { }
> };
>
>
> --
> 2.40.0
>
On Wed, Apr 12, 2023 at 04:53:05PM +0200, Konrad Dybcio wrote:
> BI_TCXO_AO was previously shoved in under the name of its non-AO
> sibling in parent_map_2. Resolve it.
>
> Fixes: cc517ea3333f ("clk: qcom: Add display clock controller driver for QCM2290")
> Signed-off-by: Konrad Dybcio <[email protected]>
> ---
> drivers/clk/qcom/dispcc-qcm2290.c | 5 +++--
> 1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/clk/qcom/dispcc-qcm2290.c b/drivers/clk/qcom/dispcc-qcm2290.c
> index cbb5f1ec6a54..0f516c72e624 100644
> --- a/drivers/clk/qcom/dispcc-qcm2290.c
> +++ b/drivers/clk/qcom/dispcc-qcm2290.c
> @@ -24,6 +24,7 @@
>
> enum {
> P_BI_TCXO,
> + P_BI_TCXO_AO,
> P_DISP_CC_PLL0_OUT_MAIN,
> P_DSI0_PHY_PLL_OUT_BYTECLK,
> P_DSI0_PHY_PLL_OUT_DSICLK,
> @@ -83,7 +84,7 @@ static const struct clk_parent_data disp_cc_parent_data_1[] = {
> };
>
> static const struct parent_map disp_cc_parent_map_2[] = {
> - { P_BI_TCXO, 0 },
> + { P_BI_TCXO_AO, 0 },
I think the commit message fails to explain why the parent clock for the
AHB clocks should be active-only. Are you sure, can you please
elaborate?
Thanks,
Bjorn
> { P_GPLL0_OUT_MAIN, 4 },
> };
>
> @@ -154,7 +155,7 @@ static struct clk_regmap_div disp_cc_mdss_byte0_div_clk_src = {
> };
>
> static const struct freq_tbl ftbl_disp_cc_mdss_ahb_clk_src[] = {
> - F(19200000, P_BI_TCXO, 1, 0, 0),
> + F(19200000, P_BI_TCXO_AO, 1, 0, 0),
> F(37500000, P_GPLL0_OUT_MAIN, 8, 0, 0),
> F(75000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
> { }
>
> --
> 2.40.0
>
On Wed, 12 Apr 2023 16:53:04 +0200, Konrad Dybcio wrote:
> I noticed some very msm-downstream-y bugs in the QCM2290 dispcc..
> Let's fix them up..
>
>
Applied, thanks!
[2/3] clk: qcom: dispcc-qcm2290: Remove inexistent DSI1PHY clk
commit: 68d1151f03067533827fc50b770954ef33149533
Best regards,
--
Bjorn Andersson <[email protected]>