From: "Borislav Petkov (AMD)" <[email protected]>
PeterZ wanted this spelled out explicitly. Add it to the documentation
so that everyone's on the same page wrt to which microcode patches are
not allowed to be late loaded.
Suggested-by: Peter Zijlstra (Intel) <[email protected]>
Signed-off-by: Borislav Petkov (AMD) <[email protected]>
---
Documentation/x86/microcode.rst | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/Documentation/x86/microcode.rst b/Documentation/x86/microcode.rst
index 15b52e2b181d..d5ef9184030c 100644
--- a/Documentation/x86/microcode.rst
+++ b/Documentation/x86/microcode.rst
@@ -218,6 +218,10 @@ a fault happens, the whole core will see it either before the microcode
patch has been applied or after. In either case, T0 and T1 will have the
same microcode revision and nothing intermediate.
+In addition, microcode patches which modify software-visible features
+like CPUID bits, MSRs, chicken bits, etc are not released for late
+loading.
+
Builtin microcode
=================
--
2.35.1
The following commit has been merged into the x86/microcode branch of tip:
Commit-ID: 07cc5639f14dcc3763a926dbe7cc38ac2694de0c
Gitweb: https://git.kernel.org/tip/07cc5639f14dcc3763a926dbe7cc38ac2694de0c
Author: Borislav Petkov (AMD) <[email protected]>
AuthorDate: Sat, 15 Apr 2023 16:23:29 +02:00
Committer: Borislav Petkov (AMD) <[email protected]>
CommitterDate: Mon, 17 Apr 2023 15:38:33 +02:00
x86/microcode/AMD: Document which patches are not released for late loading
PeterZ wanted this spelled out explicitly. Add it to the documentation
so that everyone's on the same page wrt to which microcode patches are
not allowed to be late loaded.
Suggested-by: Peter Zijlstra (Intel) <[email protected]>
Signed-off-by: Borislav Petkov (AMD) <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
---
Documentation/x86/microcode.rst | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/Documentation/x86/microcode.rst b/Documentation/x86/microcode.rst
index 15b52e2..d5ef918 100644
--- a/Documentation/x86/microcode.rst
+++ b/Documentation/x86/microcode.rst
@@ -218,6 +218,10 @@ a fault happens, the whole core will see it either before the microcode
patch has been applied or after. In either case, T0 and T1 will have the
same microcode revision and nothing intermediate.
+In addition, microcode patches which modify software-visible features
+like CPUID bits, MSRs, chicken bits, etc are not released for late
+loading.
+
Builtin microcode
=================
On Sat, Apr 15 2023 at 16:28, Borislav Petkov wrote:
> From: "Borislav Petkov (AMD)" <[email protected]>
>
> PeterZ wanted this spelled out explicitly. Add it to the documentation
> so that everyone's on the same page wrt to which microcode patches are
> not allowed to be late loaded.
>
> Suggested-by: Peter Zijlstra (Intel) <[email protected]>
> Signed-off-by: Borislav Petkov (AMD) <[email protected]>
> ---
> Documentation/x86/microcode.rst | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/Documentation/x86/microcode.rst b/Documentation/x86/microcode.rst
> index 15b52e2b181d..d5ef9184030c 100644
> --- a/Documentation/x86/microcode.rst
> +++ b/Documentation/x86/microcode.rst
> @@ -218,6 +218,10 @@ a fault happens, the whole core will see it either before the microcode
> patch has been applied or after. In either case, T0 and T1 will have the
> same microcode revision and nothing intermediate.
>
> +In addition, microcode patches which modify software-visible features
> +like CPUID bits, MSRs, chicken bits, etc are not released for late
> +loading.
No. Why the heck is AMD any different from Intel vs. late loading?
It does not matter at all that the AMD microcode machinery does not have
the concurrency issues like the Intel one, which just need some extra
care.
The software visible feature change issue is exactly the same and the
problem of late loading is all about that and not about the concurrency.
So Intel got its act together and added a minimal version field into the
microcode header. AMD should do exactly the same and not assume that
late loading is safe by pretending that updates which modify software
visible features are not released.
That's just not true. AMD releases microcode updates with software
visible changes as does Intel, no?
How did all the hardware vulnerability updates, which changed CPUID,
MSRs and chicken bits, get distributed? By not releasing them?
This patch along with the other which claims that AMD is safe is just
wishful thinking material.
Boris, please remove them from the for 6.4 queue.
Thanks,
tglx