From: Rahul T R <[email protected]>
Add DSS and DP-bridge node for J784S4 SoC. DSS IP in J784S4 is
same as DSS IP in J721E, so same compatible is being used.
The DP is Cadence MHDP8546.
Signed-off-by: Rahul T R <[email protected]>
[[email protected]: move all k3-j784s4-main.dtsi changes together]
Signed-off-by: Jayesh Choudhary <[email protected]>
---
arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 77 ++++++++++++++++++++++
1 file changed, 77 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
index 51aa476dedba..739741e93bc1 100644
--- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
@@ -1373,4 +1373,81 @@ main_spi7: spi@2170000 {
clocks = <&k3_clks 383 1>;
status = "disabled";
};
+
+ mhdp: dp-bridge@a000000 {
+ compatible = "ti,j721e-mhdp8546";
+
+ reg = <0x0 0xa000000 0x0 0x30a00>,
+ <0x0 0x4f40000 0x0 0x20>;
+ reg-names = "mhdptx", "j721e-intg";
+
+ clocks = <&k3_clks 217 11>;
+
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 614 IRQ_TYPE_LEVEL_HIGH>;
+
+ power-domains = <&k3_pds 217 TI_SCI_PD_EXCLUSIVE>;
+
+ status = "disabled";
+
+ dp0_ports: ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
+ dss: dss@4a00000 {
+ compatible = "ti,j721e-dss";
+ reg =
+ <0x00 0x04a00000 0x00 0x10000>,
+ <0x00 0x04a10000 0x00 0x10000>,
+ <0x00 0x04b00000 0x00 0x10000>,
+ <0x00 0x04b10000 0x00 0x10000>,
+
+ <0x00 0x04a20000 0x00 0x10000>,
+ <0x00 0x04a30000 0x00 0x10000>,
+ <0x00 0x04a50000 0x00 0x10000>,
+ <0x00 0x04a60000 0x00 0x10000>,
+
+ <0x00 0x04a70000 0x00 0x10000>,
+ <0x00 0x04a90000 0x00 0x10000>,
+ <0x00 0x04ab0000 0x00 0x10000>,
+ <0x00 0x04ad0000 0x00 0x10000>,
+
+ <0x00 0x04a80000 0x00 0x10000>,
+ <0x00 0x04aa0000 0x00 0x10000>,
+ <0x00 0x04ac0000 0x00 0x10000>,
+ <0x00 0x04ae0000 0x00 0x10000>,
+ <0x00 0x04af0000 0x00 0x10000>;
+
+ reg-names = "common_m", "common_s0",
+ "common_s1", "common_s2",
+ "vidl1", "vidl2","vid1","vid2",
+ "ovr1", "ovr2", "ovr3", "ovr4",
+ "vp1", "vp2", "vp3", "vp4",
+ "wb";
+
+ clocks = <&k3_clks 218 0>,
+ <&k3_clks 218 2>,
+ <&k3_clks 218 5>,
+ <&k3_clks 218 14>,
+ <&k3_clks 218 18>;
+ clock-names = "fck", "vp1", "vp2", "vp3", "vp4";
+
+ power-domains = <&k3_pds 218 TI_SCI_PD_EXCLUSIVE>;
+
+ interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "common_m",
+ "common_s0",
+ "common_s1",
+ "common_s2";
+
+ status = "disabled";
+
+ dss_ports: ports {
+ };
+ };
};
--
2.25.1
On 19/04/2023 08:17, Jayesh Choudhary wrote:
> From: Rahul T R <[email protected]>
>
> Add DSS and DP-bridge node for J784S4 SoC. DSS IP in J784S4 is
> same as DSS IP in J721E, so same compatible is being used.
> The DP is Cadence MHDP8546.
>
> Signed-off-by: Rahul T R <[email protected]>
> [[email protected]: move all k3-j784s4-main.dtsi changes together]
> Signed-off-by: Jayesh Choudhary <[email protected]>
> ---
> arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 77 ++++++++++++++++++++++
> 1 file changed, 77 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
> index 51aa476dedba..739741e93bc1 100644
> --- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
> @@ -1373,4 +1373,81 @@ main_spi7: spi@2170000 {
> clocks = <&k3_clks 383 1>;
> status = "disabled";
> };
> +
> + mhdp: dp-bridge@a000000 {
> + compatible = "ti,j721e-mhdp8546";
> +
> + reg = <0x0 0xa000000 0x0 0x30a00>,
> + <0x0 0x4f40000 0x0 0x20>;
> + reg-names = "mhdptx", "j721e-intg";
> +
> + clocks = <&k3_clks 217 11>;
> +
> + interrupt-parent = <&gic500>;
> + interrupts = <GIC_SPI 614 IRQ_TYPE_LEVEL_HIGH>;
> +
> + power-domains = <&k3_pds 217 TI_SCI_PD_EXCLUSIVE>;
> +
> + status = "disabled";
> +
> + dp0_ports: ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> + };
> +
> + dss: dss@4a00000 {
> + compatible = "ti,j721e-dss";
> + reg =
> + <0x00 0x04a00000 0x00 0x10000>,
Fix indent/stray line break.
> + <0x00 0x04a10000 0x00 0x10000>,
> + <0x00 0x04b00000 0x00 0x10000>,
> + <0x00 0x04b10000 0x00 0x10000>,
> +
> + <0x00 0x04a20000 0x00 0x10000>,
> + <0x00 0x04a30000 0x00 0x10000>,
> + <0x00 0x04a50000 0x00 0x10000>,
> + <0x00 0x04a60000 0x00 0x10000>,
> +
> + <0x00 0x04a70000 0x00 0x10000>,
> + <0x00 0x04a90000 0x00 0x10000>,
> + <0x00 0x04ab0000 0x00 0x10000>,
> + <0x00 0x04ad0000 0x00 0x10000>,
> +
> + <0x00 0x04a80000 0x00 0x10000>,
> + <0x00 0x04aa0000 0x00 0x10000>,
> + <0x00 0x04ac0000 0x00 0x10000>,
> + <0x00 0x04ae0000 0x00 0x10000>,
> + <0x00 0x04af0000 0x00 0x10000>;
> +
> + reg-names = "common_m", "common_s0",
> + "common_s1", "common_s2",
> + "vidl1", "vidl2","vid1","vid2",
> + "ovr1", "ovr2", "ovr3", "ovr4",
> + "vp1", "vp2", "vp3", "vp4",
> + "wb";
> +
> + clocks = <&k3_clks 218 0>,
Broken indentation.
Best regards,
Krzysztof
On 19/04/23 13:21, Krzysztof Kozlowski wrote:
> On 19/04/2023 08:17, Jayesh Choudhary wrote:
>> From: Rahul T R <[email protected]>
>>
>> Add DSS and DP-bridge node for J784S4 SoC. DSS IP in J784S4 is
>> same as DSS IP in J721E, so same compatible is being used.
>> The DP is Cadence MHDP8546.
>>
>> Signed-off-by: Rahul T R <[email protected]>
>> [[email protected]: move all k3-j784s4-main.dtsi changes together]
>> Signed-off-by: Jayesh Choudhary <[email protected]>
>> ---
>> arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 77 ++++++++++++++++++++++
>> 1 file changed, 77 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
>> index 51aa476dedba..739741e93bc1 100644
>> --- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
>> +++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
>> @@ -1373,4 +1373,81 @@ main_spi7: spi@2170000 {
>> clocks = <&k3_clks 383 1>;
>> status = "disabled";
>> };
>> +
>> + mhdp: dp-bridge@a000000 {
>> + compatible = "ti,j721e-mhdp8546";
>> +
>> + reg = <0x0 0xa000000 0x0 0x30a00>,
>> + <0x0 0x4f40000 0x0 0x20>;
>> + reg-names = "mhdptx", "j721e-intg";
>> +
>> + clocks = <&k3_clks 217 11>;
>> +
>> + interrupt-parent = <&gic500>;
>> + interrupts = <GIC_SPI 614 IRQ_TYPE_LEVEL_HIGH>;
>> +
>> + power-domains = <&k3_pds 217 TI_SCI_PD_EXCLUSIVE>;
>> +
>> + status = "disabled";
>> +
>> + dp0_ports: ports {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + };
>> + };
>> +
>> + dss: dss@4a00000 {
>> + compatible = "ti,j721e-dss";
>> + reg =
>> + <0x00 0x04a00000 0x00 0x10000>,
>
> Fix indent/stray line break.
>
>> + <0x00 0x04a10000 0x00 0x10000>,
>> + <0x00 0x04b00000 0x00 0x10000>,
>> + <0x00 0x04b10000 0x00 0x10000>,
>> +
>> + <0x00 0x04a20000 0x00 0x10000>,
>> + <0x00 0x04a30000 0x00 0x10000>,
>> + <0x00 0x04a50000 0x00 0x10000>,
>> + <0x00 0x04a60000 0x00 0x10000>,
>> +
>> + <0x00 0x04a70000 0x00 0x10000>,
>> + <0x00 0x04a90000 0x00 0x10000>,
>> + <0x00 0x04ab0000 0x00 0x10000>,
>> + <0x00 0x04ad0000 0x00 0x10000>,
>> +
>> + <0x00 0x04a80000 0x00 0x10000>,
>> + <0x00 0x04aa0000 0x00 0x10000>,
>> + <0x00 0x04ac0000 0x00 0x10000>,
>> + <0x00 0x04ae0000 0x00 0x10000>,
>> + <0x00 0x04af0000 0x00 0x10000>;
>> +
>> + reg-names = "common_m", "common_s0",
>> + "common_s1", "common_s2",
>> + "vidl1", "vidl2","vid1","vid2",
>> + "ovr1", "ovr2", "ovr3", "ovr4",
>> + "vp1", "vp2", "vp3", "vp4",
>> + "wb";
>> +
>> + clocks = <&k3_clks 218 0>,
>
> Broken indentation.
Indentation at both places are similar to j721e dss node.
Changes are needed in both?
-Jayesh
>
>
>
> Best regards,
> Krzysztof
>
On 19/04/2023 12:35, Jayesh Choudhary wrote:
>>> + reg-names = "common_m", "common_s0",
>>> + "common_s1", "common_s2",
>>> + "vidl1", "vidl2","vid1","vid2",
>>> + "ovr1", "ovr2", "ovr3", "ovr4",
>>> + "vp1", "vp2", "vp3", "vp4",
>>> + "wb";
>>> +
>>> + clocks = <&k3_clks 218 0>,
>>
>> Broken indentation.
>
> Indentation at both places are similar to j721e dss node.
> Changes are needed in both?
There is no DTS coding style which uses indentation before or after '='.
Just because some DTS are written wrong, should not encourage you to do
the same...
I am commenting only on this patch - it is not correct. What is wrong in
other files should be fixed in other places, not relevant to this patch.
Best regards,
Krzysztof