2023-05-07 15:16:31

by Maksim Kiselev

Subject: [PATCH v4 0/5] Allwinner R329/D1/R528/T113s SPI support

This series is attempt to revive previous work to add support for SPI
controller which is used in newest Allwinner's SOCs R329/D1/R528/T113s
https://lore.kernel.org/lkml/BYAPR20MB2472E8B10BFEF75E7950BBC0BCF79@BYAPR20MB2472.namprd20.prod.outlook.com/

v4:
- fixed SPI sample mode configuration
- sorted DT bindings list

v3:
- fixed effective_speed_hz setup and added SPI sample mode configuration
- merged DT bindings for R329 and D1 SPI controllers
- added SPI_DBI node to sunxi-d1s-t113.dtsi

v2:
- added DT bindings and node for D1/T113s

Icenowy Zheng (1):
spi: sun6i: change OF match data to a struct

Maksim Kiselev (4):
dt-bindings: spi: sun6i: add DT bindings for Allwinner
R329/D1/R528/T113s SPI
spi: sun6i: add quirk for in-controller clock divider
spi: sun6i: add support for R329/D1/R528/T113s SPI controllers
riscv: dts: allwinner: d1: Add SPI controllers node

.../bindings/spi/allwinner,sun6i-a31-spi.yaml | 7 +
.../boot/dts/allwinner/sunxi-d1s-t113.dtsi | 37 +++++
drivers/spi/spi-sun6i.c | 131 ++++++++++++------
3 files changed, 135 insertions(+), 40 deletions(-)

--
2.39.2

2023-05-07 15:18:10

by Maksim Kiselev

Subject: [PATCH v4 5/5] riscv: dts: allwinner: d1: Add SPI controllers node

Some boards form the MangoPi family (MQ\MQ-Dual\MQ-R) may have
an optional SPI flash that connects to the SPI0 controller.

This controller is the same for R329/D1/R528/T113s SoCs and
should be supported by the sun50i-r329-spi driver.

So let's add its DT nodes.

Signed-off-by: Maksim Kiselev <[email protected]>
Acked-by: Conor Dooley <[email protected]>
Reviewed-by: Andre Przywara <[email protected]>
---
.../boot/dts/allwinner/sunxi-d1s-t113.dtsi | 37 +++++++++++++++++++
1 file changed, 37 insertions(+)

diff --git a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi
index 922e8e0e2c09..1bb1e5cae602 100644
--- a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi
+++ b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi
@@ -108,6 +108,12 @@ rmii_pe_pins: rmii-pe-pins {
function = "emac";
};

+ /omit-if-no-ref/
+ spi0_pins: spi0-pins {
+ pins = "PC2", "PC3", "PC4", "PC5";
+ function = "spi0";
+ };
+
/omit-if-no-ref/
uart1_pg6_pins: uart1-pg6-pins {
pins = "PG6", "PG7";
@@ -447,6 +453,37 @@ mmc2: mmc@4022000 {
#size-cells = <0>;
};

+ spi0: spi@4025000 {
+ compatible = "allwinner,sun20i-d1-spi",
+ "allwinner,sun50i-r329-spi";
+ reg = <0x04025000 0x1000>;
+ interrupts = <SOC_PERIPHERAL_IRQ(15) IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
+ clock-names = "ahb", "mod";
+ dmas = <&dma 22>, <&dma 22>;
+ dma-names = "rx", "tx";
+ resets = <&ccu RST_BUS_SPI0>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ spi1: spi@4026000 {
+ compatible = "allwinner,sun20i-d1-spi-dbi",
+ "allwinner,sun50i-r329-spi-dbi",
+ "allwinner,sun50i-r329-spi";
+ reg = <0x04026000 0x1000>;
+ interrupts = <SOC_PERIPHERAL_IRQ(16) IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
+ clock-names = "ahb", "mod";
+ dmas = <&dma 23>, <&dma 23>;
+ dma-names = "rx", "tx";
+ resets = <&ccu RST_BUS_SPI1>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
usb_otg: usb@4100000 {
compatible = "allwinner,sun20i-d1-musb",
"allwinner,sun8i-a33-musb";
--
2.39.2