The IPQ5018 is Qualcomm's 802.11ax SoC for Routers,
Gateways and Access Points.
This series adds minimal board boot support for ipq5018-mp03.1-c2 board.
[v6] Fixed patch [4/8] pinctrl driver for rebase issue.
[v5]
Added Reviewed-by tags from Krzysztof Kozlowski.
Changed patch [6/8] with [1] since its already Acked
Rebased patch [4/8] on top of [2] and fixed other comments
Fixed commit log for patch [7/8]
Fixed comments for patch [2/8]
[1] https://patchwork.kernel.org/project/linux-arm-msm/patch/[email protected]/
[2] https://lore.kernel.org/r/[email protected]
[v4]
Fixed all comments for clocks, schema, dts
Added Reviewed-by tags.
[v3]
Fixed all comments for clocks, schema fixes
Picked up Reviewed-by from Bjorn for pinctrl driver
[v2]
Fixed all comments and rebased for TOT.
Manikanta Mylavarapu (1):
dt-bindings: scm: Add compatible for IPQ5018
Sricharan Ramabadhran (7):
dt-bindings: arm64: Add IPQ5018 clock and reset
clk: qcom: Add Global Clock controller (GCC) driver for IPQ5018
dt-bindings: pinctrl: qcom: Add support for ipq5018
pinctrl: qcom: Add IPQ5018 pinctrl driver
dt-bindings: qcom: Add ipq5018 bindings
arm64: dts: Add ipq5018 SoC and rdp432-c2 board support
arm64: defconfig: Enable IPQ5018 SoC base configs
.../devicetree/bindings/arm/qcom.yaml | 7 +
.../bindings/clock/qcom,ipq5018-gcc.yaml | 63 +
.../bindings/firmware/qcom,scm.yaml | 1 +
.../bindings/pinctrl/qcom,ipq5018-tlmm.yaml | 127 +
arch/arm64/boot/dts/qcom/Makefile | 1 +
.../arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts | 72 +
arch/arm64/boot/dts/qcom/ipq5018.dtsi | 250 ++
arch/arm64/configs/defconfig | 3 +
drivers/clk/qcom/Kconfig | 10 +-
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/gcc-ipq5018.c | 3731 +++++++++++++++++
drivers/pinctrl/qcom/Kconfig | 10 +
drivers/pinctrl/qcom/Makefile | 1 +
drivers/pinctrl/qcom/pinctrl-ipq5018.c | 783 ++++
include/dt-bindings/clock/qcom,gcc-ipq5018.h | 183 +
include/dt-bindings/reset/qcom,gcc-ipq5018.h | 122 +
16 files changed, 5363 insertions(+), 2 deletions(-)
create mode 100644 Documentation/devicetree/bindings/clock/qcom,ipq5018-gcc.yaml
create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,ipq5018-tlmm.yaml
create mode 100644 arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts
create mode 100644 arch/arm64/boot/dts/qcom/ipq5018.dtsi
create mode 100644 drivers/clk/qcom/gcc-ipq5018.c
create mode 100644 drivers/pinctrl/qcom/pinctrl-ipq5018.c
create mode 100644 include/dt-bindings/clock/qcom,gcc-ipq5018.h
create mode 100644 include/dt-bindings/reset/qcom,gcc-ipq5018.h
--
2.34.1
Add pinctrl definitions for the TLMM of IPQ5018.
Reviewed-by: Bjorn Andersson <[email protected]>
Co-developed-by: Nitheesh Sekar <[email protected]>
Signed-off-by: Nitheesh Sekar <[email protected]>
Co-developed-by: Varadarajan Narayanan <[email protected]>
Signed-off-by: Varadarajan Narayanan <[email protected]>
Signed-off-by: Sricharan Ramabadhran <[email protected]>
---
[v6] Rebased patch on top of "Add pinctrl support for SDX75" series
and fixed other comments from [email protected]
drivers/pinctrl/qcom/Kconfig | 10 +
drivers/pinctrl/qcom/Makefile | 1 +
drivers/pinctrl/qcom/pinctrl-ipq5018.c | 783 +++++++++++++++++++++++++
3 files changed, 794 insertions(+)
create mode 100644 drivers/pinctrl/qcom/pinctrl-ipq5018.c
diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig
index e5c89b8bb7a3..200e89e40780 100644
--- a/drivers/pinctrl/qcom/Kconfig
+++ b/drivers/pinctrl/qcom/Kconfig
@@ -39,6 +39,16 @@ config PINCTRL_IPQ4019
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm TLMM block found in the Qualcomm IPQ4019 platform.
+config PINCTRL_IPQ5018
+ tristate "Qualcomm Technologies, Inc. IPQ5018 pin controller driver"
+ depends on GPIOLIB && OF
+ select PINCTRL_MSM
+ help
+ This is the pinctrl, pinmux, pinconf and gpiolib driver for
+ the Qualcomm Technologies Inc. TLMM block found on the
+ Qualcomm Technologies Inc. IPQ5018 platform. Select this for
+ IPQ5018.
+
config PINCTRL_IPQ8064
tristate "Qualcomm IPQ8064 pin controller driver"
depends on OF
diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile
index 2dbb0d708ad3..02a0d2f7f270 100644
--- a/drivers/pinctrl/qcom/Makefile
+++ b/drivers/pinctrl/qcom/Makefile
@@ -4,6 +4,7 @@ obj-$(CONFIG_PINCTRL_MSM) += pinctrl-msm.o
obj-$(CONFIG_PINCTRL_APQ8064) += pinctrl-apq8064.o
obj-$(CONFIG_PINCTRL_APQ8084) += pinctrl-apq8084.o
obj-$(CONFIG_PINCTRL_IPQ4019) += pinctrl-ipq4019.o
+obj-$(CONFIG_PINCTRL_IPQ5018) += pinctrl-ipq5018.o
obj-$(CONFIG_PINCTRL_IPQ8064) += pinctrl-ipq8064.o
obj-$(CONFIG_PINCTRL_IPQ5332) += pinctrl-ipq5332.o
obj-$(CONFIG_PINCTRL_IPQ8074) += pinctrl-ipq8074.o
diff --git a/drivers/pinctrl/qcom/pinctrl-ipq5018.c b/drivers/pinctrl/qcom/pinctrl-ipq5018.c
new file mode 100644
index 000000000000..3eb92a9259a3
--- /dev/null
+++ b/drivers/pinctrl/qcom/pinctrl-ipq5018.c
@@ -0,0 +1,783 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2019-2021, 2023 The Linux Foundation. All rights reserved.
+ */
+
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+
+#include "pinctrl-msm.h"
+
+#define REG_SIZE 0x1000
+#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9) \
+ { \
+ .grp = PINCTRL_PINGROUP("gpio" #id, \
+ gpio##id##_pins, \
+ ARRAY_SIZE(gpio##id##_pins)), \
+ .funcs = (int[]){ \
+ msm_mux_gpio, /* gpio mode */ \
+ msm_mux_##f1, \
+ msm_mux_##f2, \
+ msm_mux_##f3, \
+ msm_mux_##f4, \
+ msm_mux_##f5, \
+ msm_mux_##f6, \
+ msm_mux_##f7, \
+ msm_mux_##f8, \
+ msm_mux_##f9 \
+ }, \
+ .nfuncs = 10, \
+ .ctl_reg = REG_SIZE * id, \
+ .io_reg = 0x4 + REG_SIZE * id, \
+ .intr_cfg_reg = 0x8 + REG_SIZE * id, \
+ .intr_status_reg = 0xc + REG_SIZE * id, \
+ .intr_target_reg = 0x8 + REG_SIZE * id, \
+ .mux_bit = 2, \
+ .pull_bit = 0, \
+ .drv_bit = 6, \
+ .oe_bit = 9, \
+ .in_bit = 0, \
+ .out_bit = 1, \
+ .intr_enable_bit = 0, \
+ .intr_status_bit = 0, \
+ .intr_target_bit = 5, \
+ .intr_target_kpss_val = 3, \
+ .intr_raw_status_bit = 4, \
+ .intr_polarity_bit = 1, \
+ .intr_detection_bit = 2, \
+ .intr_detection_width = 2, \
+ }
+
+static const struct pinctrl_pin_desc ipq5018_pins[] = {
+ PINCTRL_PIN(0, "GPIO_0"),
+ PINCTRL_PIN(1, "GPIO_1"),
+ PINCTRL_PIN(2, "GPIO_2"),
+ PINCTRL_PIN(3, "GPIO_3"),
+ PINCTRL_PIN(4, "GPIO_4"),
+ PINCTRL_PIN(5, "GPIO_5"),
+ PINCTRL_PIN(6, "GPIO_6"),
+ PINCTRL_PIN(7, "GPIO_7"),
+ PINCTRL_PIN(8, "GPIO_8"),
+ PINCTRL_PIN(9, "GPIO_9"),
+ PINCTRL_PIN(10, "GPIO_10"),
+ PINCTRL_PIN(11, "GPIO_11"),
+ PINCTRL_PIN(12, "GPIO_12"),
+ PINCTRL_PIN(13, "GPIO_13"),
+ PINCTRL_PIN(14, "GPIO_14"),
+ PINCTRL_PIN(15, "GPIO_15"),
+ PINCTRL_PIN(16, "GPIO_16"),
+ PINCTRL_PIN(17, "GPIO_17"),
+ PINCTRL_PIN(18, "GPIO_18"),
+ PINCTRL_PIN(19, "GPIO_19"),
+ PINCTRL_PIN(20, "GPIO_20"),
+ PINCTRL_PIN(21, "GPIO_21"),
+ PINCTRL_PIN(22, "GPIO_22"),
+ PINCTRL_PIN(23, "GPIO_23"),
+ PINCTRL_PIN(24, "GPIO_24"),
+ PINCTRL_PIN(25, "GPIO_25"),
+ PINCTRL_PIN(26, "GPIO_26"),
+ PINCTRL_PIN(27, "GPIO_27"),
+ PINCTRL_PIN(28, "GPIO_28"),
+ PINCTRL_PIN(29, "GPIO_29"),
+ PINCTRL_PIN(30, "GPIO_30"),
+ PINCTRL_PIN(31, "GPIO_31"),
+ PINCTRL_PIN(32, "GPIO_32"),
+ PINCTRL_PIN(33, "GPIO_33"),
+ PINCTRL_PIN(34, "GPIO_34"),
+ PINCTRL_PIN(35, "GPIO_35"),
+ PINCTRL_PIN(36, "GPIO_36"),
+ PINCTRL_PIN(37, "GPIO_37"),
+ PINCTRL_PIN(38, "GPIO_38"),
+ PINCTRL_PIN(39, "GPIO_39"),
+ PINCTRL_PIN(40, "GPIO_40"),
+ PINCTRL_PIN(41, "GPIO_41"),
+ PINCTRL_PIN(42, "GPIO_42"),
+ PINCTRL_PIN(43, "GPIO_43"),
+ PINCTRL_PIN(44, "GPIO_44"),
+ PINCTRL_PIN(45, "GPIO_45"),
+ PINCTRL_PIN(46, "GPIO_46"),
+};
+
+#define DECLARE_MSM_GPIO_PINS(pin) \
+ static const unsigned int gpio##pin##_pins[] = { pin }
+DECLARE_MSM_GPIO_PINS(0);
+DECLARE_MSM_GPIO_PINS(1);
+DECLARE_MSM_GPIO_PINS(2);
+DECLARE_MSM_GPIO_PINS(3);
+DECLARE_MSM_GPIO_PINS(4);
+DECLARE_MSM_GPIO_PINS(5);
+DECLARE_MSM_GPIO_PINS(6);
+DECLARE_MSM_GPIO_PINS(7);
+DECLARE_MSM_GPIO_PINS(8);
+DECLARE_MSM_GPIO_PINS(9);
+DECLARE_MSM_GPIO_PINS(10);
+DECLARE_MSM_GPIO_PINS(11);
+DECLARE_MSM_GPIO_PINS(12);
+DECLARE_MSM_GPIO_PINS(13);
+DECLARE_MSM_GPIO_PINS(14);
+DECLARE_MSM_GPIO_PINS(15);
+DECLARE_MSM_GPIO_PINS(16);
+DECLARE_MSM_GPIO_PINS(17);
+DECLARE_MSM_GPIO_PINS(18);
+DECLARE_MSM_GPIO_PINS(19);
+DECLARE_MSM_GPIO_PINS(20);
+DECLARE_MSM_GPIO_PINS(21);
+DECLARE_MSM_GPIO_PINS(22);
+DECLARE_MSM_GPIO_PINS(23);
+DECLARE_MSM_GPIO_PINS(24);
+DECLARE_MSM_GPIO_PINS(25);
+DECLARE_MSM_GPIO_PINS(26);
+DECLARE_MSM_GPIO_PINS(27);
+DECLARE_MSM_GPIO_PINS(28);
+DECLARE_MSM_GPIO_PINS(29);
+DECLARE_MSM_GPIO_PINS(30);
+DECLARE_MSM_GPIO_PINS(31);
+DECLARE_MSM_GPIO_PINS(32);
+DECLARE_MSM_GPIO_PINS(33);
+DECLARE_MSM_GPIO_PINS(34);
+DECLARE_MSM_GPIO_PINS(35);
+DECLARE_MSM_GPIO_PINS(36);
+DECLARE_MSM_GPIO_PINS(37);
+DECLARE_MSM_GPIO_PINS(38);
+DECLARE_MSM_GPIO_PINS(39);
+DECLARE_MSM_GPIO_PINS(40);
+DECLARE_MSM_GPIO_PINS(41);
+DECLARE_MSM_GPIO_PINS(42);
+DECLARE_MSM_GPIO_PINS(43);
+DECLARE_MSM_GPIO_PINS(44);
+DECLARE_MSM_GPIO_PINS(45);
+DECLARE_MSM_GPIO_PINS(46);
+
+enum ipq5018_functions {
+ msm_mux_atest_char,
+ msm_mux_audio_pdm0,
+ msm_mux_audio_pdm1,
+ msm_mux_audio_rxbclk,
+ msm_mux_audio_rxd,
+ msm_mux_audio_rxfsync,
+ msm_mux_audio_rxmclk,
+ msm_mux_audio_txbclk,
+ msm_mux_audio_txd,
+ msm_mux_audio_txfsync,
+ msm_mux_audio_txmclk,
+ msm_mux_blsp0_i2c,
+ msm_mux_blsp0_spi,
+ msm_mux_blsp0_uart0,
+ msm_mux_blsp0_uart1,
+ msm_mux_blsp1_i2c0,
+ msm_mux_blsp1_i2c1,
+ msm_mux_blsp1_spi0,
+ msm_mux_blsp1_spi1,
+ msm_mux_blsp1_uart0,
+ msm_mux_blsp1_uart1,
+ msm_mux_blsp1_uart2,
+ msm_mux_blsp2_i2c0,
+ msm_mux_blsp2_i2c1,
+ msm_mux_blsp2_spi,
+ msm_mux_blsp2_spi0,
+ msm_mux_blsp2_spi1,
+ msm_mux_btss,
+ msm_mux_burn0,
+ msm_mux_burn1,
+ msm_mux_cri_trng,
+ msm_mux_cri_trng0,
+ msm_mux_cri_trng1,
+ msm_mux_cxc_clk,
+ msm_mux_cxc_data,
+ msm_mux_dbg_out,
+ msm_mux_eud_gpio,
+ msm_mux_gcc_plltest,
+ msm_mux_gcc_tlmm,
+ msm_mux_gpio,
+ msm_mux_led0,
+ msm_mux_led2,
+ msm_mux_mac0,
+ msm_mux_mac1,
+ msm_mux_mdc,
+ msm_mux_mdio,
+ msm_mux_pcie0_clk,
+ msm_mux_pcie0_wake,
+ msm_mux_pcie1_clk,
+ msm_mux_pcie1_wake,
+ msm_mux_pll_test,
+ msm_mux_prng_rosc,
+ msm_mux_pwm0,
+ msm_mux_pwm1,
+ msm_mux_pwm2,
+ msm_mux_pwm3,
+ msm_mux_qdss_cti_trig_in_a0,
+ msm_mux_qdss_cti_trig_in_a1,
+ msm_mux_qdss_cti_trig_in_b0,
+ msm_mux_qdss_cti_trig_in_b1,
+ msm_mux_qdss_cti_trig_out_a0,
+ msm_mux_qdss_cti_trig_out_a1,
+ msm_mux_qdss_cti_trig_out_b0,
+ msm_mux_qdss_cti_trig_out_b1,
+ msm_mux_qdss_traceclk_a,
+ msm_mux_qdss_traceclk_b,
+ msm_mux_qdss_tracectl_a,
+ msm_mux_qdss_tracectl_b,
+ msm_mux_qdss_tracedata_a,
+ msm_mux_qdss_tracedata_b,
+ msm_mux_qspi_clk,
+ msm_mux_qspi_cs,
+ msm_mux_qspi_data,
+ msm_mux_reset_out,
+ msm_mux_sdc1_clk,
+ msm_mux_sdc1_cmd,
+ msm_mux_sdc1_data,
+ msm_mux_wci_txd,
+ msm_mux_wci_rxd,
+ msm_mux_wsa_swrm,
+ msm_mux_wsi_clk3,
+ msm_mux_wsi_data3,
+ msm_mux_wsis_reset,
+ msm_mux_xfem,
+ msm_mux__,
+};
+
+static const char * const atest_char_groups[] = {
+ "gpio0", "gpio1", "gpio2", "gpio3", "gpio37",
+};
+
+static const char * const _groups[] = {
+ "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7",
+ "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14",
+ "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21",
+ "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28",
+ "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35",
+ "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42",
+ "gpio43", "gpio44", "gpio45", "gpio46",
+};
+
+static const char * const wci_txd_groups[] = {
+ "gpio0", "gpio1", "gpio2", "gpio3",
+ "gpio42", "gpio43", "gpio44", "gpio45",
+};
+
+static const char * const wci_rxd_groups[] = {
+ "gpio0", "gpio1", "gpio2", "gpio3",
+ "gpio42", "gpio43", "gpio44", "gpio45",
+};
+
+static const char * const xfem_groups[] = {
+ "gpio0", "gpio1", "gpio2", "gpio3",
+ "gpio42", "gpio43", "gpio44", "gpio45",
+};
+
+static const char * const qdss_cti_trig_out_a0_groups[] = {
+ "gpio0",
+};
+
+static const char * const qdss_cti_trig_in_a0_groups[] = {
+ "gpio1",
+};
+
+static const char * const qdss_cti_trig_out_a1_groups[] = {
+ "gpio2",
+};
+
+static const char * const qdss_cti_trig_in_a1_groups[] = {
+ "gpio3",
+};
+
+static const char * const sdc1_data_groups[] = {
+ "gpio4", "gpio5", "gpio6", "gpio7",
+};
+
+static const char * const qspi_data_groups[] = {
+ "gpio4",
+ "gpio5",
+ "gpio6",
+ "gpio7",
+};
+
+static const char * const blsp1_spi1_groups[] = {
+ "gpio4", "gpio5", "gpio6", "gpio7",
+};
+
+static const char * const btss_groups[] = {
+ "gpio4", "gpio5", "gpio6", "gpio7", "gpio8", "gpio17", "gpio18",
+ "gpio19", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28",
+};
+
+static const char * const dbg_out_groups[] = {
+ "gpio4",
+};
+
+static const char * const qdss_traceclk_a_groups[] = {
+ "gpio4",
+};
+
+static const char * const burn0_groups[] = {
+ "gpio4",
+};
+
+static const char * const cxc_clk_groups[] = {
+ "gpio5",
+};
+
+static const char * const blsp1_i2c1_groups[] = {
+ "gpio5", "gpio6",
+};
+
+static const char * const qdss_tracectl_a_groups[] = {
+ "gpio5",
+};
+
+static const char * const burn1_groups[] = {
+ "gpio5",
+};
+
+static const char * const cxc_data_groups[] = {
+ "gpio6",
+};
+
+static const char * const qdss_tracedata_a_groups[] = {
+ "gpio6", "gpio7", "gpio8", "gpio9", "gpio10", "gpio11", "gpio12",
+ "gpio13", "gpio14", "gpio15", "gpio16", "gpio17", "gpio18", "gpio19",
+ "gpio20", "gpio21",
+};
+
+static const char * const mac0_groups[] = {
+ "gpio7",
+};
+
+static const char * const sdc1_cmd_groups[] = {
+ "gpio8",
+};
+
+static const char * const qspi_cs_groups[] = {
+ "gpio8",
+};
+
+static const char * const mac1_groups[] = {
+ "gpio8",
+};
+
+static const char * const sdc1_clk_groups[] = {
+ "gpio9",
+};
+
+static const char * const qspi_clk_groups[] = {
+ "gpio9",
+};
+
+static const char * const blsp0_spi_groups[] = {
+ "gpio10", "gpio11", "gpio12", "gpio13",
+};
+
+static const char * const blsp1_uart0_groups[] = {
+ "gpio10", "gpio11", "gpio12", "gpio13",
+};
+
+static const char * const gcc_plltest_groups[] = {
+ "gpio10", "gpio12",
+};
+
+static const char * const gcc_tlmm_groups[] = {
+ "gpio11",
+};
+
+static const char * const blsp0_i2c_groups[] = {
+ "gpio12", "gpio13",
+};
+
+static const char * const pcie0_clk_groups[] = {
+ "gpio14",
+};
+
+static const char * const cri_trng0_groups[] = {
+ "gpio14",
+};
+
+static const char * const cri_trng1_groups[] = {
+ "gpio15",
+};
+
+static const char * const pcie0_wake_groups[] = {
+ "gpio16",
+};
+
+static const char * const cri_trng_groups[] = {
+ "gpio16",
+};
+
+static const char * const pcie1_clk_groups[] = {
+ "gpio17",
+};
+
+static const char * const prng_rosc_groups[] = {
+ "gpio17",
+};
+
+static const char * const blsp1_spi0_groups[] = {
+ "gpio18", "gpio19", "gpio20", "gpio21",
+};
+
+static const char * const pcie1_wake_groups[] = {
+ "gpio19",
+};
+
+static const char * const blsp1_i2c0_groups[] = {
+ "gpio19", "gpio20",
+};
+
+static const char * const blsp0_uart0_groups[] = {
+ "gpio20", "gpio21",
+};
+
+static const char * const pll_test_groups[] = {
+ "gpio22",
+};
+
+static const char * const eud_gpio_groups[] = {
+ "gpio22", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35",
+};
+
+static const char * const audio_rxmclk_groups[] = {
+ "gpio23", "gpio23",
+};
+
+static const char * const audio_pdm0_groups[] = {
+ "gpio23", "gpio24",
+};
+
+static const char * const blsp2_spi1_groups[] = {
+ "gpio23", "gpio24", "gpio25", "gpio26",
+};
+
+static const char * const blsp1_uart2_groups[] = {
+ "gpio23", "gpio24", "gpio25", "gpio26",
+};
+
+static const char * const qdss_tracedata_b_groups[] = {
+ "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio29",
+ "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", "gpio36",
+ "gpio37", "gpio38",
+};
+
+static const char * const audio_rxbclk_groups[] = {
+ "gpio24",
+};
+
+static const char * const audio_rxfsync_groups[] = {
+ "gpio25",
+};
+
+static const char * const audio_pdm1_groups[] = {
+ "gpio25", "gpio26",
+};
+
+static const char * const blsp2_i2c1_groups[] = {
+ "gpio25", "gpio26",
+};
+
+static const char * const audio_rxd_groups[] = {
+ "gpio26",
+};
+
+static const char * const audio_txmclk_groups[] = {
+ "gpio27", "gpio27",
+};
+
+static const char * const wsa_swrm_groups[] = {
+ "gpio27", "gpio28",
+};
+
+static const char * const blsp2_spi_groups[] = {
+ "gpio27",
+};
+
+static const char * const audio_txbclk_groups[] = {
+ "gpio28",
+};
+
+static const char * const blsp0_uart1_groups[] = {
+ "gpio28", "gpio29",
+};
+
+static const char * const audio_txfsync_groups[] = {
+ "gpio29",
+};
+
+static const char * const audio_txd_groups[] = {
+ "gpio30",
+};
+
+static const char * const wsis_reset_groups[] = {
+ "gpio30",
+};
+
+static const char * const blsp2_spi0_groups[] = {
+ "gpio31", "gpio32", "gpio33", "gpio34",
+};
+
+static const char * const blsp1_uart1_groups[] = {
+ "gpio31", "gpio32", "gpio33", "gpio34",
+};
+
+static const char * const blsp2_i2c0_groups[] = {
+ "gpio33", "gpio34",
+};
+
+static const char * const mdc_groups[] = {
+ "gpio36",
+};
+
+static const char * const wsi_clk3_groups[] = {
+ "gpio36",
+};
+
+static const char * const mdio_groups[] = {
+ "gpio37",
+};
+
+static const char * const wsi_data3_groups[] = {
+ "gpio37",
+};
+
+static const char * const qdss_traceclk_b_groups[] = {
+ "gpio39",
+};
+
+static const char * const reset_out_groups[] = {
+ "gpio40",
+};
+
+static const char * const qdss_tracectl_b_groups[] = {
+ "gpio40",
+};
+
+static const char * const pwm0_groups[] = {
+ "gpio42",
+};
+
+static const char * const qdss_cti_trig_out_b0_groups[] = {
+ "gpio42",
+};
+
+static const char * const pwm1_groups[] = {
+ "gpio43",
+};
+
+static const char * const qdss_cti_trig_in_b0_groups[] = {
+ "gpio43",
+};
+
+static const char * const pwm2_groups[] = {
+ "gpio44",
+};
+
+static const char * const qdss_cti_trig_out_b1_groups[] = {
+ "gpio44",
+};
+
+static const char * const pwm3_groups[] = {
+ "gpio45",
+};
+
+static const char * const qdss_cti_trig_in_b1_groups[] = {
+ "gpio45",
+};
+
+static const char * const led0_groups[] = {
+ "gpio46", "gpio30", "gpio10",
+};
+
+static const char * const led2_groups[] = {
+ "gpio30",
+};
+
+static const char * const gpio_groups[] = {
+ "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7",
+ "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14",
+ "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21",
+ "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28",
+ "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35",
+ "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42",
+ "gpio43", "gpio44", "gpio45", "gpio46",
+};
+
+static const struct pinfunction ipq5018_functions[] = {
+ MSM_PIN_FUNCTION(atest_char),
+ MSM_PIN_FUNCTION(audio_pdm0),
+ MSM_PIN_FUNCTION(audio_pdm1),
+ MSM_PIN_FUNCTION(audio_rxbclk),
+ MSM_PIN_FUNCTION(audio_rxd),
+ MSM_PIN_FUNCTION(audio_rxfsync),
+ MSM_PIN_FUNCTION(audio_rxmclk),
+ MSM_PIN_FUNCTION(audio_txbclk),
+ MSM_PIN_FUNCTION(audio_txd),
+ MSM_PIN_FUNCTION(audio_txfsync),
+ MSM_PIN_FUNCTION(audio_txmclk),
+ MSM_PIN_FUNCTION(blsp0_i2c),
+ MSM_PIN_FUNCTION(blsp0_spi),
+ MSM_PIN_FUNCTION(blsp0_uart0),
+ MSM_PIN_FUNCTION(blsp0_uart1),
+ MSM_PIN_FUNCTION(blsp1_i2c0),
+ MSM_PIN_FUNCTION(blsp1_i2c1),
+ MSM_PIN_FUNCTION(blsp1_spi0),
+ MSM_PIN_FUNCTION(blsp1_spi1),
+ MSM_PIN_FUNCTION(blsp1_uart0),
+ MSM_PIN_FUNCTION(blsp1_uart1),
+ MSM_PIN_FUNCTION(blsp1_uart2),
+ MSM_PIN_FUNCTION(blsp2_i2c0),
+ MSM_PIN_FUNCTION(blsp2_i2c1),
+ MSM_PIN_FUNCTION(blsp2_spi),
+ MSM_PIN_FUNCTION(blsp2_spi0),
+ MSM_PIN_FUNCTION(blsp2_spi1),
+ MSM_PIN_FUNCTION(btss),
+ MSM_PIN_FUNCTION(burn0),
+ MSM_PIN_FUNCTION(burn1),
+ MSM_PIN_FUNCTION(cri_trng),
+ MSM_PIN_FUNCTION(cri_trng0),
+ MSM_PIN_FUNCTION(cri_trng1),
+ MSM_PIN_FUNCTION(cxc_clk),
+ MSM_PIN_FUNCTION(cxc_data),
+ MSM_PIN_FUNCTION(dbg_out),
+ MSM_PIN_FUNCTION(eud_gpio),
+ MSM_PIN_FUNCTION(gcc_plltest),
+ MSM_PIN_FUNCTION(gcc_tlmm),
+ MSM_PIN_FUNCTION(gpio),
+ MSM_PIN_FUNCTION(led0),
+ MSM_PIN_FUNCTION(led2),
+ MSM_PIN_FUNCTION(mac0),
+ MSM_PIN_FUNCTION(mac1),
+ MSM_PIN_FUNCTION(mdc),
+ MSM_PIN_FUNCTION(mdio),
+ MSM_PIN_FUNCTION(pcie0_clk),
+ MSM_PIN_FUNCTION(pcie0_wake),
+ MSM_PIN_FUNCTION(pcie1_clk),
+ MSM_PIN_FUNCTION(pcie1_wake),
+ MSM_PIN_FUNCTION(pll_test),
+ MSM_PIN_FUNCTION(prng_rosc),
+ MSM_PIN_FUNCTION(pwm0),
+ MSM_PIN_FUNCTION(pwm1),
+ MSM_PIN_FUNCTION(pwm2),
+ MSM_PIN_FUNCTION(pwm3),
+ MSM_PIN_FUNCTION(qdss_cti_trig_in_a0),
+ MSM_PIN_FUNCTION(qdss_cti_trig_in_a1),
+ MSM_PIN_FUNCTION(qdss_cti_trig_in_b0),
+ MSM_PIN_FUNCTION(qdss_cti_trig_in_b1),
+ MSM_PIN_FUNCTION(qdss_cti_trig_out_a0),
+ MSM_PIN_FUNCTION(qdss_cti_trig_out_a1),
+ MSM_PIN_FUNCTION(qdss_cti_trig_out_b0),
+ MSM_PIN_FUNCTION(qdss_cti_trig_out_b1),
+ MSM_PIN_FUNCTION(qdss_traceclk_a),
+ MSM_PIN_FUNCTION(qdss_traceclk_b),
+ MSM_PIN_FUNCTION(qdss_tracectl_a),
+ MSM_PIN_FUNCTION(qdss_tracectl_b),
+ MSM_PIN_FUNCTION(qdss_tracedata_a),
+ MSM_PIN_FUNCTION(qdss_tracedata_b),
+ MSM_PIN_FUNCTION(qspi_clk),
+ MSM_PIN_FUNCTION(qspi_cs),
+ MSM_PIN_FUNCTION(qspi_data),
+ MSM_PIN_FUNCTION(reset_out),
+ MSM_PIN_FUNCTION(sdc1_clk),
+ MSM_PIN_FUNCTION(sdc1_cmd),
+ MSM_PIN_FUNCTION(sdc1_data),
+ MSM_PIN_FUNCTION(wci_txd),
+ MSM_PIN_FUNCTION(wci_rxd),
+ MSM_PIN_FUNCTION(wsa_swrm),
+ MSM_PIN_FUNCTION(wsi_clk3),
+ MSM_PIN_FUNCTION(wsi_data3),
+ MSM_PIN_FUNCTION(wsis_reset),
+ MSM_PIN_FUNCTION(xfem),
+};
+
+static const struct msm_pingroup ipq5018_groups[] = {
+ PINGROUP(0, atest_char, _, qdss_cti_trig_out_a0, wci_txd, wci_rxd, xfem, _, _, _),
+ PINGROUP(1, atest_char, _, qdss_cti_trig_in_a0, wci_txd, wci_rxd, xfem, _, _, _),
+ PINGROUP(2, atest_char, _, qdss_cti_trig_out_a1, wci_txd, wci_rxd, xfem, _, _, _),
+ PINGROUP(3, atest_char, _, qdss_cti_trig_in_a1, wci_txd, wci_rxd, xfem, _, _, _),
+ PINGROUP(4, sdc1_data, qspi_data, blsp1_spi1, btss, dbg_out, qdss_traceclk_a, _, burn0, _),
+ PINGROUP(5, sdc1_data, qspi_data, cxc_clk, blsp1_spi1, blsp1_i2c1, btss, _, qdss_tracectl_a, _),
+ PINGROUP(6, sdc1_data, qspi_data, cxc_data, blsp1_spi1, blsp1_i2c1, btss, _, qdss_tracedata_a, _),
+ PINGROUP(7, sdc1_data, qspi_data, mac0, blsp1_spi1, btss, _, qdss_tracedata_a, _, _),
+ PINGROUP(8, sdc1_cmd, qspi_cs, mac1, btss, _, qdss_tracedata_a, _, _, _),
+ PINGROUP(9, sdc1_clk, qspi_clk, _, qdss_tracedata_a, _, _, _, _, _),
+ PINGROUP(10, blsp0_spi, blsp1_uart0, led0, gcc_plltest, qdss_tracedata_a, _, _, _, _),
+ PINGROUP(11, blsp0_spi, blsp1_uart0, _, gcc_tlmm, qdss_tracedata_a, _, _, _, _),
+ PINGROUP(12, blsp0_spi, blsp0_i2c, blsp1_uart0, _, gcc_plltest, qdss_tracedata_a, _, _, _),
+ PINGROUP(13, blsp0_spi, blsp0_i2c, blsp1_uart0, _, qdss_tracedata_a, _, _, _, _),
+ PINGROUP(14, pcie0_clk, _, _, cri_trng0, qdss_tracedata_a, _, _, _, _),
+ PINGROUP(15, _, _, cri_trng1, qdss_tracedata_a, _, _, _, _, _),
+ PINGROUP(16, pcie0_wake, _, _, cri_trng, qdss_tracedata_a, _, _, _, _),
+ PINGROUP(17, pcie1_clk, btss, _, prng_rosc, qdss_tracedata_a, _, _, _, _),
+ PINGROUP(18, blsp1_spi0, btss, _, qdss_tracedata_a, _, _, _, _, _),
+ PINGROUP(19, pcie1_wake, blsp1_spi0, blsp1_i2c0, btss, _, qdss_tracedata_a, _, _, _),
+ PINGROUP(20, blsp0_uart0, blsp1_spi0, blsp1_i2c0, _, qdss_tracedata_a, _, _, _, _),
+ PINGROUP(21, blsp0_uart0, blsp1_spi0, _, qdss_tracedata_a, _, _, _, _, _),
+ PINGROUP(22, _, pll_test, eud_gpio, _, _, _, _, _, _),
+ PINGROUP(23, audio_rxmclk, audio_pdm0, audio_rxmclk, blsp2_spi1, blsp1_uart2, btss, _, qdss_tracedata_b, _),
+ PINGROUP(24, audio_rxbclk, audio_pdm0, blsp2_spi1, blsp1_uart2, btss, _, qdss_tracedata_b, _, _),
+ PINGROUP(25, audio_rxfsync, audio_pdm1, blsp2_i2c1, blsp2_spi1, blsp1_uart2, btss, _, qdss_tracedata_b, _),
+ PINGROUP(26, audio_rxd, audio_pdm1, blsp2_i2c1, blsp2_spi1, blsp1_uart2, btss, _, qdss_tracedata_b, _),
+ PINGROUP(27, audio_txmclk, wsa_swrm, audio_txmclk, blsp2_spi, btss, _, qdss_tracedata_b, _, _),
+ PINGROUP(28, audio_txbclk, wsa_swrm, blsp0_uart1, btss, qdss_tracedata_b, _, _, _, _),
+ PINGROUP(29, audio_txfsync, _, blsp0_uart1, _, qdss_tracedata_b, _, _, _, _),
+ PINGROUP(30, audio_txd, led2, led0, _, _, _, _, _, _),
+ PINGROUP(31, blsp2_spi0, blsp1_uart1, _, qdss_tracedata_b, eud_gpio, _, _, _, _),
+ PINGROUP(32, blsp2_spi0, blsp1_uart1, _, qdss_tracedata_b, eud_gpio, _, _, _, _),
+ PINGROUP(33, blsp2_i2c0, blsp2_spi0, blsp1_uart1, _, qdss_tracedata_b, eud_gpio, _, _, _),
+ PINGROUP(34, blsp2_i2c0, blsp2_spi0, blsp1_uart1, _, qdss_tracedata_b, eud_gpio, _, _, _),
+ PINGROUP(35, _, qdss_tracedata_b, eud_gpio, _, _, _, _, _, _),
+ PINGROUP(36, mdc, qdss_tracedata_b, _, wsi_clk3, _, _, _, _, _),
+ PINGROUP(37, mdio, atest_char, qdss_tracedata_b, _, wsi_data3, _, _, _, _),
+ PINGROUP(38, qdss_tracedata_b, _, _, _, _, _, _, _, _),
+ PINGROUP(39, qdss_traceclk_b, _, _, _, _, _, _, _, _),
+ PINGROUP(40, reset_out, qdss_tracectl_b, _, _, _, _, _, _, _),
+ PINGROUP(41, _, _, _, _, _, _, _, _, _),
+ PINGROUP(42, pwm0, qdss_cti_trig_out_b0, wci_txd, wci_rxd, xfem, _, _, _, _),
+ PINGROUP(43, pwm1, qdss_cti_trig_in_b0, wci_txd, wci_rxd, xfem, _, _, _, _),
+ PINGROUP(44, pwm2, qdss_cti_trig_out_b1, wci_txd, wci_rxd, xfem, _, _, _, _),
+ PINGROUP(45, pwm3, qdss_cti_trig_in_b1, wci_txd, wci_rxd, xfem, _, _, _, _),
+ PINGROUP(46, led0, _, _, _, _, _, _, _, _),
+};
+
+static const struct msm_pinctrl_soc_data ipq5018_pinctrl = {
+ .pins = ipq5018_pins,
+ .npins = ARRAY_SIZE(ipq5018_pins),
+ .functions = ipq5018_functions,
+ .nfunctions = ARRAY_SIZE(ipq5018_functions),
+ .groups = ipq5018_groups,
+ .ngroups = ARRAY_SIZE(ipq5018_groups),
+ .ngpios = 47,
+};
+
+static int ipq5018_pinctrl_probe(struct platform_device *pdev)
+{
+ return msm_pinctrl_probe(pdev, &ipq5018_pinctrl);
+}
+
+static const struct of_device_id ipq5018_pinctrl_of_match[] = {
+ { .compatible = "qcom,ipq5018-tlmm", },
+ { }
+};
+MODULE_DEVICE_TABLE(of, ipq5018_pinctrl_of_match);
+
+static struct platform_driver ipq5018_pinctrl_driver = {
+ .driver = {
+ .name = "ipq5018-tlmm",
+ .of_match_table = ipq5018_pinctrl_of_match,
+ },
+ .probe = ipq5018_pinctrl_probe,
+ .remove = msm_pinctrl_remove,
+};
+
+static int __init ipq5018_pinctrl_init(void)
+{
+ return platform_driver_register(&ipq5018_pinctrl_driver);
+}
+arch_initcall(ipq5018_pinctrl_init);
+
+static void __exit ipq5018_pinctrl_exit(void)
+{
+ platform_driver_unregister(&ipq5018_pinctrl_driver);
+}
+module_exit(ipq5018_pinctrl_exit);
+
+MODULE_DESCRIPTION("Qualcomm Technologies Inc ipq5018 pinctrl driver");
+MODULE_LICENSE("GPL");
--
2.34.1
Add device tree binding Documentation details for ipq5018
pinctrl driver.
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Co-developed-by: Nitheesh Sekar <[email protected]>
Signed-off-by: Nitheesh Sekar <[email protected]>
Co-developed-by: Varadarajan Narayanan <[email protected]>
Signed-off-by: Varadarajan Narayanan <[email protected]>
Signed-off-by: Sricharan Ramabadhran <[email protected]>
---
[v6] Added reviewed by
.../bindings/pinctrl/qcom,ipq5018-tlmm.yaml | 127 ++++++++++++++++++
1 file changed, 127 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,ipq5018-tlmm.yaml
diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,ipq5018-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,ipq5018-tlmm.yaml
new file mode 100644
index 000000000000..fad0118fd521
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/qcom,ipq5018-tlmm.yaml
@@ -0,0 +1,127 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/qcom,ipq5018-tlmm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm IPQ5018 TLMM pin controller
+
+maintainers:
+ - Bjorn Andersson <[email protected]>
+ - Krzysztof Kozlowski <[email protected]>
+
+description:
+ Top Level Mode Multiplexer pin controller in Qualcomm IPQ5018 SoC.
+
+properties:
+ compatible:
+ const: qcom,ipq5018-tlmm
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ interrupt-controller: true
+ "#interrupt-cells": true
+ gpio-controller: true
+ "#gpio-cells": true
+ gpio-ranges: true
+ wakeup-parent: true
+
+ gpio-reserved-ranges:
+ minItems: 1
+ maxItems: 24
+
+ gpio-line-names:
+ maxItems: 47
+
+patternProperties:
+ "-state$":
+ oneOf:
+ - $ref: "#/$defs/qcom-ipq5018-tlmm-state"
+ - patternProperties:
+ "-pins$":
+ $ref: "#/$defs/qcom-ipq5018-tlmm-state"
+ additionalProperties: false
+
+$defs:
+ qcom-ipq5018-tlmm-state:
+ type: object
+ description:
+ Pinctrl node's client devices use subnodes for desired pin configuration.
+ Client device subnodes use below standard properties.
+ $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
+ unevaluatedProperties: false
+
+ properties:
+ pins:
+ description:
+ List of gpio pins affected by the properties specified in this
+ subnode.
+ items:
+ pattern: "^gpio([0-9]|[1-3][0-9]|4[0-6])$"
+ minItems: 1
+ maxItems: 8
+
+ function:
+ description:
+ Specify the alternative function to be configured for the specified
+ pins.
+
+ enum: [ atest_char, audio_pdm0, audio_pdm1, audio_rxbclk, audio_rxd,
+ audio_rxfsync, audio_rxmclk, audio_txbclk, audio_txd,
+ audio_txfsync, audio_txmclk, blsp0_i2c, blsp0_spi, blsp0_uart0,
+ blsp0_uart1, blsp1_i2c0, blsp1_i2c1, blsp1_spi0, blsp1_spi1,
+ blsp1_uart0, blsp1_uart1, blsp1_uart2, blsp2_i2c0, blsp2_i2c1,
+ blsp2_spi, blsp2_spi0, blsp2_spi1, btss, burn0, burn1, cri_trng,
+ cri_trng0, cri_trng1, cxc_clk, cxc_data, dbg_out, eud_gpio,
+ gcc_plltest, gcc_tlmm, gpio, led0, led2, mac0, mac1, mdc, mdio,
+ pcie0_clk, pcie0_wake, pcie1_clk, pcie1_wake, pll_test,
+ prng_rosc, pwm0, pwm1, pwm2, pwm3, qdss_cti_trig_in_a0,
+ qdss_cti_trig_in_a1, qdss_cti_trig_in_b0, qdss_cti_trig_in_b1,
+ qdss_cti_trig_out_a0, qdss_cti_trig_out_a1,
+ qdss_cti_trig_out_b0, qdss_cti_trig_out_b1, qdss_traceclk_a,
+ qdss_traceclk_b, qdss_tracectl_a, qdss_tracectl_b,
+ qdss_tracedata_a, qdss_tracedata_b, qspi_clk, qspi_cs,
+ qspi_data, reset_out, sdc1_clk, sdc1_cmd, sdc1_data, wci_txd,
+ wci_rxd, wsa_swrm, wsi_clk3, wsi_data3, wsis_reset, xfem ]
+
+ required:
+ - pins
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ tlmm: pinctrl@1000000 {
+ compatible = "qcom,ipq5018-tlmm";
+ reg = <0x01000000 0x300000>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&tlmm 0 0 47>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
+
+ uart-w-state {
+ rx-pins {
+ pins = "gpio33";
+ function = "blsp1_uart1";
+ bias-pull-down;
+ };
+
+ tx-pins {
+ pins = "gpio34";
+ function = "blsp1_uart1";
+ bias-pull-down;
+ };
+ };
+ };
+...
--
2.34.1
Add initial device tree support for the Qualcomm IPQ5018 SoC and
rdp432-c2 board.
Few things like 'reboot' does not work because, couple of more 'SCM'
APIS are needed to clear some TrustZone settings. Those will be
posted separately.
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Co-developed-by: Varadarajan Narayanan <[email protected]>
Signed-off-by: Varadarajan Narayanan <[email protected]>
Co-developed-by: Gokul Sriram Palanisamy <[email protected]>
Signed-off-by: Gokul Sriram Palanisamy <[email protected]>
Signed-off-by: Sricharan Ramabadhran <[email protected]>
---
[v6] Added Reviewed by and fixed commit log as per comments from
[email protected]
arch/arm64/boot/dts/qcom/Makefile | 1 +
.../arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts | 72 +++++
arch/arm64/boot/dts/qcom/ipq5018.dtsi | 250 ++++++++++++++++++
3 files changed, 323 insertions(+)
create mode 100644 arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts
create mode 100644 arch/arm64/boot/dts/qcom/ipq5018.dtsi
diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
index d42c59572ace..57858e7f2095 100644
--- a/arch/arm64/boot/dts/qcom/Makefile
+++ b/arch/arm64/boot/dts/qcom/Makefile
@@ -3,6 +3,7 @@ dtb-$(CONFIG_ARCH_QCOM) += apq8016-sbc.dtb
dtb-$(CONFIG_ARCH_QCOM) += apq8094-sony-xperia-kitakami-karin_windy.dtb
dtb-$(CONFIG_ARCH_QCOM) += apq8096-db820c.dtb
dtb-$(CONFIG_ARCH_QCOM) += apq8096-ifc6640.dtb
+dtb-$(CONFIG_ARCH_QCOM) += ipq5018-rdp432-c2.dtb
dtb-$(CONFIG_ARCH_QCOM) += ipq5332-mi01.2.dtb
dtb-$(CONFIG_ARCH_QCOM) += ipq5332-rdp468.dtb
dtb-$(CONFIG_ARCH_QCOM) += ipq6018-cp01-c1.dtb
diff --git a/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts b/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts
new file mode 100644
index 000000000000..e636a1cb9b77
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts
@@ -0,0 +1,72 @@
+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+/*
+ * IPQ5018 MP03.1-C2 board device tree source
+ *
+ * Copyright (c) 2023 The Linux Foundation. All rights reserved.
+ */
+
+/dts-v1/;
+
+#include "ipq5018.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. IPQ5018/AP-RDP432.1-C2";
+ compatible = "qcom,ipq5018-rdp432-c2", "qcom,ipq5018";
+
+ aliases {
+ serial0 = &blsp1_uart1;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&blsp1_uart1 {
+ pinctrl-0 = <&uart1_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&sdhc_1 {
+ pinctrl-0 = <&sdc_default_state>;
+ pinctrl-names = "default";
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
+ max-frequency = <192000000>;
+ bus-width = <4>;
+ status = "okay";
+};
+
+&sleep_clk {
+ clock-frequency = <32000>;
+};
+
+&tlmm {
+ sdc_default_state: sdc-default-state {
+ clk-pins {
+ pins = "gpio9";
+ function = "sdc1_clk";
+ drive-strength = <8>;
+ bias-disable;
+ };
+
+ cmd-pins {
+ pins = "gpio8";
+ function = "sdc1_cmd";
+ drive-strength = <8>;
+ bias-pull-up;
+ };
+
+ data-pins {
+ pins = "gpio4", "gpio5", "gpio6", "gpio7";
+ function = "sdc1_data";
+ drive-strength = <8>;
+ bias-disable;
+ };
+ };
+};
+
+&xo_board_clk {
+ clock-frequency = <24000000>;
+};
diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
new file mode 100644
index 000000000000..fc31043b59fe
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
@@ -0,0 +1,250 @@
+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+/*
+ * IPQ5018 SoC device tree source
+ *
+ * Copyright (c) 2023 The Linux Foundation. All rights reserved.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/qcom,gcc-ipq5018.h>
+#include <dt-bindings/reset/qcom,gcc-ipq5018.h>
+
+/ {
+ interrupt-parent = <&intc>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ clocks {
+ sleep_clk: sleep-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ };
+
+ xo_board_clk: xo-board-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ };
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ CPU0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x0>;
+ enable-method = "psci";
+ next-level-cache = <&L2_0>;
+ };
+
+ CPU1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x1>;
+ enable-method = "psci";
+ next-level-cache = <&L2_0>;
+ };
+
+ L2_0: l2-cache {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-size = <0x80000>;
+ cache-unified;
+ };
+ };
+
+ firmware {
+ scm {
+ compatible = "qcom,scm-ipq5018", "qcom,scm";
+ };
+ };
+
+ memory@40000000 {
+ device_type = "memory";
+ /* We expect the bootloader to fill in the size */
+ reg = <0x0 0x40000000 0x0 0x0>;
+ };
+
+ pmu {
+ compatible = "arm,cortex-a53-pmu";
+ interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ tz_region: tz@4ac00000 {
+ reg = <0x0 0x4ac00000 0x0 0x400000>;
+ no-map;
+ };
+ };
+
+ soc: soc@0 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0 0xffffffff>;
+
+ tlmm: pinctrl@1000000 {
+ compatible = "qcom,ipq5018-tlmm";
+ reg = <0x01000000 0x300000>;
+ interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&tlmm 0 0 47>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ uart1_pins: uart1-state {
+ pins = "gpio31", "gpio32", "gpio33", "gpio34";
+ function = "blsp1_uart1";
+ drive-strength = <8>;
+ bias-pull-down;
+ };
+ };
+
+ gcc: clock-controller@1800000 {
+ compatible = "qcom,gcc-ipq5018";
+ reg = <0x01800000 0x80000>;
+ clocks = <&xo_board_clk>,
+ <&sleep_clk>,
+ <0>,
+ <0>,
+ <0>,
+ <0>,
+ <0>,
+ <0>,
+ <0>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
+ sdhc_1: mmc@7804000 {
+ compatible = "qcom,ipq5018-sdhci", "qcom,sdhci-msm-v5";
+ reg = <0x7804000 0x1000>;
+ reg-names = "hc";
+
+ interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hc_irq", "pwr_irq";
+
+ clocks = <&gcc GCC_SDCC1_AHB_CLK>,
+ <&gcc GCC_SDCC1_APPS_CLK>,
+ <&xo_board_clk>;
+ clock-names = "iface", "core", "xo";
+ non-removable;
+ status = "disabled";
+ };
+
+ blsp1_uart1: serial@78af000 {
+ compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
+ reg = <0x078af000 0x200>;
+ interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
+ status = "disabled";
+ };
+
+ intc: interrupt-controller@b000000 {
+ compatible = "qcom,msm-qgic2";
+ reg = <0x0b000000 0x1000>, /* GICD */
+ <0x0b002000 0x2000>, /* GICC */
+ <0x0b001000 0x1000>, /* GICH */
+ <0x0b004000 0x2000>; /* GICV */
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x0b00a000 0x1ffa>;
+
+ v2m0: v2m@0 {
+ compatible = "arm,gic-v2m-frame";
+ reg = <0x00000000 0xff8>;
+ msi-controller;
+ };
+
+ v2m1: v2m@1000 {
+ compatible = "arm,gic-v2m-frame";
+ reg = <0x00001000 0xff8>;
+ msi-controller;
+ };
+ };
+
+ timer@b120000 {
+ compatible = "arm,armv7-timer-mem";
+ reg = <0x0b120000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ frame@b120000 {
+ reg = <0x0b121000 0x1000>,
+ <0x0b122000 0x1000>;
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ frame-number = <0>;
+ };
+
+ frame@b123000 {
+ reg = <0xb123000 0x1000>;
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ frame-number = <1>;
+ status = "disabled";
+ };
+
+ frame@b124000 {
+ frame-number = <2>;
+ interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x0b124000 0x1000>;
+ status = "disabled";
+ };
+
+ frame@b125000 {
+ reg = <0x0b125000 0x1000>;
+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+ frame-number = <3>;
+ status = "disabled";
+ };
+
+ frame@b126000 {
+ reg = <0x0b126000 0x1000>;
+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+ frame-number = <4>;
+ status = "disabled";
+ };
+
+ frame@b127000 {
+ reg = <0x0b127000 0x1000>;
+ interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+ frame-number = <5>;
+ status = "disabled";
+ };
+
+ frame@b128000 {
+ reg = <0x0b128000 0x1000>;
+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+ frame-number = <6>;
+ status = "disabled";
+ };
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+ };
+};
--
2.34.1
Document the new ipq5018 SOC/board device tree bindings.
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Signed-off-by: Sricharan Ramabadhran <[email protected]>
---
[v6] Added reviewed by
Documentation/devicetree/bindings/arm/qcom.yaml | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml
index d9dd25695c3d..9abeea553fc3 100644
--- a/Documentation/devicetree/bindings/arm/qcom.yaml
+++ b/Documentation/devicetree/bindings/arm/qcom.yaml
@@ -30,6 +30,7 @@ description: |
apq8084
apq8096
ipq4018
+ ipq5018
ipq5332
ipq6018
ipq8074
@@ -96,6 +97,7 @@ description: |
hk10-c2
idp
liquid
+ rdp432-c2
mtp
qrd
rb2
@@ -330,6 +332,11 @@ properties:
- qcom,ipq4019-dk04.1-c1
- const: qcom,ipq4019
+ - items:
+ - enum:
+ - qcom,ipq5018-rdp432-c2
+ - const: qcom,ipq5018
+
- items:
- enum:
- qcom,ipq5332-ap-mi01.2
--
2.34.1
On 5/16/2023 10:24 PM, Sricharan Ramabadhran wrote:
> Add initial device tree support for the Qualcomm IPQ5018 SoC and
> rdp432-c2 board.
>
> Few things like 'reboot' does not work because, couple of more 'SCM'
> APIS are needed to clear some TrustZone settings. Those will be
> posted separately.
>
> Reviewed-by: Krzysztof Kozlowski <[email protected]>
> Co-developed-by: Varadarajan Narayanan <[email protected]>
> Signed-off-by: Varadarajan Narayanan <[email protected]>
> Co-developed-by: Gokul Sriram Palanisamy <[email protected]>
> Signed-off-by: Gokul Sriram Palanisamy <[email protected]>
> Signed-off-by: Sricharan Ramabadhran <[email protected]>
> ---
> [v6] Added Reviewed by and fixed commit log as per comments from
> [email protected]
>
> arch/arm64/boot/dts/qcom/Makefile | 1 +
> .../arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts | 72 +++++
> arch/arm64/boot/dts/qcom/ipq5018.dtsi | 250 ++++++++++++++++++
> 3 files changed, 323 insertions(+)
> create mode 100644 arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts
> create mode 100644 arch/arm64/boot/dts/qcom/ipq5018.dtsi
>
> diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
> index d42c59572ace..57858e7f2095 100644
> --- a/arch/arm64/boot/dts/qcom/Makefile
> +++ b/arch/arm64/boot/dts/qcom/Makefile
> @@ -3,6 +3,7 @@ dtb-$(CONFIG_ARCH_QCOM) += apq8016-sbc.dtb
> dtb-$(CONFIG_ARCH_QCOM) += apq8094-sony-xperia-kitakami-karin_windy.dtb
> dtb-$(CONFIG_ARCH_QCOM) += apq8096-db820c.dtb
> dtb-$(CONFIG_ARCH_QCOM) += apq8096-ifc6640.dtb
> +dtb-$(CONFIG_ARCH_QCOM) += ipq5018-rdp432-c2.dtb
> dtb-$(CONFIG_ARCH_QCOM) += ipq5332-mi01.2.dtb
> dtb-$(CONFIG_ARCH_QCOM) += ipq5332-rdp468.dtb
> dtb-$(CONFIG_ARCH_QCOM) += ipq6018-cp01-c1.dtb
> diff --git a/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts b/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts
> new file mode 100644
> index 000000000000..e636a1cb9b77
> --- /dev/null
<snip>
> + reserved-memory {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + tz_region: tz@4ac00000 {
> + reg = <0x0 0x4ac00000 0x0 0x400000>;
TZ size is 2MB not 4MB.
<snip>...
Thanks