Refactor conversion operation to support rk3588 saradc and
add separate start, read, powerdown in respective hooks.
Signed-off-by: Simon Xue <[email protected]>
Signed-off-by: Shreeya Patel <[email protected]>
---
drivers/iio/adc/rockchip_saradc.c | 127 +++++++++++++++++++++++++++---
1 file changed, 115 insertions(+), 12 deletions(-)
diff --git a/drivers/iio/adc/rockchip_saradc.c b/drivers/iio/adc/rockchip_saradc.c
index 79448c5ffc2a..ac6fdf8e673b 100644
--- a/drivers/iio/adc/rockchip_saradc.c
+++ b/drivers/iio/adc/rockchip_saradc.c
@@ -38,10 +38,29 @@
#define SARADC_TIMEOUT msecs_to_jiffies(100)
#define SARADC_MAX_CHANNELS 8
+/* v2 registers */
+#define SARADC2_CONV_CON 0x0
+#define SARADC_T_PD_SOC 0x4
+#define SARADC_T_DAS_SOC 0xc
+#define SARADC2_END_INT_EN 0x104
+#define SARADC2_ST_CON 0x108
+#define SARADC2_STATUS 0x10c
+#define SARADC2_END_INT_ST 0x110
+#define SARADC2_DATA_BASE 0x120
+
+#define SARADC2_EN_END_INT BIT(0)
+#define SARADC2_START BIT(4)
+#define SARADC2_SINGLE_MODE BIT(5)
+
+struct rockchip_saradc;
+
struct rockchip_saradc_data {
const struct iio_chan_spec *channels;
int num_channels;
unsigned long clk_rate;
+ void (*start)(struct rockchip_saradc *info, int chn);
+ int (*read)(struct rockchip_saradc *info);
+ void (*power_down)(struct rockchip_saradc *info);
};
struct rockchip_saradc {
@@ -60,27 +79,77 @@ struct rockchip_saradc {
struct notifier_block nb;
};
-static void rockchip_saradc_power_down(struct rockchip_saradc *info)
+static void rockchip_saradc_reset_controller(struct reset_control *reset);
+
+static void rockchip_saradc_start_v1(struct rockchip_saradc *info, int chn)
+{
+ /* 8 clock periods as delay between power up and start cmd */
+ writel_relaxed(8, info->regs + SARADC_DLY_PU_SOC);
+ /* Select the channel to be used and trigger conversion */
+ writel(SARADC_CTRL_POWER_CTRL | (chn & SARADC_CTRL_CHN_MASK) |
+ SARADC_CTRL_IRQ_ENABLE, info->regs + SARADC_CTRL);
+}
+
+static void rockchip_saradc_start_v2(struct rockchip_saradc *info, int chn)
+{
+ int val;
+
+ if (info->reset)
+ rockchip_saradc_reset_controller(info->reset);
+
+ writel_relaxed(0xc, info->regs + SARADC_T_DAS_SOC);
+ writel_relaxed(0x20, info->regs + SARADC_T_PD_SOC);
+ val = SARADC2_EN_END_INT << 16 | SARADC2_EN_END_INT;
+ writel_relaxed(val, info->regs + SARADC2_END_INT_EN);
+ val = SARADC2_START | SARADC2_SINGLE_MODE | chn;
+ writel(val << 16 | val, info->regs + SARADC2_CONV_CON);
+}
+
+static void rockchip_saradc_start(struct rockchip_saradc *info, int chn)
+{
+ info->data->start(info, chn);
+}
+
+static int rockchip_saradc_read_v1(struct rockchip_saradc *info)
+{
+ return readl_relaxed(info->regs + SARADC_DATA);
+}
+
+static int rockchip_saradc_read_v2(struct rockchip_saradc *info)
+{
+ int offset;
+
+ /* Clear irq */
+ writel_relaxed(0x1, info->regs + SARADC2_END_INT_ST);
+
+ offset = SARADC2_DATA_BASE + info->last_chan->channel * 0x4;
+
+ return readl_relaxed(info->regs + offset);
+}
+
+static int rockchip_saradc_read(struct rockchip_saradc *info)
+{
+ return info->data->read(info);
+}
+
+static void rockchip_saradc_power_down_v1(struct rockchip_saradc *info)
{
- /* Clear irq & power down adc */
writel_relaxed(0, info->regs + SARADC_CTRL);
}
+static void rockchip_saradc_power_down(struct rockchip_saradc *info)
+{
+ if (info->data->power_down)
+ info->data->power_down(info);
+}
+
static int rockchip_saradc_conversion(struct rockchip_saradc *info,
struct iio_chan_spec const *chan)
{
reinit_completion(&info->completion);
- /* 8 clock periods as delay between power up and start cmd */
- writel_relaxed(8, info->regs + SARADC_DLY_PU_SOC);
-
info->last_chan = chan;
-
- /* Select the channel to be used and trigger conversion */
- writel(SARADC_CTRL_POWER_CTRL
- | (chan->channel & SARADC_CTRL_CHN_MASK)
- | SARADC_CTRL_IRQ_ENABLE,
- info->regs + SARADC_CTRL);
+ rockchip_saradc_start(info, chan->channel);
if (!wait_for_completion_timeout(&info->completion, SARADC_TIMEOUT))
return -ETIMEDOUT;
@@ -123,7 +192,7 @@ static irqreturn_t rockchip_saradc_isr(int irq, void *dev_id)
struct rockchip_saradc *info = dev_id;
/* Read value */
- info->last_val = readl_relaxed(info->regs + SARADC_DATA);
+ info->last_val = rockchip_saradc_read(info);
info->last_val &= GENMASK(info->last_chan->scan_type.realbits - 1, 0);
rockchip_saradc_power_down(info);
@@ -163,6 +232,9 @@ static const struct rockchip_saradc_data saradc_data = {
.channels = rockchip_saradc_iio_channels,
.num_channels = ARRAY_SIZE(rockchip_saradc_iio_channels),
.clk_rate = 1000000,
+ .start = rockchip_saradc_start_v1,
+ .read = rockchip_saradc_read_v1,
+ .power_down = rockchip_saradc_power_down_v1,
};
static const struct iio_chan_spec rockchip_rk3066_tsadc_iio_channels[] = {
@@ -174,6 +246,9 @@ static const struct rockchip_saradc_data rk3066_tsadc_data = {
.channels = rockchip_rk3066_tsadc_iio_channels,
.num_channels = ARRAY_SIZE(rockchip_rk3066_tsadc_iio_channels),
.clk_rate = 50000,
+ .start = rockchip_saradc_start_v1,
+ .read = rockchip_saradc_read_v1,
+ .power_down = rockchip_saradc_power_down_v1,
};
static const struct iio_chan_spec rockchip_rk3399_saradc_iio_channels[] = {
@@ -189,6 +264,9 @@ static const struct rockchip_saradc_data rk3399_saradc_data = {
.channels = rockchip_rk3399_saradc_iio_channels,
.num_channels = ARRAY_SIZE(rockchip_rk3399_saradc_iio_channels),
.clk_rate = 1000000,
+ .start = rockchip_saradc_start_v1,
+ .read = rockchip_saradc_read_v1,
+ .power_down = rockchip_saradc_power_down_v1,
};
static const struct iio_chan_spec rockchip_rk3568_saradc_iio_channels[] = {
@@ -206,6 +284,28 @@ static const struct rockchip_saradc_data rk3568_saradc_data = {
.channels = rockchip_rk3568_saradc_iio_channels,
.num_channels = ARRAY_SIZE(rockchip_rk3568_saradc_iio_channels),
.clk_rate = 1000000,
+ .start = rockchip_saradc_start_v1,
+ .read = rockchip_saradc_read_v1,
+ .power_down = rockchip_saradc_power_down_v1,
+};
+
+static const struct iio_chan_spec rockchip_rk3588_saradc_iio_channels[] = {
+ SARADC_CHANNEL(0, "adc0", 12),
+ SARADC_CHANNEL(1, "adc1", 12),
+ SARADC_CHANNEL(2, "adc2", 12),
+ SARADC_CHANNEL(3, "adc3", 12),
+ SARADC_CHANNEL(4, "adc4", 12),
+ SARADC_CHANNEL(5, "adc5", 12),
+ SARADC_CHANNEL(6, "adc6", 12),
+ SARADC_CHANNEL(7, "adc7", 12),
+};
+
+static const struct rockchip_saradc_data rk3588_saradc_data = {
+ .channels = rockchip_rk3588_saradc_iio_channels,
+ .num_channels = ARRAY_SIZE(rockchip_rk3588_saradc_iio_channels),
+ .clk_rate = 1000000,
+ .start = rockchip_saradc_start_v2,
+ .read = rockchip_saradc_read_v2,
};
static const struct of_device_id rockchip_saradc_match[] = {
@@ -221,6 +321,9 @@ static const struct of_device_id rockchip_saradc_match[] = {
}, {
.compatible = "rockchip,rk3568-saradc",
.data = &rk3568_saradc_data,
+ }, {
+ .compatible = "rockchip,rk3588-saradc",
+ .data = &rk3588_saradc_data,
},
{},
};
--
2.30.2
Il 17/05/23 01:00, Shreeya Patel ha scritto:
> Refactor conversion operation to support rk3588 saradc and
> add separate start, read, powerdown in respective hooks.
>
> Signed-off-by: Simon Xue <[email protected]>
> Signed-off-by: Shreeya Patel <[email protected]>
> ---
> drivers/iio/adc/rockchip_saradc.c | 127 +++++++++++++++++++++++++++---
> 1 file changed, 115 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/iio/adc/rockchip_saradc.c b/drivers/iio/adc/rockchip_saradc.c
> index 79448c5ffc2a..ac6fdf8e673b 100644
> --- a/drivers/iio/adc/rockchip_saradc.c
> +++ b/drivers/iio/adc/rockchip_saradc.c
> @@ -38,10 +38,29 @@
> #define SARADC_TIMEOUT msecs_to_jiffies(100)
> #define SARADC_MAX_CHANNELS 8
>
> +/* v2 registers */
> +#define SARADC2_CONV_CON 0x0
> +#define SARADC_T_PD_SOC 0x4
> +#define SARADC_T_DAS_SOC 0xc
> +#define SARADC2_END_INT_EN 0x104
> +#define SARADC2_ST_CON 0x108
> +#define SARADC2_STATUS 0x10c
> +#define SARADC2_END_INT_ST 0x110
> +#define SARADC2_DATA_BASE 0x120
> +
> +#define SARADC2_EN_END_INT BIT(0)
> +#define SARADC2_START BIT(4)
> +#define SARADC2_SINGLE_MODE BIT(5)
> +
> +struct rockchip_saradc;
> +
> struct rockchip_saradc_data {
> const struct iio_chan_spec *channels;
> int num_channels;
> unsigned long clk_rate;
> + void (*start)(struct rockchip_saradc *info, int chn);
> + int (*read)(struct rockchip_saradc *info);
> + void (*power_down)(struct rockchip_saradc *info);
> };
>
> struct rockchip_saradc {
> @@ -60,27 +79,77 @@ struct rockchip_saradc {
> struct notifier_block nb;
> };
>
> -static void rockchip_saradc_power_down(struct rockchip_saradc *info)
> +static void rockchip_saradc_reset_controller(struct reset_control *reset);
> +
> +static void rockchip_saradc_start_v1(struct rockchip_saradc *info, int chn)
> +{
> + /* 8 clock periods as delay between power up and start cmd */
> + writel_relaxed(8, info->regs + SARADC_DLY_PU_SOC);
> + /* Select the channel to be used and trigger conversion */
> + writel(SARADC_CTRL_POWER_CTRL | (chn & SARADC_CTRL_CHN_MASK) |
> + SARADC_CTRL_IRQ_ENABLE, info->regs + SARADC_CTRL);
> +}
> +
> +static void rockchip_saradc_start_v2(struct rockchip_saradc *info, int chn)
> +{
> + int val;
> +
> + if (info->reset)
> + rockchip_saradc_reset_controller(info->reset);
> +
> + writel_relaxed(0xc, info->regs + SARADC_T_DAS_SOC);
> + writel_relaxed(0x20, info->regs + SARADC_T_PD_SOC);
> + val = SARADC2_EN_END_INT << 16 | SARADC2_EN_END_INT;
What about using bitfield macros?
/* "LO" and "HI" may get a better name, if there's any possible one! */
#define SARADC2_EN_END_INT_LO BIT(0)
#define SARADC2_EN_END_INT_HI BIT(16)
val = FIELD_PREP(SARADC_EN_END_INT_LO, 1);
val |= FIELD_PREP(SARADC_EN_END_INT_HI, 1);
writel ....
Otherwise, if it's about two really "specular" instances, you can probably
keep the current definition as SARADC2_EN_END_INT and do
val = FIELD_PREP(SARADC_EN_END_INT, 1);
val |= val << 16;
writel ...
/* note: high, low bits are unknown to me, I assumed it's 16 bits :-) */
#define SARADC2_CONV_CHANNELS GENMASK(15, 0)
val = FIELD_PREP(SARADC2_START, 1);
val |= FIELD_PREP(SARADC2_SINGLE_MODE, 1);
val |= FIELD_PREP(SARADC2_CONV_CHANNELS, chn);
val |= val << 16;
writel ...
> + writel_relaxed(val, info->regs + SARADC2_END_INT_EN);
> + val = SARADC2_START | SARADC2_SINGLE_MODE | chn;
> + writel(val << 16 | val, info->regs + SARADC2_CONV_CON);
> +}
> +
Cheers,
Angelo
On Wed, 17 May 2023 04:30:45 +0530
Shreeya Patel <[email protected]> wrote:
> Refactor conversion operation to support rk3588 saradc and
> add separate start, read, powerdown in respective hooks.
>
> Signed-off-by: Simon Xue <[email protected]>
> Signed-off-by: Shreeya Patel <[email protected]>
Hi Shreeya,
This particular chain of tags has unclear authorship.
If Simon wrote the driver, then the author (from address) of the
patch should be Simon's. If it is a codeveloped situation look
at how to use the co-developed-by tag
Generally the nicest way to add new callbacks is to do them in their
own patch. Then introduce new devices with different callbacks in a follow
on patch. That means the first one can be reviewed to ensure there
is no functional change separate from the new code in the following patch.
> +static const struct rockchip_saradc_data rk3588_saradc_data = {
> + .channels = rockchip_rk3588_saradc_iio_channels,
> + .num_channels = ARRAY_SIZE(rockchip_rk3588_saradc_iio_channels),
> + .clk_rate = 1000000,
> + .start = rockchip_saradc_start_v2,
As mentioned above, I'd like to see the changes for old devices done in patch
1 and the support for new device in a new patch.
> + .read = rockchip_saradc_read_v2,
> };