IPQ9574 SoC uses the PMIC MP5496 and SMPA1 regulator for APSS voltage scaling.
This patch series adds support for the same and also enables the RPM
communication over the RPMSG framework.
DTS patch depends on the below series which applies cleanly on top of [1]
https://lore.kernel.org/linux-arm-msm/[email protected]/
[1] https://lore.kernel.org/linux-arm-msm/[email protected]/
[V5]:
- Dropped the below patches as they are already part of linux-next/master
[1/5] regulator: qcom_smd: Add s1 sub-node to mp5496 regulator
[2/5] regulator: qcom_smd: Add MP5496 S1 regulator
- Rebased on the below series
https://lore.kernel.org/linux-arm-msm/[email protected]/
[V4]:
https://lore.kernel.org/linux-arm-msm/[email protected]/
- Detailed change logs are added to the respective patches
[V3]:
https://lore.kernel.org/linux-arm-msm/[email protected]/
- Dropped PATCH [1/6] dt-bindings: soc: qcom: smd-rpm: Add IPQ9574 compatible
as it is available in linux-next/master
- Dropped PATCH [4/6] regulator: qcom_smd: Add support to define the bootup voltage
and updated the nominal voltage in the Board DT as discussed
- Splitted the board DT changes to a separate patch as suggested
- Detailed change logs are added to the respective patches
[V2]:
https://lore.kernel.org/linux-arm-msm/[email protected]/
- Reordered the patches to have the bindings and driver changes
in place before the device tree support
- Dropped the 'soc: qcom: smd-rpm: Add IPQ9574 compatible' since
it is already part of the linux-next/master
- Detailed change log is added to the respective patches
[V1]:
https://lore.kernel.org/linux-arm-msm/[email protected]/
Devi Priya (3):
arm64: dts: qcom: ipq9574: Add RPM related nodes
arm64: dts: qcom: ipq9574: Add SMPA1 regulator node
arm64: dts: qcom: ipq9574: Add cpufreq support
arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts | 19 +++++
arch/arm64/boot/dts/qcom/ipq9574.dtsi | 77 ++++++++++++++++++++-
2 files changed, 95 insertions(+), 1 deletion(-)
--
2.17.1
Add RPM Glink & RPM message RAM nodes to support frequency scaling
on IPQ9574.
Reviewed-by: Konrad Dybcio <[email protected]>
Co-developed-by: Praveenkumar I <[email protected]>
Signed-off-by: Praveenkumar I <[email protected]>
Signed-off-by: Devi Priya <[email protected]>
---
Changes in V5:
- No change
arch/arm64/boot/dts/qcom/ipq9574.dtsi | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
index adc3fefcb469..31244b1d8c25 100644
--- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
@@ -110,12 +110,29 @@
};
};
+ rpm-glink {
+ compatible = "qcom,glink-rpm";
+ interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
+ qcom,rpm-msg-ram = <&rpm_msg_ram>;
+ mboxes = <&apcs_glb 0>;
+
+ rpm_requests: rpm-requests {
+ compatible = "qcom,rpm-ipq9574";
+ qcom,glink-channels = "rpm_requests";
+ };
+ };
+
soc: soc@0 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0 0xffffffff>;
+ rpm_msg_ram: sram@60000 {
+ compatible = "qcom,rpm-msg-ram";
+ reg = <0x00060000 0x6000>;
+ };
+
rng: rng@e3000 {
compatible = "qcom,prng-ee";
reg = <0x000e3000 0x1000>;
--
2.17.1
Add cpu freq nodes in the device tree to bump cpu frequency above 800MHz.
Reviewed-by: Konrad Dybcio <[email protected]>
Co-developed-by: Praveenkumar I <[email protected]>
Signed-off-by: Praveenkumar I <[email protected]>
Signed-off-by: Devi Priya <[email protected]>
---
Changes in V5:
- Sorted the includes alphabetically
arch/arm64/boot/dts/qcom/ipq9574.dtsi | 60 ++++++++++++++++++++++++++-
1 file changed, 59 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
index 31244b1d8c25..16edffe53c8b 100644
--- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
@@ -6,8 +6,9 @@
* Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
*/
-#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/qcom,apss-ipq.h>
#include <dt-bindings/clock/qcom,ipq9574-gcc.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/reset/qcom,ipq9574-gcc.h>
/ {
@@ -37,6 +38,10 @@
reg = <0x0>;
enable-method = "psci";
next-level-cache = <&L2_0>;
+ clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
+ clock-names = "cpu";
+ operating-points-v2 = <&cpu_opp_table>;
+ cpu-supply = <&ipq9574_s1>;
};
CPU1: cpu@1 {
@@ -45,6 +50,10 @@
reg = <0x1>;
enable-method = "psci";
next-level-cache = <&L2_0>;
+ clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
+ clock-names = "cpu";
+ operating-points-v2 = <&cpu_opp_table>;
+ cpu-supply = <&ipq9574_s1>;
};
CPU2: cpu@2 {
@@ -53,6 +62,10 @@
reg = <0x2>;
enable-method = "psci";
next-level-cache = <&L2_0>;
+ clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
+ clock-names = "cpu";
+ operating-points-v2 = <&cpu_opp_table>;
+ cpu-supply = <&ipq9574_s1>;
};
CPU3: cpu@3 {
@@ -61,6 +74,10 @@
reg = <0x3>;
enable-method = "psci";
next-level-cache = <&L2_0>;
+ clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
+ clock-names = "cpu";
+ operating-points-v2 = <&cpu_opp_table>;
+ cpu-supply = <&ipq9574_s1>;
};
L2_0: l2-cache {
@@ -82,6 +99,47 @@
reg = <0x0 0x40000000 0x0 0x0>;
};
+ cpu_opp_table: opp-table-cpu {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-936000000 {
+ opp-hz = /bits/ 64 <936000000>;
+ opp-microvolt = <725000>;
+ clock-latency-ns = <200000>;
+ };
+
+ opp-1104000000 {
+ opp-hz = /bits/ 64 <1104000000>;
+ opp-microvolt = <787500>;
+ clock-latency-ns = <200000>;
+ };
+
+ opp-1416000000 {
+ opp-hz = /bits/ 64 <1416000000>;
+ opp-microvolt = <862500>;
+ clock-latency-ns = <200000>;
+ };
+
+ opp-1488000000 {
+ opp-hz = /bits/ 64 <1488000000>;
+ opp-microvolt = <925000>;
+ clock-latency-ns = <200000>;
+ };
+
+ opp-1800000000 {
+ opp-hz = /bits/ 64 <1800000000>;
+ opp-microvolt = <987500>;
+ clock-latency-ns = <200000>;
+ };
+
+ opp-2208000000 {
+ opp-hz = /bits/ 64 <2208000000>;
+ opp-microvolt = <1062500>;
+ clock-latency-ns = <200000>;
+ };
+ };
+
pmu {
compatible = "arm,cortex-a73-pmu";
interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
--
2.17.1
Add support for SMPA1 regulator node in IPQ9574.
Reviewed-by: Konrad Dybcio <[email protected]>
Co-developed-by: Praveenkumar I <[email protected]>
Signed-off-by: Praveenkumar I <[email protected]>
Signed-off-by: Devi Priya <[email protected]>
---
Changes in V5:
- Picked up the R-b tag
arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts b/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts
index 7be578017bf7..1a35fbc42f8c 100644
--- a/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts
+++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts
@@ -43,6 +43,25 @@
};
};
+&rpm_requests {
+ regulators {
+ compatible = "qcom,rpm-mp5496-regulators";
+
+ ipq9574_s1: s1 {
+ /*
+ * During kernel bootup, the SoC runs at 800MHz with 875mV set by the bootloaders.
+ * During regulator registration, kernel not knowing the initial voltage,
+ * considers it as zero and brings up the regulators with minimum supported voltage.
+ * Update the regulator-min-microvolt with SVS voltage of 725mV so that
+ * the regulators are brought up with 725mV which is sufficient for all the
+ * corner parts to operate at 800MHz
+ */
+ regulator-min-microvolt = <725000>;
+ regulator-max-microvolt = <1075000>;
+ };
+ };
+};
+
&sdhc_1 {
pinctrl-0 = <&sdc_default_state>;
pinctrl-names = "default";
--
2.17.1
On Wed, 17 May 2023 22:55:24 +0530, Devi Priya wrote:
> IPQ9574 SoC uses the PMIC MP5496 and SMPA1 regulator for APSS voltage scaling.
> This patch series adds support for the same and also enables the RPM
> communication over the RPMSG framework.
>
> DTS patch depends on the below series which applies cleanly on top of [1]
> https://lore.kernel.org/linux-arm-msm/[email protected]/
>
> [...]
Applied, thanks!
[1/3] arm64: dts: qcom: ipq9574: Add RPM related nodes
commit: 8cc864a4375dd62023a2880050bf618a225cb907
[2/3] arm64: dts: qcom: ipq9574: Add SMPA1 regulator node
commit: 56ba2b3aeb4b76549a7759e79bd44330cd9b885a
[3/3] arm64: dts: qcom: ipq9574: Add cpufreq support
commit: 8f0ae6bc0098f63a008820f80c08b01ea2167da3
Best regards,
--
Bjorn Andersson <[email protected]>