2023-05-18 10:48:56

by Will Deacon

Subject: [PATCH v2] bpf: Fix mask generation for 32-bit narrow loads of 64-bit fields

A narrow load from a 64-bit context field results in a 64-bit load
followed potentially by a 64-bit right-shift and then a bitwise AND
operation to extract the relevant data.

In the case of a 32-bit access, an immediate mask of 0xffffffff is used
to construct a 64-bit BPP_AND operation which then sign-extends the mask
value and effectively acts as a glorified no-op. For example:

0: 61 10 00 00 00 00 00 00 r0 = *(u32 *)(r1 + 0)

results in the following code generation for a 64-bit field:

ldr x7, [x7] // 64-bit load
mov x10, #0xffffffffffffffff
and x7, x7, x10

Fix the mask generation so that narrow loads always perform a 32-bit AND
operation:

ldr x7, [x7] // 64-bit load
mov w10, #0xffffffff
and w7, w7, w10

Cc: Alexei Starovoitov <[email protected]>
Cc: Daniel Borkmann <[email protected]>
Cc: John Fastabend <[email protected]>
Cc: Krzesimir Nowak <[email protected]>
Cc: Andrey Ignatov <[email protected]>
Acked-by: Yonghong Song <[email protected]>
Fixes: 31fd85816dbe ("bpf: permits narrower load from bpf program context fields")
Signed-off-by: Will Deacon <[email protected]>
---

v2: Improve commit message and add Acked-by.

kernel/bpf/verifier.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/kernel/bpf/verifier.c b/kernel/bpf/verifier.c
index fbcf5a4e2fcd..5871aa78d01a 100644
--- a/kernel/bpf/verifier.c
+++ b/kernel/bpf/verifier.c
@@ -17033,7 +17033,7 @@ static int convert_ctx_accesses(struct bpf_verifier_env *env)
insn_buf[cnt++] = BPF_ALU64_IMM(BPF_RSH,
insn->dst_reg,
shift);
- insn_buf[cnt++] = BPF_ALU64_IMM(BPF_AND, insn->dst_reg,
+ insn_buf[cnt++] = BPF_ALU32_IMM(BPF_AND, insn->dst_reg,
(1ULL << size * 8) - 1);
}
}
--
2.40.1.698.g37aff9b760-goog

2023-05-19 18:29:15

by Alexei Starovoitov

Subject: Re: [PATCH v2] bpf: Fix mask generation for 32-bit narrow loads of 64-bit fields

On Thu, May 18, 2023 at 3:25 AM Will Deacon <[email protected]> wrote:
>
> A narrow load from a 64-bit context field results in a 64-bit load
> followed potentially by a 64-bit right-shift and then a bitwise AND
> operation to extract the relevant data.
>
> In the case of a 32-bit access, an immediate mask of 0xffffffff is used
> to construct a 64-bit BPP_AND operation which then sign-extends the mask
> value and effectively acts as a glorified no-op. For example:
>
> 0: 61 10 00 00 00 00 00 00 r0 = *(u32 *)(r1 + 0)
>
> results in the following code generation for a 64-bit field:
>
> ldr x7, [x7] // 64-bit load
> mov x10, #0xffffffffffffffff
> and x7, x7, x10
>
> Fix the mask generation so that narrow loads always perform a 32-bit AND
> operation:
>
> ldr x7, [x7] // 64-bit load
> mov w10, #0xffffffff
> and w7, w7, w10
>
> Cc: Alexei Starovoitov <[email protected]>
> Cc: Daniel Borkmann <[email protected]>
> Cc: John Fastabend <[email protected]>
> Cc: Krzesimir Nowak <[email protected]>
> Cc: Andrey Ignatov <[email protected]>
> Acked-by: Yonghong Song <[email protected]>
> Fixes: 31fd85816dbe ("bpf: permits narrower load from bpf program context fields")
> Signed-off-by: Will Deacon <[email protected]>

Thanks for the fix! Applied to bpf tree.