From: POOVENDHAN SELVARAJ <[email protected]>
Add the initial device tree support for the Reference Design
Platform(RDP) 454 based on IPQ9574 family of SoCs. This patch series adds
support for Console UART, SPI NOR and SMPA1 regulator node.
The series depends on the below patch sets which adds support for
SPI NOR and SMPA1 regulator nodes.
https://lore.kernel.org/linux-arm-msm/[email protected]/
https://lore.kernel.org/linux-arm-msm/[email protected]/
Poovendhan Selvaraj (2):
dt-bindings: arm: qcom: document AL02-C9 board based on IPQ9574 family
arm64: dts: qcom: ipq9574: add support for RDP454 variant
.../devicetree/bindings/arm/qcom.yaml | 2 +
arch/arm64/boot/dts/qcom/Makefile | 1 +
arch/arm64/boot/dts/qcom/ipq9574-rdp454.dts | 92 +++++++++++++++++++
3 files changed, 95 insertions(+)
create mode 100644 arch/arm64/boot/dts/qcom/ipq9574-rdp454.dts
base-commit: 4272e06e19f388ccfe1f04f19060ea84d2a19a8b
--
2.17.1
From: POOVENDHAN SELVARAJ <[email protected]>
Add the initial device tree support for the Reference Design Platform (RDP)
454 based on IPQ9574 family of SoCs. This patch adds support for Console
UART, SPI NOR and SMPA1 regulator node.
Signed-off-by: Poovendhan Selvaraj <[email protected]>
---
arch/arm64/boot/dts/qcom/Makefile | 1 +
arch/arm64/boot/dts/qcom/ipq9574-rdp454.dts | 92 +++++++++++++++++++++
2 files changed, 93 insertions(+)
create mode 100644 arch/arm64/boot/dts/qcom/ipq9574-rdp454.dts
diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
index 7b5466395f46..834e790bec90 100644
--- a/arch/arm64/boot/dts/qcom/Makefile
+++ b/arch/arm64/boot/dts/qcom/Makefile
@@ -12,6 +12,7 @@ dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk10-c2.dtb
dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp418.dtb
dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp433.dtb
dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp449.dtb
+dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp454.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8916-acer-a1-724.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8916-alcatel-idol347.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8916-asus-z00l.dtb
diff --git a/arch/arm64/boot/dts/qcom/ipq9574-rdp454.dts b/arch/arm64/boot/dts/qcom/ipq9574-rdp454.dts
new file mode 100644
index 000000000000..b3e853a9cc94
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp454.dts
@@ -0,0 +1,92 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * IPQ9574 RDP454 board device tree source
+ *
+ * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+
+#include "ipq9574.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. IPQ9574/AP-AL02-C9";
+ compatible = "qcom,ipq9574-ap-al02-c9", "qcom,ipq9574";
+
+ aliases {
+ serial0 = &blsp1_uart2;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+/* In AL02-C9, the max supported CPU Freq is 1.5 GHz. Disabling frequencies beyond 1.5GHz*/
+&cpu_opp_table {
+ opp-1800000000 {
+ opp-supported-hw = <0>;
+ };
+
+ opp-2208000000 {
+ opp-supported-hw = <0>;
+ };
+};
+
+/* Disable IPQ9574 integrated radio's reserved memory */
+&blsp1_spi0 {
+ pinctrl-0 = <&spi_0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ flash@0 {
+ compatible = "micron,n25q128a11", "jedec,spi-nor";
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ spi-max-frequency = <50000000>;
+ };
+};
+
+&blsp1_uart2 {
+ pinctrl-0 = <&uart2_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&rpm_requests {
+ regulators {
+ compatible = "qcom,rpm-mp5496-regulators";
+
+ ipq9574_s1: s1 {
+ /*
+ * During kernel bootup, the SoC runs at 800MHz with 875mV set by the bootloaders.
+ * During regulator registration, kernel not knowing the initial voltage,
+ * considers it as zero and brings up the regulators with minimum supported voltage.
+ * Update the regulator-min-microvolt with SVS voltage of 725mV so that
+ * the regulators are brought up with 725mV which is sufficient for all the
+ * corner parts to operate at 800MHz
+ */
+ regulator-min-microvolt = <725000>;
+ regulator-max-microvolt = <1075000>;
+ };
+ };
+};
+
+&sleep_clk {
+ clock-frequency = <32000>;
+};
+
+&tlmm {
+ spi_0_pins: spi-0-state {
+ pins = "gpio11", "gpio12", "gpio13", "gpio14";
+ function = "blsp0_spi";
+ drive-strength = <8>;
+ bias-disable;
+ };
+};
+
+&xo_board_clk {
+ clock-frequency = <24000000>;
+};
--
2.17.1
From: POOVENDHAN SELVARAJ <[email protected]>
Document AL02-C9 (Reference Design Platform 454) board based on IPQ9574
family of SoCs.
Signed-off-by: Poovendhan Selvaraj <[email protected]>
---
Documentation/devicetree/bindings/arm/qcom.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml
index febf057012d4..fe7ed853e598 100644
--- a/Documentation/devicetree/bindings/arm/qcom.yaml
+++ b/Documentation/devicetree/bindings/arm/qcom.yaml
@@ -88,6 +88,7 @@ description: |
ap-al02-c2
ap-al02-c6
ap-al02-c7
+ ap-al02-c9
ap-mi01.2
ap-mi01.6
cdp
@@ -356,6 +357,7 @@ properties:
- qcom,ipq9574-ap-al02-c2
- qcom,ipq9574-ap-al02-c6
- qcom,ipq9574-ap-al02-c7
+ - qcom,ipq9574-ap-al02-c9
- const: qcom,ipq9574
- description: Sierra Wireless MangOH Green with WP8548 Module
--
2.17.1
On Fri, May 19, 2023 at 04:01:27PM +0530, Poovendhan Selvaraj wrote:
> From: POOVENDHAN SELVARAJ <[email protected]>
> Signed-off-by: Poovendhan Selvaraj <[email protected]>
Acked-by: Conor Dooley <[email protected]>
Thanks,
Conor.
On 19.05.2023 12:31, Poovendhan Selvaraj wrote:
> From: POOVENDHAN SELVARAJ <[email protected]>
>
> Add the initial device tree support for the Reference Design Platform (RDP)
> 454 based on IPQ9574 family of SoCs. This patch adds support for Console
> UART, SPI NOR and SMPA1 regulator node.
>
> Signed-off-by: Poovendhan Selvaraj <[email protected]>
> ---
> arch/arm64/boot/dts/qcom/Makefile | 1 +
> arch/arm64/boot/dts/qcom/ipq9574-rdp454.dts | 92 +++++++++++++++++++++
> 2 files changed, 93 insertions(+)
> create mode 100644 arch/arm64/boot/dts/qcom/ipq9574-rdp454.dts
>
> diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
> index 7b5466395f46..834e790bec90 100644
> --- a/arch/arm64/boot/dts/qcom/Makefile
> +++ b/arch/arm64/boot/dts/qcom/Makefile
> @@ -12,6 +12,7 @@ dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk10-c2.dtb
> dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp418.dtb
> dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp433.dtb
> dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp449.dtb
> +dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp454.dtb
> dtb-$(CONFIG_ARCH_QCOM) += msm8916-acer-a1-724.dtb
> dtb-$(CONFIG_ARCH_QCOM) += msm8916-alcatel-idol347.dtb
> dtb-$(CONFIG_ARCH_QCOM) += msm8916-asus-z00l.dtb
> diff --git a/arch/arm64/boot/dts/qcom/ipq9574-rdp454.dts b/arch/arm64/boot/dts/qcom/ipq9574-rdp454.dts
> new file mode 100644
> index 000000000000..b3e853a9cc94
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp454.dts
> @@ -0,0 +1,92 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
> +/*
> + * IPQ9574 RDP454 board device tree source
> + *
> + * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.
> + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
> + */
> +
> +/dts-v1/;
> +
> +#include "ipq9574.dtsi"
> +
> +/ {
> + model = "Qualcomm Technologies, Inc. IPQ9574/AP-AL02-C9";
> + compatible = "qcom,ipq9574-ap-al02-c9", "qcom,ipq9574";
> +
> + aliases {
> + serial0 = &blsp1_uart2;
> + };
> +
> + chosen {
> + stdout-path = "serial0:115200n8";
> + };
> +};
> +
> +/* In AL02-C9, the max supported CPU Freq is 1.5 GHz. Disabling frequencies beyond 1.5GHz*/
In -> On
GHz*/ -> GHz */
Disabling -> Disable
Can this not be determined based on fuse values?
> +&cpu_opp_table {
> + opp-1800000000 {
> + opp-supported-hw = <0>;
> + };
> +
> + opp-2208000000 {
> + opp-supported-hw = <0>;
> + };
> +};
> +
> +/* Disable IPQ9574 integrated radio's reserved memory */
?
Konrad
> +&blsp1_spi0 {
> + pinctrl-0 = <&spi_0_pins>;
> + pinctrl-names = "default";
> + status = "okay";
> +
> + flash@0 {
> + compatible = "micron,n25q128a11", "jedec,spi-nor";
> + reg = <0>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + spi-max-frequency = <50000000>;
> + };
> +};
> +
> +&blsp1_uart2 {
> + pinctrl-0 = <&uart2_pins>;
> + pinctrl-names = "default";
> + status = "okay";
> +};
> +
> +&rpm_requests {
> + regulators {
> + compatible = "qcom,rpm-mp5496-regulators";
> +
> + ipq9574_s1: s1 {
> + /*
> + * During kernel bootup, the SoC runs at 800MHz with 875mV set by the bootloaders.
> + * During regulator registration, kernel not knowing the initial voltage,
> + * considers it as zero and brings up the regulators with minimum supported voltage.
> + * Update the regulator-min-microvolt with SVS voltage of 725mV so that
> + * the regulators are brought up with 725mV which is sufficient for all the
> + * corner parts to operate at 800MHz
> + */
> + regulator-min-microvolt = <725000>;
> + regulator-max-microvolt = <1075000>;
> + };
> + };
> +};
> +
> +&sleep_clk {
> + clock-frequency = <32000>;
> +};
> +
> +&tlmm {
> + spi_0_pins: spi-0-state {
> + pins = "gpio11", "gpio12", "gpio13", "gpio14";
> + function = "blsp0_spi";
> + drive-strength = <8>;
> + bias-disable;
> + };
> +};
> +
> +&xo_board_clk {
> + clock-frequency = <24000000>;
> +};
On 5/19/2023 11:01 PM, Konrad Dybcio wrote:
>
> On 19.05.2023 12:31, Poovendhan Selvaraj wrote:
>> From: POOVENDHAN SELVARAJ <[email protected]>
>>
>> Add the initial device tree support for the Reference Design Platform (RDP)
>> 454 based on IPQ9574 family of SoCs. This patch adds support for Console
>> UART, SPI NOR and SMPA1 regulator node.
>>
>> Signed-off-by: Poovendhan Selvaraj <[email protected]>
>> ---
>> arch/arm64/boot/dts/qcom/Makefile | 1 +
>> arch/arm64/boot/dts/qcom/ipq9574-rdp454.dts | 92 +++++++++++++++++++++
>> 2 files changed, 93 insertions(+)
>> create mode 100644 arch/arm64/boot/dts/qcom/ipq9574-rdp454.dts
>>
>> diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
>> index 7b5466395f46..834e790bec90 100644
>> --- a/arch/arm64/boot/dts/qcom/Makefile
>> +++ b/arch/arm64/boot/dts/qcom/Makefile
>> @@ -12,6 +12,7 @@ dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk10-c2.dtb
>> dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp418.dtb
>> dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp433.dtb
>> dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp449.dtb
>> +dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp454.dtb
>> dtb-$(CONFIG_ARCH_QCOM) += msm8916-acer-a1-724.dtb
>> dtb-$(CONFIG_ARCH_QCOM) += msm8916-alcatel-idol347.dtb
>> dtb-$(CONFIG_ARCH_QCOM) += msm8916-asus-z00l.dtb
>> diff --git a/arch/arm64/boot/dts/qcom/ipq9574-rdp454.dts b/arch/arm64/boot/dts/qcom/ipq9574-rdp454.dts
>> new file mode 100644
>> index 000000000000..b3e853a9cc94
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp454.dts
>> @@ -0,0 +1,92 @@
>> +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
>> +/*
>> + * IPQ9574 RDP454 board device tree source
>> + *
>> + * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.
>> + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
>> + */
>> +
>> +/dts-v1/;
>> +
>> +#include "ipq9574.dtsi"
>> +
>> +/ {
>> + model = "Qualcomm Technologies, Inc. IPQ9574/AP-AL02-C9";
>> + compatible = "qcom,ipq9574-ap-al02-c9", "qcom,ipq9574";
>> +
>> + aliases {
>> + serial0 = &blsp1_uart2;
>> + };
>> +
>> + chosen {
>> + stdout-path = "serial0:115200n8";
>> + };
>> +};
>> +
>> +/* In AL02-C9, the max supported CPU Freq is 1.5 GHz. Disabling frequencies beyond 1.5GHz*/
> In -> On
>
> GHz*/ -> GHz */
>
> Disabling -> Disable
Okay. Will address them in next spin
>
> Can this not be determined based on fuse values?
Yes...That should be possible.Will then drop the below cpu_opp_table
entries and post a separate series for the same.
>
>> +&cpu_opp_table {
>> + opp-1800000000 {
>> + opp-supported-hw = <0>;
>> + };
>> +
>> + opp-2208000000 {
>> + opp-supported-hw = <0>;
>> + };
>> +};
>> +
>> +/* Disable IPQ9574 integrated radio's reserved memory */
> ?
>
> Konrad
sorry, will drop it as it got added by mistake.
Regards,
Poovendhan S
>> +&blsp1_spi0 {
>> + pinctrl-0 = <&spi_0_pins>;
>> + pinctrl-names = "default";
>> + status = "okay";
>> +
>> + flash@0 {
>> + compatible = "micron,n25q128a11", "jedec,spi-nor";
>> + reg = <0>;
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + spi-max-frequency = <50000000>;
>> + };
>> +};
>> +
>> +&blsp1_uart2 {
>> + pinctrl-0 = <&uart2_pins>;
>> + pinctrl-names = "default";
>> + status = "okay";
>> +};
>> +
>> +&rpm_requests {
>> + regulators {
>> + compatible = "qcom,rpm-mp5496-regulators";
>> +
>> + ipq9574_s1: s1 {
>> + /*
>> + * During kernel bootup, the SoC runs at 800MHz with 875mV set by the bootloaders.
>> + * During regulator registration, kernel not knowing the initial voltage,
>> + * considers it as zero and brings up the regulators with minimum supported voltage.
>> + * Update the regulator-min-microvolt with SVS voltage of 725mV so that
>> + * the regulators are brought up with 725mV which is sufficient for all the
>> + * corner parts to operate at 800MHz
>> + */
>> + regulator-min-microvolt = <725000>;
>> + regulator-max-microvolt = <1075000>;
>> + };
>> + };
>> +};
>> +
>> +&sleep_clk {
>> + clock-frequency = <32000>;
>> +};
>> +
>> +&tlmm {
>> + spi_0_pins: spi-0-state {
>> + pins = "gpio11", "gpio12", "gpio13", "gpio14";
>> + function = "blsp0_spi";
>> + drive-strength = <8>;
>> + bias-disable;
>> + };
>> +};
>> +
>> +&xo_board_clk {
>> + clock-frequency = <24000000>;
>> +};
On Fri, 19 May 2023 16:01:26 +0530, Poovendhan Selvaraj wrote:
> From: POOVENDHAN SELVARAJ <[email protected]>
>
> Add the initial device tree support for the Reference Design
> Platform(RDP) 454 based on IPQ9574 family of SoCs. This patch series adds
> support for Console UART, SPI NOR and SMPA1 regulator node.
>
> The series depends on the below patch sets which adds support for
> SPI NOR and SMPA1 regulator nodes.
> https://lore.kernel.org/linux-arm-msm/[email protected]/
> https://lore.kernel.org/linux-arm-msm/[email protected]/
>
> [...]
Applied, thanks!
[1/2] dt-bindings: arm: qcom: document AL02-C9 board based on IPQ9574 family
commit: add687cbfc3482ca74949b91b251e76792d25652
[2/2] arm64: dts: qcom: ipq9574: add support for RDP454 variant
commit: 2435d79033f5e7400195ed3b31585c0c053de553
Best regards,
--
Bjorn Andersson <[email protected]>