Hi,
The SoCs making use of Qualcomm PCIe controllers do not support the PCIe hotplug
functionality. But the hotplug capability bit is set by default in the hardware.
This causes the kernel PCI core to register hotplug service for the controller
and send hotplug commands to it. But those commands will timeout generating
messages as below during boot and suspend/resume.
[ 5.782159] pcieport 0001:00:00.0: pciehp: Timeout on hotplug command 0x03c0 (issued 2020 msec ago)
[ 5.810161] pcieport 0001:00:00.0: pciehp: Timeout on hotplug command 0x03c0 (issued 2048 msec ago)
[ 7.838162] pcieport 0001:00:00.0: pciehp: Timeout on hotplug command 0x07c0 (issued 2020 msec ago)
[ 7.870159] pcieport 0001:00:00.0: pciehp: Timeout on hotplug command 0x07c0 (issued 2052 msec ago)
This not only spams the console output but also induces a delay of a couple of
seconds. To fix this issue, this series clears the HPC bit in PCI_EXP_SLTCAP
register as a part of the post init sequence for all IP versions to not
advertise the hotplug capability for the controller.
Testing
=======
This series has been tested on DB845c (SDM845 SoC) and Lenovo Thinkpad X13s
(SC8280XP SoC).
Thanks,
Mani
Changes in v2:
* Collected tags
* Moved the HPC clearing to a separate function and reused across different
configs
Manivannan Sadhasivam (8):
PCI: qcom: Use DWC helpers for modifying the read-only DBI registers
PCI: qcom: Disable write access to read only registers for IP v2.9.0
PCI: qcom: Do not advertise hotplug capability for IPs v2.7.0 and
v1.9.0
PCI: qcom: Do not advertise hotplug capability for IPs v2.3.3 and
v2.9.0
PCI: qcom: Do not advertise hotplug capability for IP v2.3.2
PCI: qcom: Use post init sequence of IP v2.3.2 for v2.4.0
PCI: qcom: Do not advertise hotplug capability for IP v1.0.0
PCI: qcom: Do not advertise hotplug capability for IP v2.1.0
drivers/pci/controller/dwc/pcie-qcom.c | 73 ++++++++++++++------------
1 file changed, 38 insertions(+), 35 deletions(-)
--
2.25.1
SoCs making use of Qcom PCIe controller IP v1.0.0 do not support hotplug
functionality. But the hotplug capability bit is set by default in the
hardware. This causes the kernel PCI core to register hotplug service for
the controller and send hotplug commands to it. But those commands will
timeout generating messages as below during boot and suspend/resume.
[ 5.782159] pcieport 0001:00:00.0: pciehp: Timeout on hotplug command 0x03c0 (issued 2020 msec ago)
[ 5.810161] pcieport 0001:00:00.0: pciehp: Timeout on hotplug command 0x03c0 (issued 2048 msec ago)
[ 7.838162] pcieport 0001:00:00.0: pciehp: Timeout on hotplug command 0x07c0 (issued 2020 msec ago)
[ 7.870159] pcieport 0001:00:00.0: pciehp: Timeout on hotplug command 0x07c0 (issued 2052 msec ago)
This not only spams the console output but also induces a delay of a
couple of seconds. To fix this issue, let's clear the HPC bit in
PCI_EXP_SLTCAP register as a part of the post init sequence to not
advertise the hotplug capability for the controller.
Signed-off-by: Manivannan Sadhasivam <[email protected]>
---
drivers/pci/controller/dwc/pcie-qcom.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
index e6db9e551752..612266fb849a 100644
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -521,6 +521,8 @@ static int qcom_pcie_post_init_1_0_0(struct qcom_pcie *pcie)
writel(val, pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT);
}
+ qcom_pcie_clear_hpc(pcie->pci);
+
return 0;
}
--
2.25.1
SoCs making use of Qcom PCIe controller IP v2.3.2 do not support hotplug
functionality. But the hotplug capability bit is set by default in the
hardware. This causes the kernel PCI core to register hotplug service for
the controller and send hotplug commands to it. But those commands will
timeout generating messages as below during boot and suspend/resume.
[ 5.782159] pcieport 0001:00:00.0: pciehp: Timeout on hotplug command 0x03c0 (issued 2020 msec ago)
[ 5.810161] pcieport 0001:00:00.0: pciehp: Timeout on hotplug command 0x03c0 (issued 2048 msec ago)
[ 7.838162] pcieport 0001:00:00.0: pciehp: Timeout on hotplug command 0x07c0 (issued 2020 msec ago)
[ 7.870159] pcieport 0001:00:00.0: pciehp: Timeout on hotplug command 0x07c0 (issued 2052 msec ago)
This not only spams the console output but also induces a delay of a
couple of seconds. To fix this issue, let's clear the HPC bit in
PCI_EXP_SLTCAP register as a part of the post init sequence to not
advertise the hotplug capability for the controller.
Signed-off-by: Manivannan Sadhasivam <[email protected]>
---
drivers/pci/controller/dwc/pcie-qcom.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
index 64b6a8c6a99d..9c8dfd224e6e 100644
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -616,6 +616,8 @@ static int qcom_pcie_post_init_2_3_2(struct qcom_pcie *pcie)
val |= EN;
writel(val, pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2);
+ qcom_pcie_clear_hpc(pcie->pci);
+
return 0;
}
--
2.25.1
On Fri, May 19, 2023 at 08:01:09PM +0530, Manivannan Sadhasivam wrote:
> Hi,
>
> The SoCs making use of Qualcomm PCIe controllers do not support the PCIe hotplug
> functionality. But the hotplug capability bit is set by default in the hardware.
> This causes the kernel PCI core to register hotplug service for the controller
> and send hotplug commands to it. But those commands will timeout generating
> messages as below during boot and suspend/resume.
>
> [ 5.782159] pcieport 0001:00:00.0: pciehp: Timeout on hotplug command 0x03c0 (issued 2020 msec ago)
> [ 5.810161] pcieport 0001:00:00.0: pciehp: Timeout on hotplug command 0x03c0 (issued 2048 msec ago)
> [ 7.838162] pcieport 0001:00:00.0: pciehp: Timeout on hotplug command 0x07c0 (issued 2020 msec ago)
> [ 7.870159] pcieport 0001:00:00.0: pciehp: Timeout on hotplug command 0x07c0 (issued 2052 msec ago)
>
> This not only spams the console output but also induces a delay of a couple of
> seconds. To fix this issue, this series clears the HPC bit in PCI_EXP_SLTCAP
> register as a part of the post init sequence for all IP versions to not
> advertise the hotplug capability for the controller.
>
> Testing
> =======
>
> This series has been tested on DB845c (SDM845 SoC) and Lenovo Thinkpad X13s
> (SC8280XP SoC).
>
> Thanks,
> Mani
>
> Changes in v2:
>
> * Collected tags
> * Moved the HPC clearing to a separate function and reused across different
> configs
>
> Manivannan Sadhasivam (8):
> PCI: qcom: Use DWC helpers for modifying the read-only DBI registers
> PCI: qcom: Disable write access to read only registers for IP v2.9.0
> PCI: qcom: Do not advertise hotplug capability for IPs v2.7.0 and
> v1.9.0
> PCI: qcom: Do not advertise hotplug capability for IPs v2.3.3 and
> v2.9.0
> PCI: qcom: Do not advertise hotplug capability for IP v2.3.2
> PCI: qcom: Use post init sequence of IP v2.3.2 for v2.4.0
> PCI: qcom: Do not advertise hotplug capability for IP v1.0.0
> PCI: qcom: Do not advertise hotplug capability for IP v2.1.0
>
> drivers/pci/controller/dwc/pcie-qcom.c | 73 ++++++++++++++------------
> 1 file changed, 38 insertions(+), 35 deletions(-)
>
Some patches are signed-off twice, FYI, I can fix that while
applying.
Lorenzo
> --
> 2.25.1
>
On Mon, May 22, 2023 at 11:01:17AM +0200, Lorenzo Pieralisi wrote:
> On Fri, May 19, 2023 at 08:01:09PM +0530, Manivannan Sadhasivam wrote:
> > Hi,
> >
> > The SoCs making use of Qualcomm PCIe controllers do not support the PCIe hotplug
> > functionality. But the hotplug capability bit is set by default in the hardware.
> > This causes the kernel PCI core to register hotplug service for the controller
> > and send hotplug commands to it. But those commands will timeout generating
> > messages as below during boot and suspend/resume.
> >
> > [ 5.782159] pcieport 0001:00:00.0: pciehp: Timeout on hotplug command 0x03c0 (issued 2020 msec ago)
> > [ 5.810161] pcieport 0001:00:00.0: pciehp: Timeout on hotplug command 0x03c0 (issued 2048 msec ago)
> > [ 7.838162] pcieport 0001:00:00.0: pciehp: Timeout on hotplug command 0x07c0 (issued 2020 msec ago)
> > [ 7.870159] pcieport 0001:00:00.0: pciehp: Timeout on hotplug command 0x07c0 (issued 2052 msec ago)
> >
> > This not only spams the console output but also induces a delay of a couple of
> > seconds. To fix this issue, this series clears the HPC bit in PCI_EXP_SLTCAP
> > register as a part of the post init sequence for all IP versions to not
> > advertise the hotplug capability for the controller.
> >
> > Testing
> > =======
> >
> > This series has been tested on DB845c (SDM845 SoC) and Lenovo Thinkpad X13s
> > (SC8280XP SoC).
> >
> > Thanks,
> > Mani
> >
> > Changes in v2:
> >
> > * Collected tags
> > * Moved the HPC clearing to a separate function and reused across different
> > configs
> >
> > Manivannan Sadhasivam (8):
> > PCI: qcom: Use DWC helpers for modifying the read-only DBI registers
> > PCI: qcom: Disable write access to read only registers for IP v2.9.0
> > PCI: qcom: Do not advertise hotplug capability for IPs v2.7.0 and
> > v1.9.0
> > PCI: qcom: Do not advertise hotplug capability for IPs v2.3.3 and
> > v2.9.0
> > PCI: qcom: Do not advertise hotplug capability for IP v2.3.2
> > PCI: qcom: Use post init sequence of IP v2.3.2 for v2.4.0
> > PCI: qcom: Do not advertise hotplug capability for IP v1.0.0
> > PCI: qcom: Do not advertise hotplug capability for IP v2.1.0
> >
> > drivers/pci/controller/dwc/pcie-qcom.c | 73 ++++++++++++++------------
> > 1 file changed, 38 insertions(+), 35 deletions(-)
> >
>
> Some patches are signed-off twice, FYI, I can fix that while
> applying.
>
Sorry for that! I used b4 to apply these patches and that added additional
signed-off-by tag for all patches. Since Dmitry also requested to remove his
gmail tag, I can spin another version once we sort out the comment on patch
2/8.
- Mani
> Lorenzo
>
> > --
> > 2.25.1
> >
--
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