Hi,
This enables SATA support for RK3588.
Changes since PATCHv1:
* https://lore.kernel.org/all/[email protected]/
* Rebase to v6.4-rc1
* Collect Acked-by for syscon DT binding update
* Use ASIC clock description suggested by Serge Semin
* Also add RBC clock (not used by RK3588)
* Add extra patch narrowing down the allowed clocks for RK356x and RK3588
-- Sebastian
Sebastian Reichel (6):
dt-bindings: soc: rockchip: add rk3588 pipe-phy syscon
dt-bindings: ata: ahci: add RK3588 AHCI controller
dt-bindings: ata: ahci: dwc: enforce rockchip clocks
dt-bindings: phy: rockchip: rk3588 has two reset lines
arm64: dts: rockchip: rk3588: add combo PHYs
arm64: dts: rockchip: rk3588: add SATA support
.../bindings/ata/snps,dwc-ahci-common.yaml | 8 +-
.../bindings/ata/snps,dwc-ahci.yaml | 40 +++++++--
.../phy/phy-rockchip-naneng-combphy.yaml | 8 +-
.../devicetree/bindings/soc/rockchip/grf.yaml | 1 +
arch/arm64/boot/dts/rockchip/rk3588.dtsi | 44 +++++++++
arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 90 +++++++++++++++++++
6 files changed, 183 insertions(+), 8 deletions(-)
--
2.39.2
Add all 3 combo PHYs that can be found in RK3588.
They are used for SATA, PCIe or USB3.
Signed-off-by: Sebastian Reichel <[email protected]>
---
arch/arm64/boot/dts/rockchip/rk3588.dtsi | 21 ++++++++++++
arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 42 +++++++++++++++++++++++
2 files changed, 63 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3588.dtsi b/arch/arm64/boot/dts/rockchip/rk3588.dtsi
index 8be75556af8f..9d8539b5309b 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588.dtsi
@@ -7,6 +7,11 @@
#include "rk3588-pinctrl.dtsi"
/ {
+ pipe_phy1_grf: syscon@fd5c0000 {
+ compatible = "rockchip,rk3588-pipe-phy-grf", "syscon";
+ reg = <0x0 0xfd5c0000 0x0 0x100>;
+ };
+
i2s8_8ch: i2s@fddc8000 {
compatible = "rockchip,rk3588-i2s-tdm";
reg = <0x0 0xfddc8000 0x0 0x1000>;
@@ -123,4 +128,20 @@ gmac0_mtl_tx_setup: tx-queues-config {
queue1 {};
};
};
+
+ combphy1_ps: phy@fee10000 {
+ compatible = "rockchip,rk3588-naneng-combphy";
+ reg = <0x0 0xfee10000 0x0 0x100>;
+ #phy-cells = <1>;
+ clocks = <&cru CLK_REF_PIPE_PHY1>, <&cru PCLK_PCIE_COMBO_PIPE_PHY1>,
+ <&cru PCLK_PHP_ROOT>;
+ clock-names = "ref", "apb", "pipe";
+ assigned-clocks = <&cru CLK_REF_PIPE_PHY1>;
+ assigned-clock-rates = <100000000>;
+ resets = <&cru SRST_REF_PIPE_PHY1>, <&cru SRST_P_PCIE2_PHY1>;
+ reset-names = "phy", "apb";
+ rockchip,pipe-grf = <&php_grf>;
+ rockchip,pipe-phy-grf = <&pipe_phy1_grf>;
+ status = "disabled";
+ };
};
diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
index 01058fed8f96..45ae457a22a4 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
@@ -944,6 +944,16 @@ php_grf: syscon@fd5b0000 {
reg = <0x0 0xfd5b0000 0x0 0x1000>;
};
+ pipe_phy0_grf: syscon@fd5bc000 {
+ compatible = "rockchip,rk3588-pipe-phy-grf", "syscon";
+ reg = <0x0 0xfd5bc000 0x0 0x100>;
+ };
+
+ pipe_phy2_grf: syscon@fd5c4000 {
+ compatible = "rockchip,rk3588-pipe-phy-grf", "syscon";
+ reg = <0x0 0xfd5c4000 0x0 0x100>;
+ };
+
ioc: syscon@fd5f0000 {
compatible = "rockchip,rk3588-ioc", "syscon";
reg = <0x0 0xfd5f0000 0x0 0x10000>;
@@ -2371,6 +2381,38 @@ dmac2: dma-controller@fed10000 {
#dma-cells = <1>;
};
+ combphy0_ps: phy@fee00000 {
+ compatible = "rockchip,rk3588-naneng-combphy";
+ reg = <0x0 0xfee00000 0x0 0x100>;
+ #phy-cells = <1>;
+ clocks = <&cru CLK_REF_PIPE_PHY0>, <&cru PCLK_PCIE_COMBO_PIPE_PHY0>,
+ <&cru PCLK_PHP_ROOT>;
+ clock-names = "ref", "apb", "pipe";
+ assigned-clocks = <&cru CLK_REF_PIPE_PHY0>;
+ assigned-clock-rates = <100000000>;
+ resets = <&cru SRST_REF_PIPE_PHY0>, <&cru SRST_P_PCIE2_PHY0>;
+ reset-names = "phy", "apb";
+ rockchip,pipe-grf = <&php_grf>;
+ rockchip,pipe-phy-grf = <&pipe_phy0_grf>;
+ status = "disabled";
+ };
+
+ combphy2_psu: phy@fee20000 {
+ compatible = "rockchip,rk3588-naneng-combphy";
+ reg = <0x0 0xfee20000 0x0 0x100>;
+ #phy-cells = <1>;
+ clocks = <&cru CLK_REF_PIPE_PHY2>, <&cru PCLK_PCIE_COMBO_PIPE_PHY2>,
+ <&cru PCLK_PHP_ROOT>;
+ clock-names = "ref", "apb", "pipe";
+ assigned-clocks = <&cru CLK_REF_PIPE_PHY2>;
+ assigned-clock-rates = <100000000>;
+ resets = <&cru SRST_REF_PIPE_PHY2>, <&cru SRST_P_PCIE2_PHY2>;
+ reset-names = "phy", "apb";
+ rockchip,pipe-grf = <&php_grf>;
+ rockchip,pipe-phy-grf = <&pipe_phy2_grf>;
+ status = "disabled";
+ };
+
system_sram2: sram@ff001000 {
compatible = "mmio-sram";
reg = <0x0 0xff001000 0x0 0xef000>;
--
2.39.2
The RK3588 has two reset lines for the combphy. One for the
APB interface and one for the actual PHY.
Signed-off-by: Sebastian Reichel <[email protected]>
---
.../bindings/phy/phy-rockchip-naneng-combphy.yaml | 8 +++++++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml b/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml
index 9ae514fa7533..82550a5c2ed5 100644
--- a/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml
+++ b/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml
@@ -31,8 +31,14 @@ properties:
- const: pipe
resets:
+ minItems: 1
+ maxItems: 2
+
+ reset-names:
+ minItems: 1
items:
- - description: exclusive PHY reset line
+ - const: phy
+ - const: apb
rockchip,enable-ssc:
type: boolean
--
2.39.2
Add all three SATA IP blocks to the RK3588 DT.
Signed-off-by: Sebastian Reichel <[email protected]>
---
arch/arm64/boot/dts/rockchip/rk3588.dtsi | 23 +++++++++++
arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 48 +++++++++++++++++++++++
2 files changed, 71 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3588.dtsi b/arch/arm64/boot/dts/rockchip/rk3588.dtsi
index 9d8539b5309b..b9508cea34f1 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588.dtsi
@@ -129,6 +129,29 @@ gmac0_mtl_tx_setup: tx-queues-config {
};
};
+ sata1: sata@fe220000 {
+ compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci";
+ reg = <0 0xfe220000 0 0x1000>;
+ clocks = <&cru ACLK_SATA1>, <&cru CLK_PMALIVE1>,
+ <&cru CLK_RXOOB1>, <&cru CLK_PIPEPHY1_REF>,
+ <&cru CLK_PIPEPHY1_PIPE_ASIC_G>;
+ clock-names = "sata", "pmalive", "rxoob", "ref", "asic";
+ interrupts = <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH 0>;
+ ports-implemented = <0x1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ sata-port@0 {
+ reg = <0>;
+ hba-port-cap = <HBA_PORT_FBSCP>;
+ phys = <&combphy1_ps PHY_TYPE_SATA>;
+ phy-names = "sata-phy";
+ snps,rx-ts-max = <32>;
+ snps,tx-ts-max = <32>;
+ };
+ };
+
combphy1_ps: phy@fee10000 {
compatible = "rockchip,rk3588-naneng-combphy";
reg = <0x0 0xfee10000 0x0 0x100>;
diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
index 45ae457a22a4..00a91b08e3bb 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
@@ -9,6 +9,8 @@
#include <dt-bindings/power/rk3588-power.h>
#include <dt-bindings/reset/rockchip,rk3588-cru.h>
#include <dt-bindings/thermal/thermal.h>
+#include <dt-bindings/phy/phy.h>
+#include <dt-bindings/ata/ahci.h>
/ {
compatible = "rockchip,rk3588";
@@ -1717,6 +1719,52 @@ gmac1_mtl_tx_setup: tx-queues-config {
};
};
+ sata0: sata@fe210000 {
+ compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci";
+ reg = <0 0xfe210000 0 0x1000>;
+ clocks = <&cru ACLK_SATA0>, <&cru CLK_PMALIVE0>,
+ <&cru CLK_RXOOB0>, <&cru CLK_PIPEPHY0_REF>,
+ <&cru CLK_PIPEPHY0_PIPE_ASIC_G>;
+ clock-names = "sata", "pmalive", "rxoob", "ref", "asic";
+ interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH 0>;
+ ports-implemented = <0x1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ sata-port@0 {
+ reg = <0>;
+ hba-port-cap = <HBA_PORT_FBSCP>;
+ phys = <&combphy0_ps PHY_TYPE_SATA>;
+ phy-names = "sata-phy";
+ snps,rx-ts-max = <32>;
+ snps,tx-ts-max = <32>;
+ };
+ };
+
+ sata2: sata@fe230000 {
+ compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci";
+ reg = <0 0xfe230000 0 0x1000>;
+ clocks = <&cru ACLK_SATA2>, <&cru CLK_PMALIVE2>,
+ <&cru CLK_RXOOB2>, <&cru CLK_PIPEPHY2_REF>,
+ <&cru CLK_PIPEPHY2_PIPE_ASIC_G>;
+ clock-names = "sata", "pmalive", "rxoob", "ref", "asic";
+ interrupts = <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH 0>;
+ ports-implemented = <0x1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ sata-port@0 {
+ reg = <0>;
+ hba-port-cap = <HBA_PORT_FBSCP>;
+ phys = <&combphy2_psu PHY_TYPE_SATA>;
+ phy-names = "sata-phy";
+ snps,rx-ts-max = <32>;
+ snps,tx-ts-max = <32>;
+ };
+ };
+
sdmmc: mmc@fe2c0000 {
compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x0 0xfe2c0000 0x0 0x4000>;
--
2.39.2
Hey Sebastian,
On Mon, May 22, 2023 at 07:34:21PM +0200, Sebastian Reichel wrote:
> The RK3588 has two reset lines for the combphy. One for the
> APB interface and one for the actual PHY.
But the 68 only has one? Should per-compatible enforcement be added
like you added for the clocks?
> Signed-off-by: Sebastian Reichel <[email protected]>
> ---
> .../bindings/phy/phy-rockchip-naneng-combphy.yaml | 8 +++++++-
> 1 file changed, 7 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml b/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml
> index 9ae514fa7533..82550a5c2ed5 100644
> --- a/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml
> +++ b/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml
> @@ -31,8 +31,14 @@ properties:
> - const: pipe
>
> resets:
> + minItems: 1
> + maxItems: 2
> +
> + reset-names:
> + minItems: 1
> items:
> - - description: exclusive PHY reset line
> + - const: phy
> + - const: apb
>
> rockchip,enable-ssc:
> type: boolean
> --
> 2.39.2
>
Hello Sebastian
On Mon, May 22, 2023 at 07:34:17PM +0200, Sebastian Reichel wrote:
> Hi,
>
> This enables SATA support for RK3588.
Thanks for the updated series. I'll have a look at the DW AHCI SATA
part of it on this week.
-Serge(y)
>
> Changes since PATCHv1:
> * https://lore.kernel.org/all/[email protected]/
> * Rebase to v6.4-rc1
> * Collect Acked-by for syscon DT binding update
> * Use ASIC clock description suggested by Serge Semin
> * Also add RBC clock (not used by RK3588)
> * Add extra patch narrowing down the allowed clocks for RK356x and RK3588
>
> -- Sebastian
>
> Sebastian Reichel (6):
> dt-bindings: soc: rockchip: add rk3588 pipe-phy syscon
> dt-bindings: ata: ahci: add RK3588 AHCI controller
> dt-bindings: ata: ahci: dwc: enforce rockchip clocks
> dt-bindings: phy: rockchip: rk3588 has two reset lines
> arm64: dts: rockchip: rk3588: add combo PHYs
> arm64: dts: rockchip: rk3588: add SATA support
>
> .../bindings/ata/snps,dwc-ahci-common.yaml | 8 +-
> .../bindings/ata/snps,dwc-ahci.yaml | 40 +++++++--
> .../phy/phy-rockchip-naneng-combphy.yaml | 8 +-
> .../devicetree/bindings/soc/rockchip/grf.yaml | 1 +
> arch/arm64/boot/dts/rockchip/rk3588.dtsi | 44 +++++++++
> arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 90 +++++++++++++++++++
> 6 files changed, 183 insertions(+), 8 deletions(-)
>
> --
> 2.39.2
>
On Mon, 22 May 2023 19:34:17 +0200, Sebastian Reichel wrote:
> This enables SATA support for RK3588.
>
> Changes since PATCHv1:
> * https://lore.kernel.org/all/[email protected]/
> * Rebase to v6.4-rc1
> * Collect Acked-by for syscon DT binding update
> * Use ASIC clock description suggested by Serge Semin
> * Also add RBC clock (not used by RK3588)
> * Add extra patch narrowing down the allowed clocks for RK356x and RK3588
>
> [...]
Applied, thanks!
[1/6] dt-bindings: soc: rockchip: add rk3588 pipe-phy syscon
commit: ea85370df14011255c60e1951ef4ef749806aa5c
Best regards,
--
Heiko Stuebner <[email protected]>