Add sdhc node for eMMC on QDU1000 and QRU1000 SoCs.
Signed-off-by: Komal Bajaj <[email protected]>
---
arch/arm64/boot/dts/qcom/qdu1000.dtsi | 51 +++++++++++++++++++++++++++
1 file changed, 51 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/qdu1000.dtsi b/arch/arm64/boot/dts/qcom/qdu1000.dtsi
index 734438113bba..38ee7115a35f 100644
--- a/arch/arm64/boot/dts/qcom/qdu1000.dtsi
+++ b/arch/arm64/boot/dts/qcom/qdu1000.dtsi
@@ -19,6 +19,10 @@
chosen: chosen { };
+ aliases {
+ mmc0 = &sdhc_1; /* eMMC */
+ };
+
cpus {
#address-cells = <2>;
#size-cells = <0>;
@@ -842,6 +846,53 @@
#hwlock-cells = <1>;
};
+ sdhc_1: mmc@8804000 {
+ compatible = "qcom,qdu1000-sdhci", "qcom,sdhci-msm-v5";
+ reg = <0x0 0x08804000 0x0 0x1000>,
+ <0x0 0x08805000 0x0 0x1000>;
+ reg-names = "hc", "cqhci";
+
+ interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hc_irq", "pwr_irq";
+
+ clocks = <&gcc GCC_SDCC5_AHB_CLK>,
+ <&gcc GCC_SDCC5_APPS_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "iface",
+ "core",
+ "xo";
+
+ resets = <&gcc GCC_SDCC5_BCR>;
+
+ interconnects = <&system_noc MASTER_SDCC_1 0 &mc_virt SLAVE_EBI1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_SDCC_2 0>;
+ interconnect-names = "sdhc-ddr", "cpu-sdhc";
+ power-domains = <&rpmhpd QDU1000_CX>;
+ operating-points-v2 = <&sdhc1_opp_table>;
+
+ iommus = <&apps_smmu 0x80 0x0>;
+ dma-coherent;
+
+ bus-width = <8>;
+
+ qcom,dll-config = <0x0007642c>;
+ qcom,ddr-config = <0x80040868>;
+
+ status = "disabled";
+
+ sdhc1_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-384000000 {
+ opp-hz = /bits/ 64 <384000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ opp-peak-kBps = <6528000 1652800>;
+ opp-avg-kBps = <400000 0>;
+ };
+ };
+ };
+
pdc: interrupt-controller@b220000 {
compatible = "qcom,qdu1000-pdc", "qcom,pdc";
reg = <0x0 0xb220000 0x0 0x30000>, <0x0 0x174000f0 0x0 0x64>;
--
2.17.1
On Mon, May 22, 2023 at 03:06:18PM +0530, Komal Bajaj wrote:
Path says arch/arm64/, so $subject should start "arm64: dts: qcom: ..."
> Add sdhc node for eMMC on QDU1000 and QRU1000 SoCs.
>
> Signed-off-by: Komal Bajaj <[email protected]>
> ---
> arch/arm64/boot/dts/qcom/qdu1000.dtsi | 51 +++++++++++++++++++++++++++
> 1 file changed, 51 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/qdu1000.dtsi b/arch/arm64/boot/dts/qcom/qdu1000.dtsi
> index 734438113bba..38ee7115a35f 100644
> --- a/arch/arm64/boot/dts/qcom/qdu1000.dtsi
> +++ b/arch/arm64/boot/dts/qcom/qdu1000.dtsi
> @@ -19,6 +19,10 @@
>
> chosen: chosen { };
>
> + aliases {
> + mmc0 = &sdhc_1; /* eMMC */
Don't we just have a single SDC instance on this platform? If so you
don't need aliases.
> + };
> +
> cpus {
> #address-cells = <2>;
> #size-cells = <0>;
> @@ -842,6 +846,53 @@
> #hwlock-cells = <1>;
> };
>
> + sdhc_1: mmc@8804000 {
And you can skip the "_1" suffix...
Regards,
Bjorn
> + compatible = "qcom,qdu1000-sdhci", "qcom,sdhci-msm-v5";
> + reg = <0x0 0x08804000 0x0 0x1000>,
> + <0x0 0x08805000 0x0 0x1000>;
> + reg-names = "hc", "cqhci";
> +
> + interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "hc_irq", "pwr_irq";
> +
> + clocks = <&gcc GCC_SDCC5_AHB_CLK>,
> + <&gcc GCC_SDCC5_APPS_CLK>,
> + <&rpmhcc RPMH_CXO_CLK>;
> + clock-names = "iface",
> + "core",
> + "xo";
> +
> + resets = <&gcc GCC_SDCC5_BCR>;
> +
> + interconnects = <&system_noc MASTER_SDCC_1 0 &mc_virt SLAVE_EBI1 0>,
> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_SDCC_2 0>;
> + interconnect-names = "sdhc-ddr", "cpu-sdhc";
> + power-domains = <&rpmhpd QDU1000_CX>;
> + operating-points-v2 = <&sdhc1_opp_table>;
> +
> + iommus = <&apps_smmu 0x80 0x0>;
> + dma-coherent;
> +
> + bus-width = <8>;
> +
> + qcom,dll-config = <0x0007642c>;
> + qcom,ddr-config = <0x80040868>;
> +
> + status = "disabled";
> +
> + sdhc1_opp_table: opp-table {
> + compatible = "operating-points-v2";
> +
> + opp-384000000 {
> + opp-hz = /bits/ 64 <384000000>;
> + required-opps = <&rpmhpd_opp_nom>;
> + opp-peak-kBps = <6528000 1652800>;
> + opp-avg-kBps = <400000 0>;
> + };
> + };
> + };
> +
> pdc: interrupt-controller@b220000 {
> compatible = "qcom,qdu1000-pdc", "qcom,pdc";
> reg = <0x0 0xb220000 0x0 0x30000>, <0x0 0x174000f0 0x0 0x64>;
> --
> 2.17.1
>
On 5/22/2023 8:31 PM, Bjorn Andersson wrote:
> On Mon, May 22, 2023 at 03:06:18PM +0530, Komal Bajaj wrote:
>
> Path says arch/arm64/, so $subject should start "arm64: dts: qcom: ..."
>
>> Add sdhc node for eMMC on QDU1000 and QRU1000 SoCs.
>>
>> Signed-off-by: Komal Bajaj <[email protected]>
>> ---
>> arch/arm64/boot/dts/qcom/qdu1000.dtsi | 51 +++++++++++++++++++++++++++
>> 1 file changed, 51 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/qdu1000.dtsi b/arch/arm64/boot/dts/qcom/qdu1000.dtsi
>> index 734438113bba..38ee7115a35f 100644
>> --- a/arch/arm64/boot/dts/qcom/qdu1000.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/qdu1000.dtsi
>> @@ -19,6 +19,10 @@
>>
>> chosen: chosen { };
>>
>> + aliases {
>> + mmc0 = &sdhc_1; /* eMMC */
> Don't we just have a single SDC instance on this platform? If so you
> don't need aliases.
Sure, will remove aliases.
>
>> + };
>> +
>> cpus {
>> #address-cells = <2>;
>> #size-cells = <0>;
>> @@ -842,6 +846,53 @@
>> #hwlock-cells = <1>;
>> };
>>
>> + sdhc_1: mmc@8804000 {
> And you can skip the "_1" suffix...
Sure
Thanks
Komal
>
> Regards,
> Bjorn
>
>> + compatible = "qcom,qdu1000-sdhci", "qcom,sdhci-msm-v5";
>> + reg = <0x0 0x08804000 0x0 0x1000>,
>> + <0x0 0x08805000 0x0 0x1000>;
>> + reg-names = "hc", "cqhci";
>> +
>> + interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
>> + interrupt-names = "hc_irq", "pwr_irq";
>> +
>> + clocks = <&gcc GCC_SDCC5_AHB_CLK>,
>> + <&gcc GCC_SDCC5_APPS_CLK>,
>> + <&rpmhcc RPMH_CXO_CLK>;
>> + clock-names = "iface",
>> + "core",
>> + "xo";
>> +
>> + resets = <&gcc GCC_SDCC5_BCR>;
>> +
>> + interconnects = <&system_noc MASTER_SDCC_1 0 &mc_virt SLAVE_EBI1 0>,
>> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_SDCC_2 0>;
>> + interconnect-names = "sdhc-ddr", "cpu-sdhc";
>> + power-domains = <&rpmhpd QDU1000_CX>;
>> + operating-points-v2 = <&sdhc1_opp_table>;
>> +
>> + iommus = <&apps_smmu 0x80 0x0>;
>> + dma-coherent;
>> +
>> + bus-width = <8>;
>> +
>> + qcom,dll-config = <0x0007642c>;
>> + qcom,ddr-config = <0x80040868>;
>> +
>> + status = "disabled";
>> +
>> + sdhc1_opp_table: opp-table {
>> + compatible = "operating-points-v2";
>> +
>> + opp-384000000 {
>> + opp-hz = /bits/ 64 <384000000>;
>> + required-opps = <&rpmhpd_opp_nom>;
>> + opp-peak-kBps = <6528000 1652800>;
>> + opp-avg-kBps = <400000 0>;
>> + };
>> + };
>> + };
>> +
>> pdc: interrupt-controller@b220000 {
>> compatible = "qcom,qdu1000-pdc", "qcom,pdc";
>> reg = <0x0 0xb220000 0x0 0x30000>, <0x0 0x174000f0 0x0 0x64>;
>> --
>> 2.17.1
>>