struct dmc_count_channel::total counts the clock cycles of the DDR
controller. Rename it accordingly to give the reader a better idea
what this is about. While at it, at some documentation to struct
dmc_count_channel.
Signed-off-by: Sascha Hauer <[email protected]>
---
drivers/devfreq/event/rockchip-dfi.c | 19 ++++++++++++-------
1 file changed, 12 insertions(+), 7 deletions(-)
diff --git a/drivers/devfreq/event/rockchip-dfi.c b/drivers/devfreq/event/rockchip-dfi.c
index 8a7af7c32ae0d..50e497455dc69 100644
--- a/drivers/devfreq/event/rockchip-dfi.c
+++ b/drivers/devfreq/event/rockchip-dfi.c
@@ -46,9 +46,14 @@
#define DDRMON_CH1_COUNT_NUM 0x3c
#define DDRMON_CH1_DFI_ACCESS_NUM 0x40
+/**
+ * struct dmc_count_channel - structure to hold counter values from the DDR controller
+ * @access: Number of read and write accesses
+ * @clock_cycles: DDR clock cycles
+ */
struct dmc_count_channel {
u32 access;
- u32 total;
+ u32 clock_cycles;
};
struct dmc_count {
@@ -150,7 +155,7 @@ static void rockchip_dfi_read_counters(struct rockchip_dfi *dfi, struct dmc_coun
continue;
count->c[i].access = readl_relaxed(dfi_regs +
DDRMON_CH0_DFI_ACCESS_NUM + i * 20);
- count->c[i].total = readl_relaxed(dfi_regs +
+ count->c[i].clock_cycles = readl_relaxed(dfi_regs +
DDRMON_CH0_COUNT_NUM + i * 20);
}
}
@@ -182,29 +187,29 @@ static int rockchip_dfi_get_event(struct devfreq_event_dev *edev,
struct rockchip_dfi *dfi = devfreq_event_get_drvdata(edev);
struct dmc_count count;
struct dmc_count *last = &dfi->last_event_count;
- u32 access = 0, total = 0;
+ u32 access = 0, clock_cycles = 0;
int i;
rockchip_dfi_read_counters(dfi, &count);
/* We can only report one channel, so find the busiest one */
for (i = 0; i < DMC_MAX_CHANNELS; i++) {
- u32 a, t;
+ u32 a, c;
if (!(dfi->channel_mask & BIT(i)))
continue;
a = count.c[i].access - last->c[i].access;
- t = count.c[i].total - last->c[i].total;
+ c = count.c[i].clock_cycles - last->c[i].clock_cycles;
if (a > access) {
access = a;
- total = t;
+ clock_cycles = c;
}
}
edata->load_count = access * 4;
- edata->total_count = total;
+ edata->total_count = clock_cycles;
dfi->last_event_count = count;
--
2.39.2
Hi,
On Wed, May 24, 2023 at 10:31:43AM +0200, Sascha Hauer wrote:
> struct dmc_count_channel::total counts the clock cycles of the DDR
> controller. Rename it accordingly to give the reader a better idea
> what this is about. While at it, at some documentation to struct
> dmc_count_channel.
>
> Signed-off-by: Sascha Hauer <[email protected]>
> ---
Reviewed-by: Sebastian Reichel <[email protected]>
-- Sebastian
> drivers/devfreq/event/rockchip-dfi.c | 19 ++++++++++++-------
> 1 file changed, 12 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/devfreq/event/rockchip-dfi.c b/drivers/devfreq/event/rockchip-dfi.c
> index 8a7af7c32ae0d..50e497455dc69 100644
> --- a/drivers/devfreq/event/rockchip-dfi.c
> +++ b/drivers/devfreq/event/rockchip-dfi.c
> @@ -46,9 +46,14 @@
> #define DDRMON_CH1_COUNT_NUM 0x3c
> #define DDRMON_CH1_DFI_ACCESS_NUM 0x40
>
> +/**
> + * struct dmc_count_channel - structure to hold counter values from the DDR controller
> + * @access: Number of read and write accesses
> + * @clock_cycles: DDR clock cycles
> + */
> struct dmc_count_channel {
> u32 access;
> - u32 total;
> + u32 clock_cycles;
> };
>
> struct dmc_count {
> @@ -150,7 +155,7 @@ static void rockchip_dfi_read_counters(struct rockchip_dfi *dfi, struct dmc_coun
> continue;
> count->c[i].access = readl_relaxed(dfi_regs +
> DDRMON_CH0_DFI_ACCESS_NUM + i * 20);
> - count->c[i].total = readl_relaxed(dfi_regs +
> + count->c[i].clock_cycles = readl_relaxed(dfi_regs +
> DDRMON_CH0_COUNT_NUM + i * 20);
> }
> }
> @@ -182,29 +187,29 @@ static int rockchip_dfi_get_event(struct devfreq_event_dev *edev,
> struct rockchip_dfi *dfi = devfreq_event_get_drvdata(edev);
> struct dmc_count count;
> struct dmc_count *last = &dfi->last_event_count;
> - u32 access = 0, total = 0;
> + u32 access = 0, clock_cycles = 0;
> int i;
>
> rockchip_dfi_read_counters(dfi, &count);
>
> /* We can only report one channel, so find the busiest one */
> for (i = 0; i < DMC_MAX_CHANNELS; i++) {
> - u32 a, t;
> + u32 a, c;
>
> if (!(dfi->channel_mask & BIT(i)))
> continue;
>
> a = count.c[i].access - last->c[i].access;
> - t = count.c[i].total - last->c[i].total;
> + c = count.c[i].clock_cycles - last->c[i].clock_cycles;
>
> if (a > access) {
> access = a;
> - total = t;
> + clock_cycles = c;
> }
> }
>
> edata->load_count = access * 4;
> - edata->total_count = total;
> + edata->total_count = clock_cycles;
>
> dfi->last_event_count = count;
>
> --
> 2.39.2
>