2023-05-26 06:29:33

by William Qiu

Subject: [PATCH v1 0/3] Add initialization of clock for StarFive JH7110 SoC

Hi,

This patchset adds initial rudimentary support for the StarFive
Quad SPI controller driver. And this driver will be used in
StarFive's VisionFive 2 board. In 6.4, the QSPI_AHB and QSPI_APB
clocks changed from the default ON state to the default OFF state,
so these clocks need to be enabled in the driver.At the same time,
dts patch is added to this series.

The patch series is based on v6.4rc3.

William Qiu (3):
dt-bindings: qspi: cdns,qspi-nor: Add clocks for StarFive JH7110 SoC
spi: cadence-quadspi: Add clock configuration for StarFive JH7110 QSPI
riscv: dts: starfive: Add QSPI controller node for StarFive JH7110 SoC

.../bindings/spi/cdns,qspi-nor.yaml | 15 +++++++--
.../jh7110-starfive-visionfive-2.dtsi | 32 +++++++++++++++++++
arch/riscv/boot/dts/starfive/jh7110.dtsi | 18 +++++++++++
drivers/spi/spi-cadence-quadspi.c | 27 ++++++++++++++++
4 files changed, 89 insertions(+), 3 deletions(-)

--
2.34.1

2023-05-26 06:38:44

by William Qiu

Subject: [PATCH v1 3/3] riscv: dts: starfive: Add QSPI controller node for StarFive JH7110 SoC

Add the quad spi controller node for the StarFive JH7110 SoC.

Co-developed-by: Ziv Xu <[email protected]>
Signed-off-by: Ziv Xu <[email protected]>
Signed-off-by: William Qiu <[email protected]>
Reviewed-by: Hal Feng <[email protected]>
---
.../jh7110-starfive-visionfive-2.dtsi | 32 +++++++++++++++++++
arch/riscv/boot/dts/starfive/jh7110.dtsi | 18 +++++++++++
2 files changed, 50 insertions(+)

diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
index 2a6d81609284..22212c1150f9 100644
--- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
@@ -126,6 +126,38 @@ &i2c6 {
status = "okay";
};

+&qspi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ nor_flash: flash@0 {
+ compatible = "jedec,spi-nor";
+ reg=<0>;
+ cdns,read-delay = <5>;
+ spi-max-frequency = <12000000>;
+ cdns,tshsl-ns = <1>;
+ cdns,tsd2d-ns = <1>;
+ cdns,tchsh-ns = <1>;
+ cdns,tslch-ns = <1>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ spl@0 {
+ reg = <0x0 0x20000>;
+ };
+ uboot@100000 {
+ reg = <0x100000 0x300000>;
+ };
+ data@f00000 {
+ reg = <0xf00000 0x100000>;
+ };
+ };
+ };
+};
+
&sysgpio {
i2c0_pins: i2c0-0 {
i2c-pins {
diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
index 4c5fdb905da8..6385443d011f 100644
--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
@@ -440,6 +440,24 @@ i2c6: i2c@12060000 {
status = "disabled";
};

+ qspi: spi@13010000 {
+ compatible = "starfive,jh7110-qspi", "cdns,qspi-nor";
+ reg = <0x0 0x13010000 0x0 0x10000
+ 0x0 0x21000000 0x0 0x400000>;
+ interrupts = <25>;
+ clocks = <&syscrg JH7110_SYSCLK_QSPI_REF>,
+ <&syscrg JH7110_SYSCLK_QSPI_AHB>,
+ <&syscrg JH7110_SYSCLK_QSPI_APB>;
+ clock-names = "qspi-ref", "qspi-ahb", "qspi-apb";
+ resets = <&syscrg JH7110_SYSRST_QSPI_APB>,
+ <&syscrg JH7110_SYSRST_QSPI_AHB>,
+ <&syscrg JH7110_SYSRST_QSPI_REF>;
+ reset-names = "qspi", "qspi-ocp", "rstc_ref";
+ cdns,fifo-depth = <256>;
+ cdns,fifo-width = <4>;
+ cdns,trigger-address = <0x0>;
+ };
+
syscrg: clock-controller@13020000 {
compatible = "starfive,jh7110-syscrg";
reg = <0x0 0x13020000 0x0 0x10000>;
--
2.34.1