From: Hugo Villeneuve <[email protected]>
This commit is taken from Variscite linux kernel public git repository.
Original patch author: Nate Drude <[email protected]>
See: https://github.com/varigit/linux-imx/blob/5.15-2.0.x-imx_var01/drivers/net/ethernet/freescale/fec_main.c#L3993-L4050
The ethernet phy reset was moved from the fec controller to the
mdio bus, see for example: 0e825b32c033e1998d0ebaf247f5dab3c340e3bf
When the fec driver managed the reset, the regulator had time to
settle during the fec phy reset before calling of_mdiobus_register,
which probes the mii bus for the phy id to match the correct driver.
Now that the mdio bus controls the reset, the fec driver no longer has
any delay between enabling the regulator and calling of_mdiobus_register.
If the regulator voltage has not settled, the phy id will not be read
correctly and the generic phy driver will be used.
The following call tree explains in more detail:
fec_probe
fec_reset_phy <- no longer introduces delay after migration to mdio reset
fec_enet_mii_init
of_mdiobus_register
of_mdiobus_register_phy
fwnode_mdiobus_register_phy
get_phy_device <- mii probe for phy id to match driver happens here
...
fwnode_mdiobus_phy_device_register
phy_device_register
mdiobus_register_device
mdio_device_reset <- mdio reset assert / deassert delay happens here
Add a 20ms enable delay to the regulator to fix the issue.
Signed-off-by: Hugo Villeneuve <[email protected]>
---
arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi
index cbd9d124c80d..a502ef7394a3 100644
--- a/arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi
@@ -27,6 +27,7 @@ reg_eth_phy: regulator-eth-phy {
regulator-name = "eth_phy_pwr";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
+ regulator-enable-ramp-delay = <20000>;
gpio = <&gpio2 9 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
base-commit: 8b817fded42d8fe3a0eb47b1149d907851a3c942
--
2.30.2
On Mon, May 29, 2023 at 03:33:12PM -0400, Hugo Villeneuve wrote:
> From: Hugo Villeneuve <[email protected]>
>
> This commit is taken from Variscite linux kernel public git repository.
> Original patch author: Nate Drude <[email protected]>
> See: https://github.com/varigit/linux-imx/blob/5.15-2.0.x-imx_var01/drivers/net/ethernet/freescale/fec_main.c#L3993-L4050
>
> The ethernet phy reset was moved from the fec controller to the
> mdio bus, see for example: 0e825b32c033e1998d0ebaf247f5dab3c340e3bf
>
> When the fec driver managed the reset, the regulator had time to
> settle during the fec phy reset before calling of_mdiobus_register,
> which probes the mii bus for the phy id to match the correct driver.
>
> Now that the mdio bus controls the reset, the fec driver no longer has
> any delay between enabling the regulator and calling of_mdiobus_register.
> If the regulator voltage has not settled, the phy id will not be read
> correctly and the generic phy driver will be used.
>
> The following call tree explains in more detail:
>
> fec_probe
> fec_reset_phy <- no longer introduces delay after migration to mdio reset
> fec_enet_mii_init
> of_mdiobus_register
> of_mdiobus_register_phy
> fwnode_mdiobus_register_phy
> get_phy_device <- mii probe for phy id to match driver happens here
> ...
> fwnode_mdiobus_phy_device_register
> phy_device_register
> mdiobus_register_device
> mdio_device_reset <- mdio reset assert / deassert delay happens here
>
> Add a 20ms enable delay to the regulator to fix the issue.
>
> Signed-off-by: Hugo Villeneuve <[email protected]>
Applied, thanks!