Changes in v5 -
* Combined sdhc node addition and pin configuration into one commit.
Changes in v4 -
* Fixed the subject prefix to arm64.
* Updated the pinctrl entries alphabetically.
Changes in v3 -
* Removed aliases and dropped "_1" suffix as suggested by Bjorn.
* Changed pinconfig names.
Changes in v2-
* Updated the binding alphabetically.
* Removed extra comments as suggested by Bhupesh.
* Moved non-removable, no-sd, no-sdio and other properties from
soc to board dts file as suggested by Bhupesh and Konrad.
* Removed extra newlines and leading zeroes as suggested by Konrad.
* Modified sdhc1_opp_table.
* Updated the SDHC node entries alphabetically.
* Moved the status entry at the end.
Komal Bajaj (3):
dt-bindings: mmc: sdhci-msm: Document the QDU1000/QRU1000 compatible
arm64: dts: qcom: qdu1000: Add SDHCI node
arm64: dts: qcom: qdu1000-idp: add SDHCI for emmc
.../devicetree/bindings/mmc/sdhci-msm.yaml | 1 +
arch/arm64/boot/dts/qcom/qdu1000-idp.dts | 23 +++++
arch/arm64/boot/dts/qcom/qdu1000.dtsi | 97 +++++++++++++++++++
3 files changed, 121 insertions(+)
--
2.17.1
Add sdhci node for emmc in qdu1000-idp.
Reviewed-by: Konrad Dybcio <[email protected]>
Signed-off-by: Komal Bajaj <[email protected]>
---
arch/arm64/boot/dts/qcom/qdu1000-idp.dts | 23 +++++++++++++++++++++++
1 file changed, 23 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/qdu1000-idp.dts b/arch/arm64/boot/dts/qcom/qdu1000-idp.dts
index 9e9fd4b8023e..1d22f87fd238 100644
--- a/arch/arm64/boot/dts/qcom/qdu1000-idp.dts
+++ b/arch/arm64/boot/dts/qcom/qdu1000-idp.dts
@@ -448,6 +448,29 @@
status = "okay";
};
+&sdhc {
+ pinctrl-0 = <&sdc_on_state>;
+ pinctrl-1 = <&sdc_off_state>;
+ pinctrl-names = "default", "sleep";
+
+ cap-mmc-hw-reset;
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
+ mmc-hs400-1_8v;
+ mmc-hs400-enhanced-strobe;
+
+ non-removable;
+ no-sd;
+ no-sdio;
+
+ supports-cqe;
+
+ vmmc-supply = <&vreg_l10a_2p95>;
+ vqmmc-supply = <&vreg_l7a_1p8>;
+
+ status = "okay";
+};
+
&uart7 {
status = "okay";
};
--
2.17.1
Add sdhc node for eMMC on QDU1000 and QRU1000 SoCs. Also add
required pins for SDHCI, so that the interface can work reliably.
Reviewed-by: Konrad Dybcio <[email protected]>
Signed-off-by: Komal Bajaj <[email protected]>
---
arch/arm64/boot/dts/qcom/qdu1000.dtsi | 97 +++++++++++++++++++++++++++
1 file changed, 97 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/qdu1000.dtsi b/arch/arm64/boot/dts/qcom/qdu1000.dtsi
index 734438113bba..9f615f3368c2 100644
--- a/arch/arm64/boot/dts/qcom/qdu1000.dtsi
+++ b/arch/arm64/boot/dts/qcom/qdu1000.dtsi
@@ -842,6 +842,53 @@
#hwlock-cells = <1>;
};
+ sdhc: mmc@8804000 {
+ compatible = "qcom,qdu1000-sdhci", "qcom,sdhci-msm-v5";
+ reg = <0x0 0x08804000 0x0 0x1000>,
+ <0x0 0x08805000 0x0 0x1000>;
+ reg-names = "hc", "cqhci";
+
+ interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hc_irq", "pwr_irq";
+
+ clocks = <&gcc GCC_SDCC5_AHB_CLK>,
+ <&gcc GCC_SDCC5_APPS_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "iface",
+ "core",
+ "xo";
+
+ resets = <&gcc GCC_SDCC5_BCR>;
+
+ interconnects = <&system_noc MASTER_SDCC_1 0 &mc_virt SLAVE_EBI1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_SDCC_2 0>;
+ interconnect-names = "sdhc-ddr", "cpu-sdhc";
+ power-domains = <&rpmhpd QDU1000_CX>;
+ operating-points-v2 = <&sdhc1_opp_table>;
+
+ iommus = <&apps_smmu 0x80 0x0>;
+ dma-coherent;
+
+ bus-width = <8>;
+
+ qcom,dll-config = <0x0007642c>;
+ qcom,ddr-config = <0x80040868>;
+
+ status = "disabled";
+
+ sdhc1_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-384000000 {
+ opp-hz = /bits/ 64 <384000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ opp-peak-kBps = <6528000 1652800>;
+ opp-avg-kBps = <400000 0>;
+ };
+ };
+ };
+
pdc: interrupt-controller@b220000 {
compatible = "qcom,qdu1000-pdc", "qcom,pdc";
reg = <0x0 0xb220000 0x0 0x30000>, <0x0 0x174000f0 0x0 0x64>;
@@ -1100,6 +1147,56 @@
pins = "gpio31";
function = "gpio";
};
+
+ sdc_on_state: sdc-on-state {
+ clk-pins {
+ pins = "sdc1_clk";
+ drive-strength = <16>;
+ bias-disable;
+ };
+
+ cmd-pins {
+ pins = "sdc1_cmd";
+ drive-strength = <10>;
+ bias-pull-up;
+ };
+
+ data-pins {
+ pins = "sdc1_data";
+ drive-strength = <10>;
+ bias-pull-up;
+ };
+
+ rclk-pins {
+ pins = "sdc1_rclk";
+ bias-pull-down;
+ };
+ };
+
+ sdc_off_state: sdc-off-state {
+ clk-pins {
+ pins = "sdc1_clk";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ cmd-pins {
+ pins = "sdc1_cmd";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ data-pins {
+ pins = "sdc1_data";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ rclk-pins {
+ pins = "sdc1_rclk";
+ bias-pull-down;
+ };
+ };
};
apps_smmu: iommu@15000000 {
--
2.17.1
On Thu, 1 Jun 2023 16:41:25 +0530, Komal Bajaj wrote:
> Changes in v5 -
> * Combined sdhc node addition and pin configuration into one commit.
>
> Changes in v4 -
> * Fixed the subject prefix to arm64.
> * Updated the pinctrl entries alphabetically.
>
> [...]
Applied, thanks!
[2/3] arm64: dts: qcom: qdu1000: Add SDHCI node
commit: 90c8c4eb4bbb5e2e241fd5286bd43dd30a850b9d
[3/3] arm64: dts: qcom: qdu1000-idp: add SDHCI for emmc
commit: 6901ff9987469fa33d06990463adc8a63f8be5d0
Best regards,
--
Bjorn Andersson <[email protected]>