2023-06-02 08:36:35

by Sricharan Ramabadhran

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Subject: [PATCH V8 0/8] Add minimal boot support for IPQ5018

The IPQ5018 is Qualcomm's 802.11ax SoC for Routers,
Gateways and Access Points.

This series adds minimal board boot support for ipq5018-rdp432-c2 board.

[v8] Changed only in patch 4/8
Fixed Kconfig to add COMPILE_TEST and removed header of.h.
Instead using mod_devicetable.h. Added Linus reviewed-by

[v7] Fixed tz reserved region size in patch 7/8

[v6] Fixed patch [4/8] pinctrl driver for rebase issue.

[v5]
Added Reviewed-by tags from Krzysztof Kozlowski.
Changed patch [6/8] with [1] since its already Acked
Rebased patch [4/8] on top of [2] and fixed other comments
Fixed commit log for patch [7/8]
Fixed comments for patch [2/8]

[1] https://patchwork.kernel.org/project/linux-arm-msm/patch/[email protected]/
[2] https://lore.kernel.org/r/[email protected]

[v4]
Fixed all comments for clocks, schema, dts
Added Reviewed-by tags.

[v3]
Fixed all comments for clocks, schema fixes
Picked up Reviewed-by from Bjorn for pinctrl driver

[v2]
Fixed all comments and rebased for TOT.

Manikanta Mylavarapu (1):
dt-bindings: scm: Add compatible for IPQ5018

Sricharan Ramabadhran (7):
dt-bindings: arm64: Add IPQ5018 clock and reset
clk: qcom: Add Global Clock controller (GCC) driver for IPQ5018
dt-bindings: pinctrl: qcom: Add support for ipq5018
pinctrl: qcom: Add IPQ5018 pinctrl driver
dt-bindings: qcom: Add ipq5018 bindings
arm64: dts: Add ipq5018 SoC and rdp432-c2 board support
arm64: defconfig: Enable IPQ5018 SoC base configs

.../devicetree/bindings/arm/qcom.yaml | 7 +
.../bindings/clock/qcom,ipq5018-gcc.yaml | 63 +
.../bindings/firmware/qcom,scm.yaml | 1 +
.../bindings/pinctrl/qcom,ipq5018-tlmm.yaml | 127 +
arch/arm64/boot/dts/qcom/Makefile | 1 +
.../arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts | 72 +
arch/arm64/boot/dts/qcom/ipq5018.dtsi | 250 ++
arch/arm64/configs/defconfig | 3 +
drivers/clk/qcom/Kconfig | 10 +-
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/gcc-ipq5018.c | 3731 +++++++++++++++++
drivers/pinctrl/qcom/Kconfig | 11 +
drivers/pinctrl/qcom/Makefile | 1 +
drivers/pinctrl/qcom/pinctrl-ipq5018.c | 783 ++++
include/dt-bindings/clock/qcom,gcc-ipq5018.h | 183 +
include/dt-bindings/reset/qcom,gcc-ipq5018.h | 122 +
16 files changed, 5364 insertions(+), 2 deletions(-)
create mode 100644 Documentation/devicetree/bindings/clock/qcom,ipq5018-gcc.yaml
create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,ipq5018-tlmm.yaml
create mode 100644 arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts
create mode 100644 arch/arm64/boot/dts/qcom/ipq5018.dtsi
create mode 100644 drivers/clk/qcom/gcc-ipq5018.c
create mode 100644 drivers/pinctrl/qcom/pinctrl-ipq5018.c
create mode 100644 include/dt-bindings/clock/qcom,gcc-ipq5018.h
create mode 100644 include/dt-bindings/reset/qcom,gcc-ipq5018.h

--
2.34.1



2023-06-02 08:43:31

by Sricharan Ramabadhran

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Subject: [PATCH V8 8/8] arm64: defconfig: Enable IPQ5018 SoC base configs

Enables clk & pinctrl related configs

Reviewed-by: Krzysztof Kozlowski <[email protected]>
Signed-off-by: Sricharan Ramabadhran <[email protected]>
---
arch/arm64/configs/defconfig | 3 +++
1 file changed, 3 insertions(+)

diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 53fb665078db..58fe82ee5b53 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -556,6 +556,7 @@ CONFIG_PINCTRL_IMX8ULP=y
CONFIG_PINCTRL_IMX93=y
CONFIG_PINCTRL_MSM=y
CONFIG_PINCTRL_IPQ8074=y
+CONFIG_PINCTRL_IPQ5018=y
CONFIG_PINCTRL_IPQ5332=y
CONFIG_PINCTRL_IPQ6018=y
CONFIG_PINCTRL_IPQ9574=y
@@ -1165,6 +1166,8 @@ CONFIG_QCOM_CLK_SMD_RPM=y
CONFIG_QCOM_CLK_RPMH=y
CONFIG_IPQ_APSS_6018=y
CONFIG_IPQ_GCC_5332=y
+CONFIG_IPQ_APSS_5018=y
+CONFIG_IPQ_GCC_5018=y
CONFIG_IPQ_GCC_6018=y
CONFIG_IPQ_GCC_8074=y
CONFIG_IPQ_GCC_9574=y
--
2.34.1


2023-06-02 08:45:38

by Sricharan Ramabadhran

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Subject: [PATCH V8 3/8] dt-bindings: pinctrl: qcom: Add support for ipq5018

Add device tree binding Documentation details for ipq5018
pinctrl driver.

Reviewed-by: Krzysztof Kozlowski <[email protected]>
Co-developed-by: Nitheesh Sekar <[email protected]>
Signed-off-by: Nitheesh Sekar <[email protected]>
Co-developed-by: Varadarajan Narayanan <[email protected]>
Signed-off-by: Varadarajan Narayanan <[email protected]>
Signed-off-by: Sricharan Ramabadhran <[email protected]>
---
.../bindings/pinctrl/qcom,ipq5018-tlmm.yaml | 127 ++++++++++++++++++
1 file changed, 127 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,ipq5018-tlmm.yaml

diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,ipq5018-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,ipq5018-tlmm.yaml
new file mode 100644
index 000000000000..fad0118fd521
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/qcom,ipq5018-tlmm.yaml
@@ -0,0 +1,127 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/qcom,ipq5018-tlmm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm IPQ5018 TLMM pin controller
+
+maintainers:
+ - Bjorn Andersson <[email protected]>
+ - Krzysztof Kozlowski <[email protected]>
+
+description:
+ Top Level Mode Multiplexer pin controller in Qualcomm IPQ5018 SoC.
+
+properties:
+ compatible:
+ const: qcom,ipq5018-tlmm
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ interrupt-controller: true
+ "#interrupt-cells": true
+ gpio-controller: true
+ "#gpio-cells": true
+ gpio-ranges: true
+ wakeup-parent: true
+
+ gpio-reserved-ranges:
+ minItems: 1
+ maxItems: 24
+
+ gpio-line-names:
+ maxItems: 47
+
+patternProperties:
+ "-state$":
+ oneOf:
+ - $ref: "#/$defs/qcom-ipq5018-tlmm-state"
+ - patternProperties:
+ "-pins$":
+ $ref: "#/$defs/qcom-ipq5018-tlmm-state"
+ additionalProperties: false
+
+$defs:
+ qcom-ipq5018-tlmm-state:
+ type: object
+ description:
+ Pinctrl node's client devices use subnodes for desired pin configuration.
+ Client device subnodes use below standard properties.
+ $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
+ unevaluatedProperties: false
+
+ properties:
+ pins:
+ description:
+ List of gpio pins affected by the properties specified in this
+ subnode.
+ items:
+ pattern: "^gpio([0-9]|[1-3][0-9]|4[0-6])$"
+ minItems: 1
+ maxItems: 8
+
+ function:
+ description:
+ Specify the alternative function to be configured for the specified
+ pins.
+
+ enum: [ atest_char, audio_pdm0, audio_pdm1, audio_rxbclk, audio_rxd,
+ audio_rxfsync, audio_rxmclk, audio_txbclk, audio_txd,
+ audio_txfsync, audio_txmclk, blsp0_i2c, blsp0_spi, blsp0_uart0,
+ blsp0_uart1, blsp1_i2c0, blsp1_i2c1, blsp1_spi0, blsp1_spi1,
+ blsp1_uart0, blsp1_uart1, blsp1_uart2, blsp2_i2c0, blsp2_i2c1,
+ blsp2_spi, blsp2_spi0, blsp2_spi1, btss, burn0, burn1, cri_trng,
+ cri_trng0, cri_trng1, cxc_clk, cxc_data, dbg_out, eud_gpio,
+ gcc_plltest, gcc_tlmm, gpio, led0, led2, mac0, mac1, mdc, mdio,
+ pcie0_clk, pcie0_wake, pcie1_clk, pcie1_wake, pll_test,
+ prng_rosc, pwm0, pwm1, pwm2, pwm3, qdss_cti_trig_in_a0,
+ qdss_cti_trig_in_a1, qdss_cti_trig_in_b0, qdss_cti_trig_in_b1,
+ qdss_cti_trig_out_a0, qdss_cti_trig_out_a1,
+ qdss_cti_trig_out_b0, qdss_cti_trig_out_b1, qdss_traceclk_a,
+ qdss_traceclk_b, qdss_tracectl_a, qdss_tracectl_b,
+ qdss_tracedata_a, qdss_tracedata_b, qspi_clk, qspi_cs,
+ qspi_data, reset_out, sdc1_clk, sdc1_cmd, sdc1_data, wci_txd,
+ wci_rxd, wsa_swrm, wsi_clk3, wsi_data3, wsis_reset, xfem ]
+
+ required:
+ - pins
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ tlmm: pinctrl@1000000 {
+ compatible = "qcom,ipq5018-tlmm";
+ reg = <0x01000000 0x300000>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&tlmm 0 0 47>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
+
+ uart-w-state {
+ rx-pins {
+ pins = "gpio33";
+ function = "blsp1_uart1";
+ bias-pull-down;
+ };
+
+ tx-pins {
+ pins = "gpio34";
+ function = "blsp1_uart1";
+ bias-pull-down;
+ };
+ };
+ };
+...
--
2.34.1


2023-06-02 08:46:22

by Sricharan Ramabadhran

[permalink] [raw]
Subject: [PATCH V8 5/8] dt-bindings: qcom: Add ipq5018 bindings

Document the new ipq5018 SOC/board device tree bindings.

Reviewed-by: Krzysztof Kozlowski <[email protected]>
Signed-off-by: Sricharan Ramabadhran <[email protected]>
---
Documentation/devicetree/bindings/arm/qcom.yaml | 7 +++++++
1 file changed, 7 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml
index 8302d1ee280d..8026a0c40ef9 100644
--- a/Documentation/devicetree/bindings/arm/qcom.yaml
+++ b/Documentation/devicetree/bindings/arm/qcom.yaml
@@ -30,6 +30,7 @@ description: |
apq8084
apq8096
ipq4018
+ ipq5018
ipq5332
ipq6018
ipq8074
@@ -101,6 +102,7 @@ description: |
hk10-c2
idp
liquid
+ rdp432-c2
mtp
qrd
rb2
@@ -335,6 +337,11 @@ properties:
- qcom,ipq4019-dk04.1-c1
- const: qcom,ipq4019

+ - items:
+ - enum:
+ - qcom,ipq5018-rdp432-c2
+ - const: qcom,ipq5018
+
- items:
- enum:
- qcom,ipq5332-ap-mi01.2
--
2.34.1


2023-06-02 08:46:30

by Sricharan Ramabadhran

[permalink] [raw]
Subject: [PATCH V8 6/8] dt-bindings: scm: Add compatible for IPQ5018

From: Manikanta Mylavarapu <[email protected]>

Add the scm compatible string for IPQ5018 SoC

Acked-by: Krzysztof Kozlowski <[email protected]>
Signed-off-by: Manikanta Mylavarapu <[email protected]>
---
Documentation/devicetree/bindings/firmware/qcom,scm.yaml | 1 +
1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml b/Documentation/devicetree/bindings/firmware/qcom,scm.yaml
index 367d04ad1923..ec5f5c0170b5 100644
--- a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml
+++ b/Documentation/devicetree/bindings/firmware/qcom,scm.yaml
@@ -24,6 +24,7 @@ properties:
- qcom,scm-apq8064
- qcom,scm-apq8084
- qcom,scm-ipq4019
+ - qcom,scm-ipq5018
- qcom,scm-ipq5332
- qcom,scm-ipq6018
- qcom,scm-ipq806x
--
2.34.1