MT8188 have 3 IOMMU HWs. 2 IOMMU HW is for multimedia, and 1 IOMMU HW
is for infra-master, like PCIe.
About the 2 MM IOMMU HW, the connection could be something like this:
IOMMU(VDO) IOMMU(VPP)
| |
SMI_COMMON(VDO) SMI_COMMON(VPP)
--------------- ----------------
| | ... | | ...
larb0 larb2 ... larb1 larb3 ...
INFRA IOMMU does not have SMI, the master connects to IOMMU directly.
Although multiple banks supported in MT8188, we only use one of them,
which means PCIe is put in bank0 of INFRA IOMMU.
So we have two pgtable for MT8188, specifically, these two MM IOMMU HW
share a pgtable while INFRA IOMMU HW use a independent pgtable.
Another change is that we add some SMC command for INFRA master to
enable INFRA IOMMU in ATF considering security concerns.
We also adjust the flow of mtk_iommu_config to reduce indention.
Change in v12:
- Change nothing. Just rebase on v6.4-rc4 and collect AngeloGioacchino's R-b.
change in v11:
https://lore.kernel.org/linux-iommu/[email protected]/
- Just add a new entry in MAINTAINERS from AngeloGioacchino.
change in v10:
https://lore.kernel.org/linux-mediatek/[email protected]/
- Add a Fixes tag for [2/7].
- Rebase on mtk-iommu-dma-range-v7:
https://lore.kernel.org/linux-mediatek/[email protected]/
change since v9:
https://lore.kernel.org/linux-mediatek/[email protected]/
- Move the patch about setting set_dma_mask out from this patchset.
- Add a MAINTAINER patch since the header file was added a prefix "mediatek,"
change since v8:
https://lore.kernel.org/linux-mediatek/[email protected]/
- Base on v6.3-rc1 and mtk-iommu-dma-range-v5:
https://lore.kernel.org/linux-mediatek/[email protected]/
- Add a new patch set_dma_mask about since mt8188 support the PA of pgtable 35bits.
changes since v7:
https://lore.kernel.org/linux-mediatek/[email protected]/
- Base on mtk-iommu-dma-range-v4:
https://lore.kernel.org/linux-mediatek/[email protected]/
- Add a new patch for two IOMMU share pagetable issue.
- Add a new patch for adding iova_region_larb_msk for mt8188.
- Add the comment in the dt-binding header file about larb index.
This is for readable when updating the iova_region_larb_msk.
Since there is something wrong for chengci's mail account when sending
to devicetree mail list, we don't know why. I help send this patchset.
https://lore.kernel.org/linux-mediatek/[email protected]/
changes since v6:
https://lore.kernel.org/linux-mediatek/[email protected]/
- base on tag: next-20221220.
- update commit message of patch[2/4].
changes since v5:
- base on tag: next-20221205.
- add flag PGTABLE_PA_35_EN for all IOMMU in MT8188.
- modify the type of "portid_msk" from "u32" to "unsigned long".
changes since v4:
- base on tag: next-20221018.
- add patch[2/4] to reduce indention by adjust mtk_iommu_config flow.
changes since v3:
- base on tag: next-20220916.
- use license "GPL-2.0-only OR BSD-2-Clause" in bingings head file.
- drop redundant "portid" assignment when configure infra master.
- reduce indentation by using "else if" when config infra master.
- update probe flow about "pericfg" for CFG_IFA_MASTER_IN_ATF.
- drop unused "pericfg_comp_str" in mt8188_data_infra.
- drop words like "This commit/patch".
changes since v2:
- base on tag: next-20220831.
- rename "mt8188-memory-port.h" to "mediatek,mt8188-memory-port.h".
- use dual-license in "mediatek,mt8188-memory-port.h"
- remove unnecessary "()" when define SMI_LARB_ID
changes since v1:
- base on tag: next-20220803.
- adds MT8188 IOMMU support.
Chengci.Xu (5):
dt-bindings: mediatek: mt8188: Add binding for MM & INFRA IOMMU
iommu/mediatek: Fix two IOMMU share pagetable issue
iommu/mediatek: Adjust mtk_iommu_config flow
iommu/mediatek: Add enable IOMMU SMC command for INFRA masters
iommu/mediatek: Add MT8188 IOMMU Support
Yong Wu (2):
iommu/mediatek: mt8188: Add iova_region_larb_msk
MAINTAINERS: iommu/mediatek: Update the header file name
.../bindings/iommu/mediatek,iommu.yaml | 12 +-
MAINTAINERS | 1 +
drivers/iommu/mtk_iommu.c | 151 ++++--
.../memory/mediatek,mt8188-memory-port.h | 489 ++++++++++++++++++
include/soc/mediatek/smi.h | 1 +
5 files changed, 622 insertions(+), 32 deletions(-)
create mode 100644 include/dt-bindings/memory/mediatek,mt8188-memory-port.h
--
2.18.0
From: "Chengci.Xu" <[email protected]>
Prepare for MT8188. In MT8188, the register which enables IOMMU for
INFRA masters are in the secure world for security concerns, therefore we
add a SMC command for INFRA masters to enable IOMMU in ATF.
Signed-off-by: Chengci.Xu <[email protected]>
Signed-off-by: Yong Wu <[email protected]>
Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
---
drivers/iommu/mtk_iommu.c | 32 ++++++++++++++++++++++----------
include/soc/mediatek/smi.h | 1 +
2 files changed, 23 insertions(+), 10 deletions(-)
diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
index 8cff85615d5e..9c89cf894a4d 100644
--- a/drivers/iommu/mtk_iommu.c
+++ b/drivers/iommu/mtk_iommu.c
@@ -3,6 +3,7 @@
* Copyright (c) 2015-2016 MediaTek Inc.
* Author: Yong Wu <[email protected]>
*/
+#include <linux/arm-smccc.h>
#include <linux/bitfield.h>
#include <linux/bug.h>
#include <linux/clk.h>
@@ -27,6 +28,7 @@
#include <linux/slab.h>
#include <linux/spinlock.h>
#include <linux/soc/mediatek/infracfg.h>
+#include <linux/soc/mediatek/mtk_sip_svc.h>
#include <asm/barrier.h>
#include <soc/mediatek/smi.h>
@@ -143,6 +145,7 @@
#define PGTABLE_PA_35_EN BIT(17)
#define TF_PORT_TO_ADDR_MT8173 BIT(18)
#define INT_ID_PORT_WIDTH_6 BIT(19)
+#define CFG_IFA_MASTER_IN_ATF BIT(20)
#define MTK_IOMMU_HAS_FLAG_MASK(pdata, _x, mask) \
((((pdata)->flags) & (mask)) == (_x))
@@ -580,6 +583,7 @@ static int mtk_iommu_config(struct mtk_iommu_data *data, struct device *dev,
struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
const struct mtk_iommu_iova_region *region;
unsigned long portid_msk = 0;
+ struct arm_smccc_res res;
int i, ret = 0;
for (i = 0; i < fwspec->num_ids; ++i) {
@@ -605,17 +609,24 @@ static int mtk_iommu_config(struct mtk_iommu_data *data, struct device *dev,
else
larb_mmu->mmu &= ~portid_msk;
} else if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_INFRA)) {
- /* PCI dev has only one output id, enable the next writing bit for PCIe */
- if (dev_is_pci(dev)) {
- if (fwspec->num_ids != 1) {
- dev_err(dev, "PCI dev can only have one port.\n");
- return -ENODEV;
+ if (MTK_IOMMU_HAS_FLAG(data->plat_data, CFG_IFA_MASTER_IN_ATF)) {
+ arm_smccc_smc(MTK_SIP_KERNEL_IOMMU_CONTROL,
+ IOMMU_ATF_CMD_CONFIG_INFRA_IOMMU,
+ portid_msk, enable, 0, 0, 0, 0, &res);
+ ret = res.a0;
+ } else {
+ /* PCI dev has only one output id, enable the next writing bit for PCIe */
+ if (dev_is_pci(dev)) {
+ if (fwspec->num_ids != 1) {
+ dev_err(dev, "PCI dev can only have one port.\n");
+ return -ENODEV;
+ }
+ portid_msk |= BIT(portid + 1);
}
- portid_msk |= BIT(portid + 1);
- }
- ret = regmap_update_bits(data->pericfg, PERICFG_IOMMU_1,
- (u32)portid_msk, enable ? (u32)portid_msk : 0);
+ ret = regmap_update_bits(data->pericfg, PERICFG_IOMMU_1,
+ (u32)portid_msk, enable ? (u32)portid_msk : 0);
+ }
if (ret)
dev_err(dev, "%s iommu(%s) inframaster 0x%lx fail(%d).\n",
enable ? "enable" : "disable",
@@ -1329,7 +1340,8 @@ static int mtk_iommu_probe(struct platform_device *pdev)
dev_err_probe(dev, ret, "mm dts parse fail\n");
goto out_runtime_disable;
}
- } else if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_INFRA)) {
+ } else if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_INFRA) &&
+ !MTK_IOMMU_HAS_FLAG(data->plat_data, CFG_IFA_MASTER_IN_ATF)) {
p = data->plat_data->pericfg_comp_str;
data->pericfg = syscon_regmap_lookup_by_compatible(p);
if (IS_ERR(data->pericfg)) {
diff --git a/include/soc/mediatek/smi.h b/include/soc/mediatek/smi.h
index dfd8efca5e60..000eb1cf68b7 100644
--- a/include/soc/mediatek/smi.h
+++ b/include/soc/mediatek/smi.h
@@ -13,6 +13,7 @@
enum iommu_atf_cmd {
IOMMU_ATF_CMD_CONFIG_SMI_LARB, /* For mm master to en/disable iommu */
+ IOMMU_ATF_CMD_CONFIG_INFRA_IOMMU, /* For infra master to enable iommu */
IOMMU_ATF_CMD_MAX,
};
--
2.25.1
On 02/06/2023 11:02, Yong Wu wrote:
> Prepare for MT8188. In MT8188, the register which enables IOMMU for
> INFRA masters are in the secure world for security concerns, therefore we
> add a SMC command for INFRA masters to enable IOMMU in ATF.
Reviewed-by: Alexandre Mergnat <[email protected]>
--
Regards,
Alexandre
On Fri, Jun 2, 2023 at 5:03 PM Yong Wu <[email protected]> wrote:
>
> MT8188 have 3 IOMMU HWs. 2 IOMMU HW is for multimedia, and 1 IOMMU HW
> is for infra-master, like PCIe.
>
> About the 2 MM IOMMU HW, the connection could be something like this:
>
> IOMMU(VDO) IOMMU(VPP)
> | |
> SMI_COMMON(VDO) SMI_COMMON(VPP)
> --------------- ----------------
> | | ... | | ...
> larb0 larb2 ... larb1 larb3 ...
>
> INFRA IOMMU does not have SMI, the master connects to IOMMU directly.
>
> Although multiple banks supported in MT8188, we only use one of them,
> which means PCIe is put in bank0 of INFRA IOMMU.
>
> So we have two pgtable for MT8188, specifically, these two MM IOMMU HW
> share a pgtable while INFRA IOMMU HW use a independent pgtable.
>
> Another change is that we add some SMC command for INFRA master to
> enable INFRA IOMMU in ATF considering security concerns.
>
> We also adjust the flow of mtk_iommu_config to reduce indention.
A friendly ping - this series was reviewed, but I'm not sure if it's
still on the radar today.
This can be cleanly applied on top of next-20230725.
To give more confidence, I also tested the basic multimedia and infra
functionalities on my MT8188 with this series, so
Tested-by: Fei Shao <[email protected]>
to the entire v12 series.
Regards,
Fei
On Tue, Aug 01, 2023 at 12:53:29PM +0000, Yong Wu (吴勇) wrote:
> Your A-b always is expected before Joerg applies.
It is time to make some progress on the MTK driver patch flow. I just
applied this series, thanks.