Add AMD Pensando common and Elba SoC specific device nodes
Signed-off-by: Brad Larson <[email protected]>
---
v14 changes:
- Fix dtbs_check l2-cache* property issue by adding required
cache-level and cache-unified properties
- Observed the issue after updating dtschema from 2023.1 to 2023.4
and yamllint from 1.26.3 to 1.30.0
v11 changes:
- Delete reset-names
- Fix spi0 compatible to be specific 'amd,pensando-elba-ctrl'
v9 changes:
- Single node for spi0 system-controller and squash
the reset-controller child into parent
---
arch/arm64/boot/dts/amd/Makefile | 1 +
arch/arm64/boot/dts/amd/elba-16core.dtsi | 197 ++++++++++++++++++
arch/arm64/boot/dts/amd/elba-asic-common.dtsi | 80 +++++++
arch/arm64/boot/dts/amd/elba-asic.dts | 28 +++
arch/arm64/boot/dts/amd/elba-flash-parts.dtsi | 106 ++++++++++
arch/arm64/boot/dts/amd/elba.dtsi | 191 +++++++++++++++++
6 files changed, 603 insertions(+)
create mode 100644 arch/arm64/boot/dts/amd/elba-16core.dtsi
create mode 100644 arch/arm64/boot/dts/amd/elba-asic-common.dtsi
create mode 100644 arch/arm64/boot/dts/amd/elba-asic.dts
create mode 100644 arch/arm64/boot/dts/amd/elba-flash-parts.dtsi
create mode 100644 arch/arm64/boot/dts/amd/elba.dtsi
diff --git a/arch/arm64/boot/dts/amd/Makefile b/arch/arm64/boot/dts/amd/Makefile
index 68103a8b0ef5..8502cc2afbc5 100644
--- a/arch/arm64/boot/dts/amd/Makefile
+++ b/arch/arm64/boot/dts/amd/Makefile
@@ -1,2 +1,3 @@
# SPDX-License-Identifier: GPL-2.0
+dtb-$(CONFIG_ARCH_PENSANDO) += elba-asic.dtb
dtb-$(CONFIG_ARCH_SEATTLE) += amd-overdrive-rev-b0.dtb amd-overdrive-rev-b1.dtb
diff --git a/arch/arm64/boot/dts/amd/elba-16core.dtsi b/arch/arm64/boot/dts/amd/elba-16core.dtsi
new file mode 100644
index 000000000000..f9f9f5fd5f69
--- /dev/null
+++ b/arch/arm64/boot/dts/amd/elba-16core.dtsi
@@ -0,0 +1,197 @@
+// SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
+/*
+ * Copyright 2020-2022 Advanced Micro Devices, Inc.
+ */
+
+/ {
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ cpu-map {
+ cluster0 {
+ core0 { cpu = <&cpu0>; };
+ core1 { cpu = <&cpu1>; };
+ core2 { cpu = <&cpu2>; };
+ core3 { cpu = <&cpu3>; };
+ };
+
+ cluster1 {
+ core0 { cpu = <&cpu4>; };
+ core1 { cpu = <&cpu5>; };
+ core2 { cpu = <&cpu6>; };
+ core3 { cpu = <&cpu7>; };
+ };
+
+ cluster2 {
+ core0 { cpu = <&cpu8>; };
+ core1 { cpu = <&cpu9>; };
+ core2 { cpu = <&cpu10>; };
+ core3 { cpu = <&cpu11>; };
+ };
+
+ cluster3 {
+ core0 { cpu = <&cpu12>; };
+ core1 { cpu = <&cpu13>; };
+ core2 { cpu = <&cpu14>; };
+ core3 { cpu = <&cpu15>; };
+ };
+ };
+
+ /* CLUSTER 0 */
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ reg = <0 0x0>;
+ next-level-cache = <&l2_0>;
+ enable-method = "psci";
+ };
+
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ reg = <0 0x1>;
+ next-level-cache = <&l2_0>;
+ enable-method = "psci";
+ };
+
+ cpu2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ reg = <0 0x2>;
+ next-level-cache = <&l2_0>;
+ enable-method = "psci";
+ };
+
+ cpu3: cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ reg = <0 0x3>;
+ next-level-cache = <&l2_0>;
+ enable-method = "psci";
+ };
+
+ l2_0: l2-cache0 {
+ compatible = "cache";
+ cache-unified;
+ cache-level = <2>;
+ };
+
+ /* CLUSTER 1 */
+ cpu4: cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ reg = <0 0x100>;
+ next-level-cache = <&l2_1>;
+ enable-method = "psci";
+ };
+
+ cpu5: cpu@101 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ reg = <0 0x101>;
+ next-level-cache = <&l2_1>;
+ enable-method = "psci";
+ };
+
+ cpu6: cpu@102 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ reg = <0 0x102>;
+ next-level-cache = <&l2_1>;
+ enable-method = "psci";
+ };
+
+ cpu7: cpu@103 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ reg = <0 0x103>;
+ next-level-cache = <&l2_1>;
+ enable-method = "psci";
+ };
+
+ l2_1: l2-cache1 {
+ compatible = "cache";
+ cache-unified;
+ cache-level = <2>;
+ };
+
+ /* CLUSTER 2 */
+ cpu8: cpu@200 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ reg = <0 0x200>;
+ next-level-cache = <&l2_2>;
+ enable-method = "psci";
+ };
+
+ cpu9: cpu@201 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ reg = <0 0x201>;
+ next-level-cache = <&l2_2>;
+ enable-method = "psci";
+ };
+
+ cpu10: cpu@202 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ reg = <0 0x202>;
+ next-level-cache = <&l2_2>;
+ enable-method = "psci";
+ };
+
+ cpu11: cpu@203 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ reg = <0 0x203>;
+ next-level-cache = <&l2_2>;
+ enable-method = "psci";
+ };
+
+ l2_2: l2-cache2 {
+ compatible = "cache";
+ cache-unified;
+ cache-level = <2>;
+ };
+
+ /* CLUSTER 3 */
+ cpu12: cpu@300 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ reg = <0 0x300>;
+ next-level-cache = <&l2_3>;
+ enable-method = "psci";
+ };
+
+ cpu13: cpu@301 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ reg = <0 0x301>;
+ next-level-cache = <&l2_3>;
+ enable-method = "psci";
+ };
+
+ cpu14: cpu@302 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ reg = <0 0x302>;
+ next-level-cache = <&l2_3>;
+ enable-method = "psci";
+ };
+
+ cpu15: cpu@303 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ reg = <0 0x303>;
+ next-level-cache = <&l2_3>;
+ enable-method = "psci";
+ };
+
+ l2_3: l2-cache3 {
+ compatible = "cache";
+ cache-unified;
+ cache-level = <2>;
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/amd/elba-asic-common.dtsi b/arch/arm64/boot/dts/amd/elba-asic-common.dtsi
new file mode 100644
index 000000000000..1a615788f54e
--- /dev/null
+++ b/arch/arm64/boot/dts/amd/elba-asic-common.dtsi
@@ -0,0 +1,80 @@
+// SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
+/*
+ * Copyright 2020-2022 Advanced Micro Devices, Inc.
+ */
+
+&ahb_clk {
+ clock-frequency = <400000000>;
+};
+
+&emmc_clk {
+ clock-frequency = <200000000>;
+};
+
+&flash_clk {
+ clock-frequency = <400000000>;
+};
+
+&ref_clk {
+ clock-frequency = <156250000>;
+};
+
+&qspi {
+ status = "okay";
+
+ flash0: flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <40000000>;
+ spi-rx-bus-width = <2>;
+ m25p,fast-read;
+ cdns,read-delay = <0>;
+ cdns,tshsl-ns = <0>;
+ cdns,tsd2d-ns = <0>;
+ cdns,tchsh-ns = <0>;
+ cdns,tslch-ns = <0>;
+ };
+};
+
+&gpio0 {
+ status = "okay";
+};
+
+&emmc {
+ bus-width = <8>;
+ cap-mmc-hw-reset;
+ resets = <&rstc 0>;
+ status = "okay";
+};
+
+&wdt0 {
+ status = "okay";
+};
+
+&i2c0 {
+ clock-frequency = <100000>;
+ status = "okay";
+
+ rtc@51 {
+ compatible = "nxp,pcf85263";
+ reg = <0x51>;
+ };
+};
+
+&spi0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ num-cs = <4>;
+ cs-gpios = <0>, <0>, <&porta 1 GPIO_ACTIVE_LOW>,
+ <&porta 7 GPIO_ACTIVE_LOW>;
+ status = "okay";
+
+ rstc: system-controller@0 {
+ compatible = "amd,pensando-elba-ctrl";
+ reg = <0>;
+ spi-max-frequency = <12000000>;
+ interrupt-parent = <&porta>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+ #reset-cells = <1>;
+ };
+};
diff --git a/arch/arm64/boot/dts/amd/elba-asic.dts b/arch/arm64/boot/dts/amd/elba-asic.dts
new file mode 100644
index 000000000000..c3f4da2f7449
--- /dev/null
+++ b/arch/arm64/boot/dts/amd/elba-asic.dts
@@ -0,0 +1,28 @@
+// SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
+/*
+ * Device Tree file for AMD Pensando Elba Board.
+ *
+ * Copyright 2020-2022 Advanced Micro Devices, Inc.
+ */
+
+/dts-v1/;
+
+#include "elba.dtsi"
+#include "elba-16core.dtsi"
+#include "elba-asic-common.dtsi"
+#include "elba-flash-parts.dtsi"
+
+/ {
+ model = "AMD Pensando Elba Board";
+ compatible = "amd,pensando-elba-ortano", "amd,pensando-elba";
+
+ aliases {
+ serial0 = &uart0;
+ spi0 = &spi0;
+ spi1 = &qspi;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
diff --git a/arch/arm64/boot/dts/amd/elba-flash-parts.dtsi b/arch/arm64/boot/dts/amd/elba-flash-parts.dtsi
new file mode 100644
index 000000000000..734893fef2c3
--- /dev/null
+++ b/arch/arm64/boot/dts/amd/elba-flash-parts.dtsi
@@ -0,0 +1,106 @@
+// SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
+/*
+ * Copyright 2020-2022 Advanced Micro Devices, Inc.
+ */
+
+&flash0 {
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ partition@0 {
+ label = "flash";
+ reg = <0x10000 0xfff0000>;
+ };
+
+ partition@f0000 {
+ label = "golduenv";
+ reg = <0xf0000 0x10000>;
+ };
+
+ partition@100000 {
+ label = "boot0";
+ reg = <0x100000 0x80000>;
+ };
+
+ partition@180000 {
+ label = "golduboot";
+ reg = <0x180000 0x200000>;
+ };
+
+ partition@380000 {
+ label = "brdcfg0";
+ reg = <0x380000 0x10000>;
+ };
+
+ partition@390000 {
+ label = "brdcfg1";
+ reg = <0x390000 0x10000>;
+ };
+
+ partition@400000 {
+ label = "goldfw";
+ reg = <0x400000 0x3c00000>;
+ };
+
+ partition@4010000 {
+ label = "fwmap";
+ reg = <0x4010000 0x20000>;
+ };
+
+ partition@4030000 {
+ label = "fwsel";
+ reg = <0x4030000 0x20000>;
+ };
+
+ partition@4090000 {
+ label = "bootlog";
+ reg = <0x4090000 0x20000>;
+ };
+
+ partition@40b0000 {
+ label = "panicbuf";
+ reg = <0x40b0000 0x20000>;
+ };
+
+ partition@40d0000 {
+ label = "uservars";
+ reg = <0x40d0000 0x20000>;
+ };
+
+ partition@4200000 {
+ label = "uboota";
+ reg = <0x4200000 0x400000>;
+ };
+
+ partition@4600000 {
+ label = "ubootb";
+ reg = <0x4600000 0x400000>;
+ };
+
+ partition@4a00000 {
+ label = "mainfwa";
+ reg = <0x4a00000 0x1000000>;
+ };
+
+ partition@5a00000 {
+ label = "mainfwb";
+ reg = <0x5a00000 0x1000000>;
+ };
+
+ partition@6a00000 {
+ label = "diaguboot";
+ reg = <0x6a00000 0x400000>;
+ };
+
+ partition@8000000 {
+ label = "diagfw";
+ reg = <0x8000000 0x7fe0000>;
+ };
+
+ partition@ffe0000 {
+ label = "ubootenv";
+ reg = <0xffe0000 0x10000>;
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/amd/elba.dtsi b/arch/arm64/boot/dts/amd/elba.dtsi
new file mode 100644
index 000000000000..674890cf2a34
--- /dev/null
+++ b/arch/arm64/boot/dts/amd/elba.dtsi
@@ -0,0 +1,191 @@
+// SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
+/*
+ * Copyright 2020-2022 Advanced Micro Devices, Inc.
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include "dt-bindings/interrupt-controller/arm-gic.h"
+
+/ {
+ model = "Elba ASIC Board";
+ compatible = "amd,pensando-elba";
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ dma-coherent;
+
+ ahb_clk: oscillator0 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ };
+
+ emmc_clk: oscillator2 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ };
+
+ flash_clk: oscillator3 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ };
+
+ ref_clk: oscillator4 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ };
+
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
+ };
+
+ pmu {
+ compatible = "arm,cortex-a72-pmu";
+ interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
+ };
+
+ soc: soc {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ i2c0: i2c@400 {
+ compatible = "snps,designware-i2c";
+ reg = <0x0 0x400 0x0 0x100>;
+ clocks = <&ahb_clk>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ i2c-sda-hold-time-ns = <480>;
+ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ wdt0: watchdog@1400 {
+ compatible = "snps,dw-wdt";
+ reg = <0x0 0x1400 0x0 0x100>;
+ clocks = <&ahb_clk>;
+ interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ qspi: spi@2400 {
+ compatible = "amd,pensando-elba-qspi", "cdns,qspi-nor";
+ reg = <0x0 0x2400 0x0 0x400>,
+ <0x0 0x7fff0000 0x0 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&flash_clk>;
+ cdns,fifo-depth = <1024>;
+ cdns,fifo-width = <4>;
+ cdns,trigger-address = <0x7fff0000>;
+ status = "disabled";
+ };
+
+ spi0: spi@2800 {
+ compatible = "amd,pensando-elba-spi";
+ reg = <0x0 0x2800 0x0 0x100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ amd,pensando-elba-syscon = <&syscon>;
+ clocks = <&ahb_clk>;
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ num-cs = <2>;
+ status = "disabled";
+ };
+
+ gpio0: gpio@4000 {
+ compatible = "snps,dw-apb-gpio";
+ reg = <0x0 0x4000 0x0 0x78>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ porta: gpio-port@0 {
+ compatible = "snps,dw-apb-gpio-port";
+ reg = <0>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ ngpios = <8>;
+ interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ interrupt-parent = <&gic>;
+ #interrupt-cells = <2>;
+ };
+
+ portb: gpio-port@1 {
+ compatible = "snps,dw-apb-gpio-port";
+ reg = <1>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ ngpios = <8>;
+ };
+ };
+
+ uart0: serial@4800 {
+ compatible = "ns16550a";
+ reg = <0x0 0x4800 0x0 0x100>;
+ clocks = <&ref_clk>;
+ interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ };
+
+ gic: interrupt-controller@800000 {
+ compatible = "arm,gic-v3";
+ reg = <0x0 0x800000 0x0 0x200000>, /* GICD */
+ <0x0 0xa00000 0x0 0x200000>, /* GICR */
+ <0x0 0x60000000 0x0 0x2000>, /* GICC */
+ <0x0 0x60010000 0x0 0x1000>, /* GICH */
+ <0x0 0x60020000 0x0 0x2000>; /* GICV */
+ #address-cells = <2>;
+ #size-cells = <2>;
+ #interrupt-cells = <3>;
+ ranges;
+ interrupt-controller;
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+
+ /*
+ * Elba specific pre-ITS is enabled using the
+ * existing property socionext,synquacer-pre-its
+ */
+ gic_its: msi-controller@820000 {
+ compatible = "arm,gic-v3-its";
+ reg = <0x0 0x820000 0x0 0x10000>;
+ msi-controller;
+ #msi-cells = <1>;
+ socionext,synquacer-pre-its =
+ <0xc00000 0x1000000>;
+ };
+ };
+
+ emmc: mmc@30440000 {
+ compatible = "amd,pensando-elba-sd4hc", "cdns,sd4hc";
+ reg = <0x0 0x30440000 0x0 0x10000>,
+ <0x0 0x30480044 0x0 0x4>; /* byte-lane ctrl */
+ clocks = <&emmc_clk>;
+ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+ cdns,phy-input-delay-sd-highspeed = <0x4>;
+ cdns,phy-input-delay-legacy = <0x4>;
+ cdns,phy-input-delay-sd-uhs-sdr50 = <0x6>;
+ cdns,phy-input-delay-sd-uhs-ddr50 = <0x16>;
+ mmc-ddr-1_8v;
+ status = "disabled";
+ };
+
+ syscon: syscon@307c0000 {
+ compatible = "amd,pensando-elba-syscon", "syscon";
+ reg = <0x0 0x307c0000 0x0 0x3000>;
+ };
+ };
+};
--
2.17.1
On 15/05/2023 20:16, Brad Larson wrote:
> Add AMD Pensando common and Elba SoC specific device nodes
>
> Signed-off-by: Brad Larson <[email protected]>
> ---
>
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Best regards,
Krzysztof
On 5/15/23 20:16, Brad Larson wrote:
> Add AMD Pensando common and Elba SoC specific device nodes
>
> Signed-off-by: Brad Larson <[email protected]>
> ---
>
> v14 changes:
> - Fix dtbs_check l2-cache* property issue by adding required
> cache-level and cache-unified properties
> - Observed the issue after updating dtschema from 2023.1 to 2023.4
> and yamllint from 1.26.3 to 1.30.0
>
> v11 changes:
> - Delete reset-names
> - Fix spi0 compatible to be specific 'amd,pensando-elba-ctrl'
>
> v9 changes:
> - Single node for spi0 system-controller and squash
> the reset-controller child into parent
>
> ---
> arch/arm64/boot/dts/amd/Makefile | 1 +
> arch/arm64/boot/dts/amd/elba-16core.dtsi | 197 ++++++++++++++++++
> arch/arm64/boot/dts/amd/elba-asic-common.dtsi | 80 +++++++
> arch/arm64/boot/dts/amd/elba-asic.dts | 28 +++
> arch/arm64/boot/dts/amd/elba-flash-parts.dtsi | 106 ++++++++++
> arch/arm64/boot/dts/amd/elba.dtsi | 191 +++++++++++++++++
> 6 files changed, 603 insertions(+)
> create mode 100644 arch/arm64/boot/dts/amd/elba-16core.dtsi
> create mode 100644 arch/arm64/boot/dts/amd/elba-asic-common.dtsi
> create mode 100644 arch/arm64/boot/dts/amd/elba-asic.dts
> create mode 100644 arch/arm64/boot/dts/amd/elba-flash-parts.dtsi
> create mode 100644 arch/arm64/boot/dts/amd/elba.dtsi
>
> diff --git a/arch/arm64/boot/dts/amd/Makefile b/arch/arm64/boot/dts/amd/Makefile
> index 68103a8b0ef5..8502cc2afbc5 100644
> --- a/arch/arm64/boot/dts/amd/Makefile
> +++ b/arch/arm64/boot/dts/amd/Makefile
> @@ -1,2 +1,3 @@
> # SPDX-License-Identifier: GPL-2.0
> +dtb-$(CONFIG_ARCH_PENSANDO) += elba-asic.dtb
> dtb-$(CONFIG_ARCH_SEATTLE) += amd-overdrive-rev-b0.dtb amd-overdrive-rev-b1.dtb
> diff --git a/arch/arm64/boot/dts/amd/elba-16core.dtsi b/arch/arm64/boot/dts/amd/elba-16core.dtsi
> new file mode 100644
> index 000000000000..f9f9f5fd5f69
> --- /dev/null
> +++ b/arch/arm64/boot/dts/amd/elba-16core.dtsi
> @@ -0,0 +1,197 @@
> +// SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
> +/*
> + * Copyright 2020-2022 Advanced Micro Devices, Inc.
2023 and the same below.
> + */
> +
> +/ {
> + cpus {
> + #address-cells = <2>;
> + #size-cells = <0>;
> +
> + cpu-map {
> + cluster0 {
> + core0 { cpu = <&cpu0>; };
> + core1 { cpu = <&cpu1>; };
> + core2 { cpu = <&cpu2>; };
> + core3 { cpu = <&cpu3>; };
> + };
> +
> + cluster1 {
> + core0 { cpu = <&cpu4>; };
> + core1 { cpu = <&cpu5>; };
> + core2 { cpu = <&cpu6>; };
> + core3 { cpu = <&cpu7>; };
> + };
> +
> + cluster2 {
> + core0 { cpu = <&cpu8>; };
> + core1 { cpu = <&cpu9>; };
> + core2 { cpu = <&cpu10>; };
> + core3 { cpu = <&cpu11>; };
> + };
> +
> + cluster3 {
> + core0 { cpu = <&cpu12>; };
> + core1 { cpu = <&cpu13>; };
> + core2 { cpu = <&cpu14>; };
> + core3 { cpu = <&cpu15>; };
> + };
> + };
> +
> + /* CLUSTER 0 */
> + cpu0: cpu@0 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a72";
> + reg = <0 0x0>;
Do you really need 2/0 split here. The first cell is 0 anyway.
> + next-level-cache = <&l2_0>;
> + enable-method = "psci";
> + };
> +
> + cpu1: cpu@1 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a72";
> + reg = <0 0x1>;
> + next-level-cache = <&l2_0>;
> + enable-method = "psci";
> + };
> +
> + cpu2: cpu@2 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a72";
> + reg = <0 0x2>;
> + next-level-cache = <&l2_0>;
> + enable-method = "psci";
> + };
> +
> + cpu3: cpu@3 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a72";
> + reg = <0 0x3>;
> + next-level-cache = <&l2_0>;
> + enable-method = "psci";
> + };
> +
> + l2_0: l2-cache0 {
> + compatible = "cache";
> + cache-unified;
> + cache-level = <2>;
> + };
> +
> + /* CLUSTER 1 */
> + cpu4: cpu@100 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a72";
> + reg = <0 0x100>;
> + next-level-cache = <&l2_1>;
> + enable-method = "psci";
> + };
> +
> + cpu5: cpu@101 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a72";
> + reg = <0 0x101>;
> + next-level-cache = <&l2_1>;
> + enable-method = "psci";
> + };
> +
> + cpu6: cpu@102 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a72";
> + reg = <0 0x102>;
> + next-level-cache = <&l2_1>;
> + enable-method = "psci";
> + };
> +
> + cpu7: cpu@103 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a72";
> + reg = <0 0x103>;
> + next-level-cache = <&l2_1>;
> + enable-method = "psci";
> + };
> +
> + l2_1: l2-cache1 {
> + compatible = "cache";
> + cache-unified;
> + cache-level = <2>;
> + };
> +
> + /* CLUSTER 2 */
> + cpu8: cpu@200 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a72";
> + reg = <0 0x200>;
> + next-level-cache = <&l2_2>;
> + enable-method = "psci";
> + };
> +
> + cpu9: cpu@201 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a72";
> + reg = <0 0x201>;
> + next-level-cache = <&l2_2>;
> + enable-method = "psci";
> + };
> +
> + cpu10: cpu@202 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a72";
> + reg = <0 0x202>;
> + next-level-cache = <&l2_2>;
> + enable-method = "psci";
> + };
> +
> + cpu11: cpu@203 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a72";
> + reg = <0 0x203>;
> + next-level-cache = <&l2_2>;
> + enable-method = "psci";
> + };
> +
> + l2_2: l2-cache2 {
> + compatible = "cache";
> + cache-unified;
> + cache-level = <2>;
> + };
> +
> + /* CLUSTER 3 */
> + cpu12: cpu@300 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a72";
> + reg = <0 0x300>;
> + next-level-cache = <&l2_3>;
> + enable-method = "psci";
> + };
> +
> + cpu13: cpu@301 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a72";
> + reg = <0 0x301>;
> + next-level-cache = <&l2_3>;
> + enable-method = "psci";
> + };
> +
> + cpu14: cpu@302 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a72";
> + reg = <0 0x302>;
> + next-level-cache = <&l2_3>;
> + enable-method = "psci";
> + };
> +
> + cpu15: cpu@303 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a72";
> + reg = <0 0x303>;
> + next-level-cache = <&l2_3>;
> + enable-method = "psci";
> + };
> +
> + l2_3: l2-cache3 {
> + compatible = "cache";
> + cache-unified;
> + cache-level = <2>;
> + };
> + };
> +};
> diff --git a/arch/arm64/boot/dts/amd/elba-asic-common.dtsi b/arch/arm64/boot/dts/amd/elba-asic-common.dtsi
> new file mode 100644
> index 000000000000..1a615788f54e
> --- /dev/null
> +++ b/arch/arm64/boot/dts/amd/elba-asic-common.dtsi
> @@ -0,0 +1,80 @@
> +// SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
> +/*
> + * Copyright 2020-2022 Advanced Micro Devices, Inc.
> + */
> +
> +&ahb_clk {
> + clock-frequency = <400000000>;
> +};
> +
> +&emmc_clk {
> + clock-frequency = <200000000>;
> +};
> +
> +&flash_clk {
> + clock-frequency = <400000000>;
> +};
> +
> +&ref_clk {
> + clock-frequency = <156250000>;
> +};
> +
> +&qspi {
> + status = "okay";
> +
> + flash0: flash@0 {
> + compatible = "jedec,spi-nor";
> + reg = <0>;
> + spi-max-frequency = <40000000>;
> + spi-rx-bus-width = <2>;
> + m25p,fast-read;
> + cdns,read-delay = <0>;
> + cdns,tshsl-ns = <0>;
> + cdns,tsd2d-ns = <0>;
> + cdns,tchsh-ns = <0>;
> + cdns,tslch-ns = <0>;
> + };
> +};
> +
> +&gpio0 {
> + status = "okay";
> +};
> +
> +&emmc {
> + bus-width = <8>;
> + cap-mmc-hw-reset;
> + resets = <&rstc 0>;
> + status = "okay";
> +};
> +
> +&wdt0 {
> + status = "okay";
> +};
> +
> +&i2c0 {
> + clock-frequency = <100000>;
> + status = "okay";
> +
> + rtc@51 {
> + compatible = "nxp,pcf85263";
> + reg = <0x51>;
> + };
> +};
> +
> +&spi0 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + num-cs = <4>;
> + cs-gpios = <0>, <0>, <&porta 1 GPIO_ACTIVE_LOW>,
> + <&porta 7 GPIO_ACTIVE_LOW>;
> + status = "okay";
> +
> + rstc: system-controller@0 {
> + compatible = "amd,pensando-elba-ctrl";
> + reg = <0>;
> + spi-max-frequency = <12000000>;
> + interrupt-parent = <&porta>;
> + interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
> + #reset-cells = <1>;
> + };
> +};
> diff --git a/arch/arm64/boot/dts/amd/elba-asic.dts b/arch/arm64/boot/dts/amd/elba-asic.dts
> new file mode 100644
> index 000000000000..c3f4da2f7449
> --- /dev/null
> +++ b/arch/arm64/boot/dts/amd/elba-asic.dts
> @@ -0,0 +1,28 @@
> +// SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
> +/*
> + * Device Tree file for AMD Pensando Elba Board.
> + *
> + * Copyright 2020-2022 Advanced Micro Devices, Inc.
> + */
> +
> +/dts-v1/;
> +
> +#include "elba.dtsi"
> +#include "elba-16core.dtsi"
> +#include "elba-asic-common.dtsi"
> +#include "elba-flash-parts.dtsi"
> +
> +/ {
> + model = "AMD Pensando Elba Board";
> + compatible = "amd,pensando-elba-ortano", "amd,pensando-elba";
> +
> + aliases {
> + serial0 = &uart0;
> + spi0 = &spi0;
> + spi1 = &qspi;
> + };
> +
> + chosen {
> + stdout-path = "serial0:115200n8";
> + };
> +};
> diff --git a/arch/arm64/boot/dts/amd/elba-flash-parts.dtsi b/arch/arm64/boot/dts/amd/elba-flash-parts.dtsi
> new file mode 100644
> index 000000000000..734893fef2c3
> --- /dev/null
> +++ b/arch/arm64/boot/dts/amd/elba-flash-parts.dtsi
> @@ -0,0 +1,106 @@
> +// SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
> +/*
> + * Copyright 2020-2022 Advanced Micro Devices, Inc.
> + */
> +
> +&flash0 {
> + partitions {
> + compatible = "fixed-partitions";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + partition@0 {
> + label = "flash";
> + reg = <0x10000 0xfff0000>;
This doesn't fit with partition@0 above.
Also size is weird.
> + };
> +
> + partition@f0000 {
> + label = "golduenv";
> + reg = <0xf0000 0x10000>;
> + };
> +
> + partition@100000 {
> + label = "boot0";
> + reg = <0x100000 0x80000>;
> + };
> +
> + partition@180000 {
> + label = "golduboot";
> + reg = <0x180000 0x200000>;
> + };
> +
> + partition@380000 {
> + label = "brdcfg0";
> + reg = <0x380000 0x10000>;
> + };
> +
> + partition@390000 {
> + label = "brdcfg1";
> + reg = <0x390000 0x10000>;
> + };
> +
> + partition@400000 {
> + label = "goldfw";
> + reg = <0x400000 0x3c00000>;
This size looks weird.
> + };
> +
> + partition@4010000 {
> + label = "fwmap";
> + reg = <0x4010000 0x20000>;
> + };
> +
> + partition@4030000 {
> + label = "fwsel";
> + reg = <0x4030000 0x20000>;
> + };
> +
> + partition@4090000 {
> + label = "bootlog";
> + reg = <0x4090000 0x20000>;
> + };
> +
> + partition@40b0000 {
> + label = "panicbuf";
> + reg = <0x40b0000 0x20000>;
> + };
> +
> + partition@40d0000 {
> + label = "uservars";
> + reg = <0x40d0000 0x20000>;
> + };
> +
> + partition@4200000 {
> + label = "uboota";
> + reg = <0x4200000 0x400000>;
> + };
> +
> + partition@4600000 {
> + label = "ubootb";
> + reg = <0x4600000 0x400000>;
> + };
> +
> + partition@4a00000 {
> + label = "mainfwa";
> + reg = <0x4a00000 0x1000000>;
> + };
> +
> + partition@5a00000 {
> + label = "mainfwb";
> + reg = <0x5a00000 0x1000000>;
> + };
> +
> + partition@6a00000 {
> + label = "diaguboot";
> + reg = <0x6a00000 0x400000>;
> + };
> +
here is gap
> + partition@8000000 {
> + label = "diagfw";
> + reg = <0x8000000 0x7fe0000>;
> + };
> +
> + partition@ffe0000 {
> + label = "ubootenv";
> + reg = <0xffe0000 0x10000>;
> + };
And this is missing space description.
Thanks,
Michal
Hi Michal,
Thanks for reviewing the patch.
On 5/16/23 09:54, Michal Simek wrote:
> On 5/15/23 20:16, Brad Larson wrote:
>> Add AMD Pensando common and Elba SoC specific device nodes
>>
>> Signed-off-by: Brad Larson <[email protected]>
>> ---
>>
>> v14 changes:
>> - Fix dtbs_check l2-cache* property issue by adding required
>> cache-level and cache-unified properties
>> - Observed the issue after updating dtschema from 2023.1 to 2023.4
>> and yamllint from 1.26.3 to 1.30.0
>>
>> v11 changes:
>> - Delete reset-names
>> - Fix spi0 compatible to be specific 'amd,pensando-elba-ctrl'
>>
>> v9 changes:
>> - Single node for spi0 system-controller and squash
>> the reset-controller child into parent
>>
>> ---
>> arch/arm64/boot/dts/amd/Makefile | 1 +
>> arch/arm64/boot/dts/amd/elba-16core.dtsi | 197 ++++++++++++++++++
>> arch/arm64/boot/dts/amd/elba-asic-common.dtsi | 80 +++++++
>> arch/arm64/boot/dts/amd/elba-asic.dts | 28 +++
>> arch/arm64/boot/dts/amd/elba-flash-parts.dtsi | 106 ++++++++++
>> arch/arm64/boot/dts/amd/elba.dtsi | 191 +++++++++++++++++
>> 6 files changed, 603 insertions(+)
>> create mode 100644 arch/arm64/boot/dts/amd/elba-16core.dtsi
>> create mode 100644 arch/arm64/boot/dts/amd/elba-asic-common.dtsi
>> create mode 100644 arch/arm64/boot/dts/amd/elba-asic.dts
>> create mode 100644 arch/arm64/boot/dts/amd/elba-flash-parts.dtsi
>> create mode 100644 arch/arm64/boot/dts/amd/elba.dtsi
>>
>> diff --git a/arch/arm64/boot/dts/amd/Makefile b/arch/arm64/boot/dts/amd/Makefile
>> index 68103a8b0ef5..8502cc2afbc5 100644
>> --- a/arch/arm64/boot/dts/amd/Makefile
>> +++ b/arch/arm64/boot/dts/amd/Makefile
>> @@ -1,2 +1,3 @@
>> # SPDX-License-Identifier: GPL-2.0
>> +dtb-$(CONFIG_ARCH_PENSANDO) += elba-asic.dtb
>> dtb-$(CONFIG_ARCH_SEATTLE) += amd-overdrive-rev-b0.dtb amd-overdrive-rev-b1.dtb
>> diff --git a/arch/arm64/boot/dts/amd/elba-16core.dtsi b/arch/arm64/boot/dts/amd/elba-16core.dtsi
>> new file mode 100644
>> index 000000000000..f9f9f5fd5f69
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/amd/elba-16core.dtsi
>> @@ -0,0 +1,197 @@
>> +// SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
>> +/*
>> + * Copyright 2020-2022 Advanced Micro Devices, Inc.
>
> 2023 and the same below.
I'll update the copyright in the next submit
>> + */
>> +
>> +/ {
>> + cpus {
>> + #address-cells = <2>;
>> + #size-cells = <0>;
>> +
>> + cpu-map {
>> + cluster0 {
>> + core0 { cpu = <&cpu0>; };
>> + core1 { cpu = <&cpu1>; };
>> + core2 { cpu = <&cpu2>; };
>> + core3 { cpu = <&cpu3>; };
>> + };
>> +
>> + cluster1 {
>> + core0 { cpu = <&cpu4>; };
>> + core1 { cpu = <&cpu5>; };
>> + core2 { cpu = <&cpu6>; };
>> + core3 { cpu = <&cpu7>; };
>> + };
>> +
>> + cluster2 {
>> + core0 { cpu = <&cpu8>; };
>> + core1 { cpu = <&cpu9>; };
>> + core2 { cpu = <&cpu10>; };
>> + core3 { cpu = <&cpu11>; };
>> + };
>> +
>> + cluster3 {
>> + core0 { cpu = <&cpu12>; };
>> + core1 { cpu = <&cpu13>; };
>> + core2 { cpu = <&cpu14>; };
>> + core3 { cpu = <&cpu15>; };
>> + };
>> + };
>> +
>> + /* CLUSTER 0 */
>> + cpu0: cpu@0 {
>> + device_type = "cpu";
>> + compatible = "arm,cortex-a72";
>> + reg = <0 0x0>;
>
> Do you really need 2/0 split here. The first cell is 0 anyway.
Yes following 64-bit system definition
...
>> diff --git a/arch/arm64/boot/dts/amd/elba-flash-parts.dtsi b/arch/arm64/boot/dts/amd/elba-flash-parts.dtsi
>> new file mode 100644
>> index 000000000000..734893fef2c3
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/amd/elba-flash-parts.dtsi
>> @@ -0,0 +1,106 @@
>> +// SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
>> +/*
>> + * Copyright 2020-2022 Advanced Micro Devices, Inc.
>> + */
>> +
>> +&flash0 {
0xf0000>> + partitions {
>> + compatible = "fixed-partitions";
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + partition@0 {
>> + label = "flash";
>> + reg = <0x10000 0xfff0000>;
>
> This doesn't fit with partition@0 above.
> Also size is weird.
This is intended to not expose sector 0.
>> + };
>> +
>> + partition@f0000 {
>> + label = "golduenv";
>> + reg = <0xf0000 0x10000>;
>> + };
>> +
>> + partition@100000 {
>> + label = "boot0";
>> + reg = <0x100000 0x80000>;
>> + };
>> +
>> + partition@180000 {
>> + label = "golduboot";
>> + reg = <0x180000 0x200000>;
>> + };
>> +
>> + partition@380000 {
>> + label = "brdcfg0";
>> + reg = <0x380000 0x10000>;
>> + };
>> +
>> + partition@390000 {
>> + label = "brdcfg1";
>> + reg = <0x390000 0x10000>;
>> + };
>> +
>> + partition@400000 {
>> + label = "goldfw";
>> + reg = <0x400000 0x3c00000>;
>
> This size looks weird.
It's the allocated size for this firmware component.
>> + };
>> +
>> + partition@4010000 {
>> + label = "fwmap";
>> + reg = <0x4010000 0x20000>;
>> + };
>> +
>> + partition@4030000 {
>> + label = "fwsel";
>> + reg = <0x4030000 0x20000>;
>> + };
>> +
>> + partition@4090000 {
>> + label = "bootlog";
>> + reg = <0x4090000 0x20000>;
>> + };
>> +
>> + partition@40b0000 {
>> + label = "panicbuf";
>> + reg = <0x40b0000 0x20000>;
>> + };
>> +
>> + partition@40d0000 {
>> + label = "uservars";
>> + reg = <0x40d0000 0x20000>;
>> + };
>> +
>> + partition@4200000 {
>> + label = "uboota";
>> + reg = <0x4200000 0x400000>;
>> + };
>> +
>> + partition@4600000 {
>> + label = "ubootb";
>> + reg = <0x4600000 0x400000>;
>> + };
>> +
>> + partition@4a00000 {
>> + label = "mainfwa";
>> + reg = <0x4a00000 0x1000000>;
>> + };
>> +
>> + partition@5a00000 {
>> + label = "mainfwb";
>> + reg = <0x5a00000 0x1000000>;
>> + };
>> +
>> + partition@6a00000 {
>> + label = "diaguboot";
>> + reg = <0x6a00000 0x400000>;
>> + };
>> +
>
> here is gap
This is intentional for unallocated space. I'll put in a 'spare' partition.
>> + partition@8000000 {
>> + label = "diagfw";
>> + reg = <0x8000000 0x7fe0000>;
>> + };
>> +
>> + partition@ffe0000 {
>> + label = "ubootenv";
>> + reg = <0xffe0000 0x10000>;
>> + };
>
> And this is missing space description.
space description?
Regards,
Brad
Hi Brad,
On Tue, May 23, 2023 at 9:30 PM Brad Larson <[email protected]> wrote:
> On 5/16/23 09:54, Michal Simek wrote:
> > On 5/15/23 20:16, Brad Larson wrote:
> >> --- /dev/null
> >> +++ b/arch/arm64/boot/dts/amd/elba-16core.dtsi
> >> @@ -0,0 +1,197 @@
> >> +// SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
> >> +/*
> >> + * Copyright 2020-2022 Advanced Micro Devices, Inc.
> >
> > 2023 and the same below.
>
> I'll update the copyright in the next submit
Did you make any substantial changes in 2023?
> >> + */
> >> +
> >> +/ {
> >> + cpus {
> >> + #address-cells = <2>;
> >> + #size-cells = <0>;
> >> +
> >> + cpu-map {
> >> + cluster0 {
> >> + core0 { cpu = <&cpu0>; };
> >> + core1 { cpu = <&cpu1>; };
> >> + core2 { cpu = <&cpu2>; };
> >> + core3 { cpu = <&cpu3>; };
> >> + };
> >> +
> >> + cluster1 {
> >> + core0 { cpu = <&cpu4>; };
> >> + core1 { cpu = <&cpu5>; };
> >> + core2 { cpu = <&cpu6>; };
> >> + core3 { cpu = <&cpu7>; };
> >> + };
> >> +
> >> + cluster2 {
> >> + core0 { cpu = <&cpu8>; };
> >> + core1 { cpu = <&cpu9>; };
> >> + core2 { cpu = <&cpu10>; };
> >> + core3 { cpu = <&cpu11>; };
> >> + };
> >> +
> >> + cluster3 {
> >> + core0 { cpu = <&cpu12>; };
> >> + core1 { cpu = <&cpu13>; };
> >> + core2 { cpu = <&cpu14>; };
> >> + core3 { cpu = <&cpu15>; };
> >> + };
> >> + };
> >> +
> >> + /* CLUSTER 0 */
> >> + cpu0: cpu@0 {
> >> + device_type = "cpu";
> >> + compatible = "arm,cortex-a72";
> >> + reg = <0 0x0>;
> >
> > Do you really need 2/0 split here. The first cell is 0 anyway.
>
> Yes following 64-bit system definition
You mean for the 64-bit main address space?
The CPU address space under /cpus is unrelated.
> >> +++ b/arch/arm64/boot/dts/amd/elba-flash-parts.dtsi
> >> @@ -0,0 +1,106 @@
> >> +// SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
> >> +/*
> >> + * Copyright 2020-2022 Advanced Micro Devices, Inc.
> >> + */
> >> +
> >> +&flash0 {
> 0xf0000>> + partitions {
> >> + compatible = "fixed-partitions";
> >> + #address-cells = <1>;
> >> + #size-cells = <1>;
> >> + partition@0 {
> >> + label = "flash";
> >> + reg = <0x10000 0xfff0000>;
> >
> > This doesn't fit with partition@0 above.
> > Also size is weird.
>
> This is intended to not expose sector 0.
The unit address should still match the first reg entry
=> partition@10000.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Hi Geert,
On Wed, May 24, 2023 at 13:52 Geert Uytterhoeven <[email protected]> wrote:
> On Tue, May 23, 2023 at 9:30â¯PM Brad Larson <[email protected]> wrote:
>> On 5/16/23 09:54, Michal Simek wrote:
>> > On 5/15/23 20:16, Brad Larson wrote:
>> >> --- /dev/null
>> >> +++ b/arch/arm64/boot/dts/amd/elba-16core.dtsi
>> >> @@ -0,0 +1,197 @@
>> >> +// SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
>> >> +/*
>> >> + * Copyright 2020-2022 Advanced Micro Devices, Inc.
>> >
>> > 2023 and the same below.
>>
>> I'll update the copyright in the next submit
>
> Did you make any substantial changes in 2023?
Yes, additional properties were added to l2-cache*
>> >> + */
>> >> +
>> >> +/ {
>> >> + cpus {
>> >> + #address-cells = <2>;
>> >> + #size-cells = <0>;
>> >> +
>> >> + cpu-map {
>> >> + cluster0 {
>> >> + core0 { cpu = <&cpu0>; };
>> >> + core1 { cpu = <&cpu1>; };
>> >> + core2 { cpu = <&cpu2>; };
>> >> + core3 { cpu = <&cpu3>; };
>> >> + };
>> >> +
>> >> + cluster1 {
>> >> + core0 { cpu = <&cpu4>; };
>> >> + core1 { cpu = <&cpu5>; };
>> >> + core2 { cpu = <&cpu6>; };
>> >> + core3 { cpu = <&cpu7>; };
>> >> + };
>> >> +
>> >> + cluster2 {
>> >> + core0 { cpu = <&cpu8>; };
>> >> + core1 { cpu = <&cpu9>; };
>> >> + core2 { cpu = <&cpu10>; };
>> >> + core3 { cpu = <&cpu11>; };
>> >> + };
>> >> +
>> >> + cluster3 {
>> >> + core0 { cpu = <&cpu12>; };
>> >> + core1 { cpu = <&cpu13>; };
>> >> + core2 { cpu = <&cpu14>; };
>> >> + core3 { cpu = <&cpu15>; };
>> >> + };
>> >> + };
>> >> +
>> >> + /* CLUSTER 0 */
>> >> + cpu0: cpu@0 {
>> >> + device_type = "cpu";
>> >> + compatible = "arm,cortex-a72";
>> >> + reg = <0 0x0>;
>> >
>> > Do you really need 2/0 split here. The first cell is 0 anyway.
>>
>> Yes following 64-bit system definition
>
> You mean for the 64-bit main address space?
> The CPU address space under /cpus is unrelated.
Yes, the reg prop for this node is CPU/threads per dt spec. Checked the history and
the Elba dt was derived from socionext for these nodes and this is how those device
trees are configured along with over a dozen other devices. I changed to
address-cells = <1> and dropped the leading zero from all cpu* reg<> and booting
the system I'm observing no change. Looking in drivers/of I'm not seeing where
cpu*/reg is read and used, any recommendation?
>> >> +++ b/arch/arm64/boot/dts/amd/elba-flash-parts.dtsi
>> >> @@ -0,0 +1,106 @@
>> >> +// SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
>> >> +/*
>> >> + * Copyright 2020-2022 Advanced Micro Devices, Inc.
>> >> + */
>> >> +
>> >> +&flash0 {
>> 0xf0000>> + partitions {
>> >> + compatible = "fixed-partitions";
>> >> + #address-cells = <1>;
>> >> + #size-cells = <1>;
>> >> + partition@0 {
>> >> + label = "flash";
>> >> + reg = <0x10000 0xfff0000>;
>> >
>> > This doesn't fit with partition@0 above.
>> > Also size is weird.
>>
>> This is intended to not expose sector 0.
>
> The unit address should still match the first reg entry
> => partition@10000.
Changed to this:
partition@0 {
label = "rsvd";
reg = <0x0 0x10000>;
read-only;
};
partition@10000 {
label = "flash";
reg = <0x10000 0xfff0000>;
};
Regards,
Brad
Hi Brad,
On Wed, May 31, 2023 at 12:04 AM Brad Larson <[email protected]> wrote:
> On Wed, May 24, 2023 at 13:52 Geert Uytterhoeven <[email protected]> wrote:
> > On Tue, May 23, 2023 at 9:30 PM Brad Larson <[email protected]> wrote:
> >> On 5/16/23 09:54, Michal Simek wrote:
> >> > On 5/15/23 20:16, Brad Larson wrote:
> >> >> + */
> >> >> +
> >> >> +/ {
> >> >> + cpus {
> >> >> + #address-cells = <2>;
> >> >> + #size-cells = <0>;
> >> >> +
> >> >> + cpu-map {
> >> >> + cluster0 {
> >> >> + core0 { cpu = <&cpu0>; };
> >> >> + core1 { cpu = <&cpu1>; };
> >> >> + core2 { cpu = <&cpu2>; };
> >> >> + core3 { cpu = <&cpu3>; };
> >> >> + };
> >> >> +
> >> >> + cluster1 {
> >> >> + core0 { cpu = <&cpu4>; };
> >> >> + core1 { cpu = <&cpu5>; };
> >> >> + core2 { cpu = <&cpu6>; };
> >> >> + core3 { cpu = <&cpu7>; };
> >> >> + };
> >> >> +
> >> >> + cluster2 {
> >> >> + core0 { cpu = <&cpu8>; };
> >> >> + core1 { cpu = <&cpu9>; };
> >> >> + core2 { cpu = <&cpu10>; };
> >> >> + core3 { cpu = <&cpu11>; };
> >> >> + };
> >> >> +
> >> >> + cluster3 {
> >> >> + core0 { cpu = <&cpu12>; };
> >> >> + core1 { cpu = <&cpu13>; };
> >> >> + core2 { cpu = <&cpu14>; };
> >> >> + core3 { cpu = <&cpu15>; };
> >> >> + };
> >> >> + };
> >> >> +
> >> >> + /* CLUSTER 0 */
> >> >> + cpu0: cpu@0 {
> >> >> + device_type = "cpu";
> >> >> + compatible = "arm,cortex-a72";
> >> >> + reg = <0 0x0>;
> >> >
> >> > Do you really need 2/0 split here. The first cell is 0 anyway.
> >>
> >> Yes following 64-bit system definition
> >
> > You mean for the 64-bit main address space?
> > The CPU address space under /cpus is unrelated.
>
> Yes, the reg prop for this node is CPU/threads per dt spec. Checked the history and
> the Elba dt was derived from socionext for these nodes and this is how those device
> trees are configured along with over a dozen other devices. I changed to
> address-cells = <1> and dropped the leading zero from all cpu* reg<> and booting
> the system I'm observing no change. Looking in drivers/of I'm not seeing where
> cpu*/reg is read and used, any recommendation?
drivers/of/cpu.c
Looks like there are lots of DTS files that use #address-cells = <2> for
CPU nodes :-(
git grep -w -A1 cpus -- "*dts*" | grep address-cells | grep "<2>"
I would use <1> is the first cell is always zero...
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Hi Geert,
On Wed, May 31, 2023 at 15:09 Geert Uytterhoeven <[email protected]> wrote:
> On Wed, May 31, 2023 at 12:04 AM Brad Larson <[email protected]> wrote:
>> On Wed, May 24, 2023 at 13:52 Geert Uytterhoeven <[email protected]> wrote:
>> > On Tue, May 23, 2023 at 9:30 PM Brad Larson <[email protected]> wrote:
>> >> On 5/16/23 09:54, Michal Simek wrote:
>> >> > On 5/15/23 20:16, Brad Larson wrote:
...
>> >> >> + /* CLUSTER 0 */
>> >> >> + cpu0: cpu@0 {
>> >> >> + device_type = "cpu";
>> >> >> + compatible = "arm,cortex-a72";
>> >> >> + reg = <0 0x0>;
>> >> >
>> >> > Do you really need 2/0 split here. The first cell is 0 anyway.
>> >>
>> >> Yes following 64-bit system definition
>> >
>> > You mean for the 64-bit main address space?
>> > The CPU address space under /cpus is unrelated.
>>
>> Yes, the reg prop for this node is CPU/threads per dt spec. Checked the history and
>> the Elba dt was derived from socionext for these nodes and this is how those device
>> trees are configured along with over a dozen other devices. I changed to
>> address-cells = <1> and dropped the leading zero from all cpu* reg<> and booting
>> the system I'm observing no change. Looking in drivers/of I'm not seeing where
>> cpu*/reg is read and used, any recommendation?
>
> drivers/of/cpu.c
>
> Looks like there are lots of DTS files that use #address-cells = <2> for
> CPU nodes :-(
>
> git grep -w -A1 cpus -- "*dts*" | grep address-cells | grep "<2>"
>
> I would use <1> is the first cell is always zero...
I'll do that. Tha variation across DTS is likely coming from ~5.10 devicetree/bindings/arm/cpus.txt
- #address-cells
...
# On ARM v8 64-bit systems value should be set to 2,
that corresponds to the MPIDR_EL1 register size.
If MPIDR_EL1[63:32] value is equal to 0 on all CPUs
in the system, #address-cells can be set to 1, since
MPIDR_EL1[63:32] bits are not used for CPUs
identification.
where the size of MPIDR_EL1 register is 2 for Elba cores. However the shorthand is
allowed if MPIDR_EL1[63:32] bita are not used.
Latest version:
On ARM v8 64-bit systems this property is required
and matches the MPIDR_EL1 register affinity bits.
* If cpus node's #address-cells property is set to 2
The first reg cell bits [7:0] must be set to
bits [39:32] of MPIDR_EL1.
The second reg cell bits [23:0] must be set to
bits [23:0] of MPIDR_EL1.
* If cpus node's #address-cells property is set to 1
The reg cell bits [23:0] must be set to bits [23:0]
of MPIDR_EL1.
All other bits in the reg cells must be set to 0.
Regards,
Brad