On SC8280XP, LPASS IP is controlled by q6dsp, however the reset lines
required by some of the IPs like Soundwire still need to be programmed from
Apps processor. This patchset adds support to reset controller on LPASS
CC and LPASS AudioCC.
Tested on X13s.
Thanks,
Srini
Changes since v2:
- removed qcom,adsp-pil-mode bindings, can be added when
we have a variant of this SoC without dsp control
- added compile check in Kconfig
- fix variable naming to reflect correct cc.
- few minor style related changes
Srinivas Kandagatla (6):
dt-bindings: clock: Add LPASSCC and reset controller for SC8280XP
dt-bindings: clock: Add LPASS AUDIOCC and reset controller for
SC8280XP
clk: qcom: Add lpass clock controller driver for SC8280XP
clk: qcom: Add lpass audio clock controller driver for SC8280XP
arm64: dts: qcom: sc8280xp: add resets for soundwire controllers
arm64: defconfig: Enable sc828x0xp lpasscc clock controller
.../bindings/clock/qcom,sc8280xp-lpasscc.yaml | 60 +++++++++++++
arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 21 +++++
arch/arm64/configs/defconfig | 1 +
drivers/clk/qcom/Kconfig | 9 ++
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/lpasscc-sc8280xp.c | 87 +++++++++++++++++++
.../dt-bindings/clock/qcom,sc8280xp-lpasscc.h | 17 ++++
7 files changed, 196 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/qcom,sc8280xp-lpasscc.yaml
create mode 100644 drivers/clk/qcom/lpasscc-sc8280xp.c
create mode 100644 include/dt-bindings/clock/qcom,sc8280xp-lpasscc.h
--
2.25.1
The LPASS (Low Power Audio Subsystem) Audio clock controller provides reset
support when it is under the control of Q6DSP.
Add support for those resets and adds IDs for clients to request the reset.
Signed-off-by: Srinivas Kandagatla <[email protected]>
Reviewed-by: Johan Hovold <[email protected]>
---
.../bindings/clock/qcom,sc8280xp-lpasscc.yaml | 10 ++++++++++
include/dt-bindings/clock/qcom,sc8280xp-lpasscc.h | 5 +++++
2 files changed, 15 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/qcom,sc8280xp-lpasscc.yaml b/Documentation/devicetree/bindings/clock/qcom,sc8280xp-lpasscc.yaml
index 047cae91f443..3326dcd6766c 100644
--- a/Documentation/devicetree/bindings/clock/qcom,sc8280xp-lpasscc.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,sc8280xp-lpasscc.yaml
@@ -19,6 +19,7 @@ description: |
properties:
compatible:
enum:
+ - qcom,sc8280xp-lpassaudiocc
- qcom,sc8280xp-lpasscc
reg:
@@ -39,6 +40,15 @@ required:
additionalProperties: false
examples:
+ - |
+ #include <dt-bindings/clock/qcom,sc8280xp-lpasscc.h>
+ lpass_audiocc: clock-controller@32a9000 {
+ compatible = "qcom,sc8280xp-lpassaudiocc";
+ reg = <0x032a9000 0x1000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
- |
#include <dt-bindings/clock/qcom,sc8280xp-lpasscc.h>
lpasscc: clock-controller@33e0000 {
diff --git a/include/dt-bindings/clock/qcom,sc8280xp-lpasscc.h b/include/dt-bindings/clock/qcom,sc8280xp-lpasscc.h
index df800ea2741c..d190d57fc81a 100644
--- a/include/dt-bindings/clock/qcom,sc8280xp-lpasscc.h
+++ b/include/dt-bindings/clock/qcom,sc8280xp-lpasscc.h
@@ -6,6 +6,11 @@
#ifndef _DT_BINDINGS_CLK_QCOM_LPASSCC_SC8280XP_H
#define _DT_BINDINGS_CLK_QCOM_LPASSCC_SC8280XP_H
+/* LPASS AUDIO CC CSR */
+#define LPASS_AUDIO_SWR_RX_CGCR 0
+#define LPASS_AUDIO_SWR_WSA_CGCR 1
+#define LPASS_AUDIO_SWR_WSA2_CGCR 2
+
/* LPASS TCSR */
#define LPASS_AUDIO_SWR_TX_CGCR 0
--
2.25.1
The LPASS (Low Power Audio Subsystem) clock controller provides reset
support when it is under the control of Q6DSP.
Add support for those resets and adds IDs for clients to request the reset.
Signed-off-by: Srinivas Kandagatla <[email protected]>
Reviewed-by: Johan Hovold <[email protected]>
---
.../bindings/clock/qcom,sc8280xp-lpasscc.yaml | 50 +++++++++++++++++++
.../dt-bindings/clock/qcom,sc8280xp-lpasscc.h | 12 +++++
2 files changed, 62 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/qcom,sc8280xp-lpasscc.yaml
create mode 100644 include/dt-bindings/clock/qcom,sc8280xp-lpasscc.h
diff --git a/Documentation/devicetree/bindings/clock/qcom,sc8280xp-lpasscc.yaml b/Documentation/devicetree/bindings/clock/qcom,sc8280xp-lpasscc.yaml
new file mode 100644
index 000000000000..047cae91f443
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/qcom,sc8280xp-lpasscc.yaml
@@ -0,0 +1,50 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,sc8280xp-lpasscc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm LPASS Core & Audio Clock Controller on SC8280XP
+
+maintainers:
+ - Srinivas Kandagatla <[email protected]>
+
+description: |
+ Qualcomm LPASS core and audio clock control module provides the clocks,
+ and reset on SC8280XP.
+
+ See also::
+ include/dt-bindings/clock/qcom,lpasscc-sc8280xp.h
+
+properties:
+ compatible:
+ enum:
+ - qcom,sc8280xp-lpasscc
+
+ reg:
+ maxItems: 1
+
+ '#clock-cells':
+ const: 1
+
+ '#reset-cells':
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - '#clock-cells'
+ - '#reset-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,sc8280xp-lpasscc.h>
+ lpasscc: clock-controller@33e0000 {
+ compatible = "qcom,sc8280xp-lpasscc";
+ reg = <0x033e0000 0x12000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+...
diff --git a/include/dt-bindings/clock/qcom,sc8280xp-lpasscc.h b/include/dt-bindings/clock/qcom,sc8280xp-lpasscc.h
new file mode 100644
index 000000000000..df800ea2741c
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,sc8280xp-lpasscc.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2023, Linaro Ltd.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_LPASSCC_SC8280XP_H
+#define _DT_BINDINGS_CLK_QCOM_LPASSCC_SC8280XP_H
+
+/* LPASS TCSR */
+#define LPASS_AUDIO_SWR_TX_CGCR 0
+
+#endif
--
2.25.1
On 08/06/2023 14:53, Srinivas Kandagatla wrote:
> The LPASS (Low Power Audio Subsystem) clock controller provides reset
> support when it is under the control of Q6DSP.
>
> Add support for those resets and adds IDs for clients to request the reset.
>
> Signed-off-by: Srinivas Kandagatla <[email protected]>
> Reviewed-by: Johan Hovold <[email protected]>
> ---
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Best regards,
Krzysztof
On 08/06/2023 14:53, Srinivas Kandagatla wrote:
> The LPASS (Low Power Audio Subsystem) Audio clock controller provides reset
> support when it is under the control of Q6DSP.
>
> Add support for those resets and adds IDs for clients to request the reset.
>
> Signed-off-by: Srinivas Kandagatla <[email protected]>
> Reviewed-by: Johan Hovold <[email protected]>
> ---
> .../bindings/clock/qcom,sc8280xp-lpasscc.yaml | 10 ++++++++++
> include/dt-bindings/clock/qcom,sc8280xp-lpasscc.h | 5 +++++
> 2 files changed, 15 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/clock/qcom,sc8280xp-lpasscc.yaml b/Documentation/devicetree/bindings/clock/qcom,sc8280xp-lpasscc.yaml
> index 047cae91f443..3326dcd6766c 100644
> --- a/Documentation/devicetree/bindings/clock/qcom,sc8280xp-lpasscc.yaml
> +++ b/Documentation/devicetree/bindings/clock/qcom,sc8280xp-lpasscc.yaml
> @@ -19,6 +19,7 @@ description: |
> properties:
> compatible:
> enum:
> + - qcom,sc8280xp-lpassaudiocc
> - qcom,sc8280xp-lpasscc
>
> reg:
> @@ -39,6 +40,15 @@ required:
> additionalProperties: false
>
> examples:
> + - |
> + #include <dt-bindings/clock/qcom,sc8280xp-lpasscc.h>
> + lpass_audiocc: clock-controller@32a9000 {
> + compatible = "qcom,sc8280xp-lpassaudiocc";
No need for new example - it's the same, just with different compatible.
With this:
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Best regards,
Krzysztof
On Thu, 8 Jun 2023 13:53:09 +0100, Srinivas Kandagatla wrote:
> On SC8280XP, LPASS IP is controlled by q6dsp, however the reset lines
> required by some of the IPs like Soundwire still need to be programmed from
> Apps processor. This patchset adds support to reset controller on LPASS
> CC and LPASS AudioCC.
>
> Tested on X13s.
>
> [...]
Applied, thanks!
[6/6] arm64: defconfig: Enable sc828x0xp lpasscc clock controller
commit: 318da4837d75efb2411b86b39427b7047b41204a
Best regards,
--
Bjorn Andersson <[email protected]>