Add support for HiSilicon UC/H60PA/PAv3 PMU driver.
PAv3 PMU: Compared with the PAv2 PMU, the PAv3 PMU has different event. The
version of PMU version register is used to distinguish the v2 and v3.
H60PA PMU: The H60PA PMU and PA are two different devices. The H60PA PMU
supports higher bandwidth, and the PA PMU delay is relatively low.
Different HIDs are used to distinguish the delay.
UC PMU: Each cluster is integrated with a unified cache (UC) PMU, which
provides consistency between NUMA and UMA domains. It sits between
L2 and the memory system.
Change since v3:
- Modify the UC PMU patch commit message according to Jonathan's comment.
Link: https://lore.kernel.org/linux-arm-kernel/[email protected]/
Change since v2:
- Modify the driver description according to Jonathan's comment.
Link: https://lore.kernel.org/linux-arm-kernel/[email protected]/
Change since v1:
- Improve according to Yicong's suggestion
- Fixes build warning of "-Wmissing-prototypes"
Link: https://lore.kernel.org/lkml/[email protected]/
Junhao He (3):
drivers/perf: hisi: Add support for HiSilicon H60PA and PAv3 PMU
driver
drivers/perf: hisi: Add support for HiSilicon UC PMU driver
docs: perf: Add new description for HiSilicon UC PMU
Documentation/admin-guide/perf/hisi-pmu.rst | 8 +
drivers/perf/hisilicon/Makefile | 2 +-
drivers/perf/hisilicon/hisi_uncore_pa_pmu.c | 142 ++++-
drivers/perf/hisilicon/hisi_uncore_pmu.c | 4 +-
drivers/perf/hisilicon/hisi_uncore_pmu.h | 15 +
drivers/perf/hisilicon/hisi_uncore_uc_pmu.c | 578 ++++++++++++++++++++
6 files changed, 732 insertions(+), 17 deletions(-)
create mode 100644 drivers/perf/hisilicon/hisi_uncore_uc_pmu.c
--
2.33.0
A new function is added on HiSilicon uncore UC PMU.
The UC PMU support to filter statistical information based on
the specified tx request uring channel. Make user configuration
through "uring_channel" parameter.
Document them to provide guidance on how to use them.
Signed-off-by: Junhao He <[email protected]>
Reviewed-by: Jonathan Cameron <[email protected]>
Reviewed-by: Yicong Yang <[email protected]>
---
Documentation/admin-guide/perf/hisi-pmu.rst | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/Documentation/admin-guide/perf/hisi-pmu.rst b/Documentation/admin-guide/perf/hisi-pmu.rst
index 546979360513..939a524fa1d6 100644
--- a/Documentation/admin-guide/perf/hisi-pmu.rst
+++ b/Documentation/admin-guide/perf/hisi-pmu.rst
@@ -98,6 +98,14 @@ CCL/ICL-ID. For I/O die, the ICL-ID is followed by:
5'b00011: HAC_ICL;
5'b10000: PCIe_ICL;
+(e) uring_channel: UC PMU events 0x47~0x59 supports filtering by tx request
+uring channel. It is 2 bits. Some important codes are as follows:
+2'b11: count the events which sent to the uring_ext (MATA) channel;
+2'b01: is the same as 2'b11;
+2'b10: count the events which sent to the uring (non-MATA) channel;
+2'b00: default value, count the events which sent to the both uring and
+ uring_ext channel;
+
Users could configure IDs to count data come from specific CCL/ICL, by setting
srcid_cmd & srcid_msk, and data desitined for specific CCL/ICL by setting
tgtid_cmd & tgtid_msk. A set bit in srcid_msk/tgtid_msk means the PMU will not
--
2.33.0
On Fri, Jun 09, 2023 at 03:56:08PM +0800, Junhao He wrote:
> A new function is added on HiSilicon uncore UC PMU.
>
> The UC PMU support to filter statistical information based on
> the specified tx request uring channel. Make user configuration
> through "uring_channel" parameter.
> Document them to provide guidance on how to use them.
>
> Signed-off-by: Junhao He <[email protected]>
> Reviewed-by: Jonathan Cameron <[email protected]>
> Reviewed-by: Yicong Yang <[email protected]>
Acked-by: Mark Rutland <[email protected]>
Mark.
> ---
> Documentation/admin-guide/perf/hisi-pmu.rst | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
> diff --git a/Documentation/admin-guide/perf/hisi-pmu.rst b/Documentation/admin-guide/perf/hisi-pmu.rst
> index 546979360513..939a524fa1d6 100644
> --- a/Documentation/admin-guide/perf/hisi-pmu.rst
> +++ b/Documentation/admin-guide/perf/hisi-pmu.rst
> @@ -98,6 +98,14 @@ CCL/ICL-ID. For I/O die, the ICL-ID is followed by:
> 5'b00011: HAC_ICL;
> 5'b10000: PCIe_ICL;
>
> +(e) uring_channel: UC PMU events 0x47~0x59 supports filtering by tx request
> +uring channel. It is 2 bits. Some important codes are as follows:
> +2'b11: count the events which sent to the uring_ext (MATA) channel;
> +2'b01: is the same as 2'b11;
> +2'b10: count the events which sent to the uring (non-MATA) channel;
> +2'b00: default value, count the events which sent to the both uring and
> + uring_ext channel;
> +
> Users could configure IDs to count data come from specific CCL/ICL, by setting
> srcid_cmd & srcid_msk, and data desitined for specific CCL/ICL by setting
> tgtid_cmd & tgtid_msk. A set bit in srcid_msk/tgtid_msk means the PMU will not
> --
> 2.33.0
>