by Conor Dooley

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Subject: Re: [PATCH 5/9] drm: atmel-hlcdc: add compatible string check for XLCDC and HLCDC

On Tue, Jun 13, 2023 at 12:34:22PM +0530, Manikandan Muralidharan wrote:
> From: Durai Manickam KR <[email protected]>
>
> Add compatible string check to differentiate XLCDC and HLCDC code
> within the atmel-hlcdc driver files.
>
> Signed-off-by: Durai Manickam KR <[email protected]>
> Signed-off-by: Manikandan Muralidharan <[email protected]>
> ---
> drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c | 7 +++++++
> drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h | 1 +
> 2 files changed, 8 insertions(+)
>
> diff --git a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c
> index d7ad828e9e8c..fbbd2592efc7 100644
> --- a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c
> +++ b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c
> @@ -761,6 +761,13 @@ static int atmel_hlcdc_dc_load(struct drm_device *dev)
> if (!dc)
> return -ENOMEM;
>
> + /* SAM9X7 supports XLCDC */
> + if (!strcmp(match->compatible, "microchip,sam9x7-xlcdc"))
> + dc->is_xlcdc = true;
> + else
> + /* Other SoC's that supports HLCDC IP */

Should this be "Other SoCs that do not support HLCDC IP"?

> + dc->is_xlcdc = false;
> +
> dc->desc = match->data;
> dc->hlcdc = dev_get_drvdata(dev->dev->parent);
> dev->dev_private = dc;
> diff --git a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h
> index aed1742b3665..804e4d476f2b 100644
> --- a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h
> +++ b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h
> @@ -451,6 +451,7 @@ struct atmel_hlcdc_dc {
> u32 imr;
> struct drm_atomic_state *state;
> } suspend;
> + bool is_xlcdc;
> };
>
> extern struct atmel_hlcdc_formats atmel_hlcdc_plane_rgb_formats;
> --
> 2.25.1
>

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2023-06-13 18:56:55

On Tue, Jun 13, 2023 at 12:34:18PM +0530, Manikandan Muralidharan wrote:
> Add new compatible string for the XLCD controller on SAM9X7 SoC.

You should probably indicate here why this is not compatible with the
existing SoCs that are supported. To hazard a guess, it is the HLCDC IP
(I forget the exact letters!)?
If so,
Acked-by: Conor Dooley <[email protected]>

Cheers,
Conor.

>
> Signed-off-by: Manikandan Muralidharan <[email protected]>
> ---
> Documentation/devicetree/bindings/mfd/atmel-hlcdc.txt | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/mfd/atmel-hlcdc.txt b/Documentation/devicetree/bindings/mfd/atmel-hlcdc.txt
> index 5f8880cc757e..7c77b6bf4adb 100644
> --- a/Documentation/devicetree/bindings/mfd/atmel-hlcdc.txt
> +++ b/Documentation/devicetree/bindings/mfd/atmel-hlcdc.txt
> @@ -8,6 +8,7 @@ Required properties:
> "atmel,sama5d3-hlcdc"
> "atmel,sama5d4-hlcdc"
> "microchip,sam9x60-hlcdc"
> + "microchip,sam9x7-xlcdc"
> - reg: base address and size of the HLCDC device registers.
> - clock-names: the name of the 3 clocks requested by the HLCDC device.
> Should contain "periph_clk", "sys_clk" and "slow_clk".
> --
> 2.25.1
>

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2023-06-13 19:06:42

On Tue, Jun 13, 2023 at 07:18:25PM +0100, Conor Dooley wrote:
> On Tue, Jun 13, 2023 at 12:34:18PM +0530, Manikandan Muralidharan wrote:
> > Add new compatible string for the XLCD controller on SAM9X7 SoC.
>
> You should probably indicate here why this is not compatible with the
> existing SoCs that are supported. To hazard a guess, it is the HLCDC IP
> (I forget the exact letters!)?

Manikandan pointed out off list that this was not clear.
Looking at it again, I think I actually truncated my sentence - it
should've been something like "it is the HLCDC IP ... is not a subset of
the XLCDC IP." Sorry for that Manikandan.

> If so,
> Acked-by: Conor Dooley <[email protected]>
>
> Cheers,
> Conor.
>
> >
> > Signed-off-by: Manikandan Muralidharan <[email protected]>
> > ---
> > Documentation/devicetree/bindings/mfd/atmel-hlcdc.txt | 1 +
> > 1 file changed, 1 insertion(+)
> >
> > diff --git a/Documentation/devicetree/bindings/mfd/atmel-hlcdc.txt b/Documentation/devicetree/bindings/mfd/atmel-hlcdc.txt
> > index 5f8880cc757e..7c77b6bf4adb 100644
> > --- a/Documentation/devicetree/bindings/mfd/atmel-hlcdc.txt
> > +++ b/Documentation/devicetree/bindings/mfd/atmel-hlcdc.txt
> > @@ -8,6 +8,7 @@ Required properties:
> > "atmel,sama5d3-hlcdc"
> > "atmel,sama5d4-hlcdc"
> > "microchip,sam9x60-hlcdc"
> > + "microchip,sam9x7-xlcdc"
> > - reg: base address and size of the HLCDC device registers.
> > - clock-names: the name of the 3 clocks requested by the HLCDC device.
> > Should contain "periph_clk", "sys_clk" and "slow_clk".
> > --
> > 2.25.1
> >

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2023-06-14 10:31:05

On Mon, Jun 26, 2023 at 05:31:59AM +0000, [email protected] wrote:
> On 21/06/23 13:17, Nicolas Ferre wrote:
> > On 16/06/2023 at 08:44, Manikandan M - I67131 wrote:
> >> On 14/06/23 20:10, Nicolas Ferre wrote:
> >>> On 13/06/2023 at 20:21, Conor Dooley wrote:
> >>>> On Tue, Jun 13, 2023 at 08:17:13PM +0200, Krzysztof Kozlowski wrote:
> >>>>> On 13/06/2023 09:04, Manikandan Muralidharan wrote:
> >>>>>> Add new compatible string for the XLCD controller on SAM9X7 SoC.
> >>>>>>
> >>>>>> Signed-off-by: Manikandan Muralidharan<[email protected]>
> >>>>>> ---
> >>>>>> ?? Documentation/devicetree/bindings/mfd/atmel-hlcdc.txt | 1 +
> >>>>>> ?? 1 file changed, 1 insertion(+)
> >>>>>>
> >>>>>> diff --git a/Documentation/devicetree/bindings/mfd/atmel-hlcdc.txt
> >>>>>> b/Documentation/devicetree/bindings/mfd/atmel-hlcdc.txt
> >>>>>> index 5f8880cc757e..7c77b6bf4adb 100644
> >>>>>> --- a/Documentation/devicetree/bindings/mfd/atmel-hlcdc.txt
> >>>>>> +++ b/Documentation/devicetree/bindings/mfd/atmel-hlcdc.txt
> >>>>>> @@ -8,6 +8,7 @@ Required properties:
> >>>>>> ????? "atmel,sama5d3-hlcdc"
> >>>>>> ????? "atmel,sama5d4-hlcdc"
> >>>>>> ????? "microchip,sam9x60-hlcdc"
> >>>>>> +?? "microchip,sam9x7-xlcdc"
> >>>>> Google says sam9x7 is a series, not a SoC. Please add compatibles for
> >>>>> specific SoCs, not for series.
> >>>> We had this one a few weeks ago, see
> >>>> https://lore.kernel.org/all/[email protected]/
> >>>> and its parents. Outcome of that seemed to be that using "sam9x7" was
> >>>> fine.
> >>>
> >>> And it's where it begins to be funny, as the LCD is precisely one aspect
> >>> where we differentiate between sam9x75, sam9x72 and sam9x70...
> >>> So please Manikandan sort this out if difference between these chips
> >>> will be better handled with different compatibility string, in
> >>> particular about //, LVDS and MIPI-DSI variants!
> >> Yes Sure, I will replace the compatible as s/sam9x7/sam9x75/g to handle
> >> the different variants of sam9x7 better.
> >
> > Moving to sam9x75 is probably good. But what is your plan for
> > differentiating parallel and LVDS (on sam9x72) and precisely this
> > sam9x75 variant which in addition has MIPI-DSI?
> In sam9x75 with support for LVDS and MIPI, Parallel interfacing
> peripherals, the additions performed on the LCD controller driver is the
> same.Considering the LCDC IP used in sam9x75, there are no registers
> sets that needs modification per connecting peripheral variants, only
> the clock and DRM_ENCODER_MODE_XXX (set by connecting peripheral driver)
> differs, which can be handled in DT, atmel-lcdc MFD driver and
> peripheral driver.
>
> In future, sam9x72 with XLCD controller can be differentiated with
> sam9x72 compatible string and with a IP version flag(is_xlcdc_v2) in its
> driver data if an upgraded XLCD IP is used with difference in bits or
> register set exist compared to current IP.

Trying to covert that into what the binding will look like...
sam9x72 & sam9x75 each get their own compatibles for the lcd controller.
From there, we permit `compatible = "microchip,sam9x75-foo"` in
isolation. It *sounds* like the basic featureset of the sam9x75 is
compatible with the sam9x72, so for that we permit
`compatible = "microchip,sam9x72-foo", "microchip,sam9x75-foo"`.
Although, if the hardware for the sam9x72 isn't set in stone yet, it
might be best to hold off on documenting it until things settle down,
and only add the sam9x75 for now.

Cheers,
Conor.

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2023-06-26 20:29:19

by Sam Ravnborg

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Subject: Re: [PATCH 3/9] drm: atmel-hlcdc: add LCD controller layer definition for SAM9X7

Hi Manikandan,

On Tue, Jun 13, 2023 at 12:34:20PM +0530, Manikandan Muralidharan wrote:
> Add the LCD controller layer definition and descriptor structure for SAM9X7
> for the following layers,
> - Base Layer
> - Overlay1 Layer
> - Overlay2 Layer
> - High End Overlay
>
> Signed-off-by: Manikandan Muralidharan <[email protected]>
> ---
> drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c | 96 ++++++++++++++++++++
> 1 file changed, 96 insertions(+)
>
> diff --git a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c
> index fa0f9a93d50d..d7ad828e9e8c 100644
> --- a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c
> +++ b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c
> @@ -462,6 +462,98 @@ static const struct atmel_hlcdc_dc_desc atmel_hlcdc_dc_sam9x60 = {
> .layers = atmel_hlcdc_sam9x60_layers,
> };
>
> +static const struct atmel_hlcdc_layer_desc atmel_xlcdc_sam9x7_layers[] = {
> + {
> + .name = "base",
> + .formats = &atmel_hlcdc_plane_rgb_formats,
> + .regs_offset = 0x60,
> + .id = 0,
> + .type = ATMEL_HLCDC_BASE_LAYER,
> + .cfgs_offset = 0x1c,
> + .layout = {
> + .xstride = { 2 },
> + .default_color = 3,
> + .general_config = 4,
> + .disc_pos = 5,
> + .disc_size = 6,
> + },
> + .clut_offset = 0x700,
> + },
> + {
> + .name = "overlay1",
> + .formats = &atmel_hlcdc_plane_rgb_formats,
> + .regs_offset = 0x160,
> + .id = 1,
> + .type = ATMEL_HLCDC_OVERLAY_LAYER,
> + .cfgs_offset = 0x1c,
> + .layout = {
> + .pos = 2,
> + .size = 3,
> + .xstride = { 4 },
> + .pstride = { 5 },
> + .default_color = 6,
> + .chroma_key = 7,
> + .chroma_key_mask = 8,
> + .general_config = 9,
> + },
> + .clut_offset = 0xb00,
> + },
> + {
> + .name = "overlay2",
> + .formats = &atmel_hlcdc_plane_rgb_formats,
> + .regs_offset = 0x260,
> + .id = 2,
> + .type = ATMEL_HLCDC_OVERLAY_LAYER,
> + .cfgs_offset = 0x1c,
> + .layout = {
> + .pos = 2,
> + .size = 3,
> + .xstride = { 4 },
> + .pstride = { 5 },
> + .default_color = 6,
> + .chroma_key = 7,
> + .chroma_key_mask = 8,
> + .general_config = 9,
> + },
> + .clut_offset = 0xf00,
> + },
> + {
> + .name = "high-end-overlay",
> + .formats = &atmel_hlcdc_plane_rgb_and_yuv_formats,
> + .regs_offset = 0x360,
> + .id = 3,
> + .type = ATMEL_HLCDC_OVERLAY_LAYER,
> + .cfgs_offset = 0x30,
> + .layout = {
> + .pos = 2,
> + .size = 3,
> + .memsize = 4,
> + .xstride = { 5, 7 },
> + .pstride = { 6, 8 },
> + .default_color = 9,
> + .chroma_key = 10,
> + .chroma_key_mask = 11,
> + .general_config = 12,
> + .csc = 16,
> + .scaler_config = 23,
> + },
> + .clut_offset = 0x1300,
> + },
> +};
> +
> +static const struct atmel_hlcdc_dc_desc atmel_xlcdc_dc_sam9x7 = {
> + .min_width = 0,
> + .min_height = 0,
> + .max_width = 2048,
> + .max_height = 2048,
> + .max_spw = 0xff,
> + .max_vpw = 0xff,
> + .max_hpw = 0x3ff,
> + .fixed_clksrc = true,
> + .nlayers = ARRAY_SIZE(atmel_xlcdc_sam9x7_layers),
> + .layers = atmel_xlcdc_sam9x7_layers,
> +};

As already suggested by someone else, add is_xlcdc to struct
atmel_hlcdc_dc_desc, so the check for the compatible can be dropped.
It would be better to put it here.

Sam

2023-06-26 21:23:16

by Sam Ravnborg

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Subject: Re: [PATCH 6/9] drm: atmel_hlcdc: Add support for XLCDC in atmel LCD driver

Hi Manikandan,

On Tue, Jun 13, 2023 at 12:34:23PM +0530, Manikandan Muralidharan wrote:
> - XLCDC in SAM9X7 has different sets of registers and additional
> configuration bits when compared to previous HLCDC IP. Read/write
> operation on the controller registers is now separated using the
> XLCDC status flag.
> - HEO scaling, window resampling, Alpha blending, YUV-to-RGB
> conversion in XLCDC is derived and handled using additional
> configuration bits and registers.
> - Writing one to the Enable fields of each layer in LCD_ATTRE
> is required to reflect the values set in Configuration, FBA, Enable
> registers of each layer

In general things would benefit from a more clear separation between
hlcdc and xlcdc. In several cases two functions would be better than
testing as done today.

See some more specific comments in the following.

Sam

>
> Signed-off-by: Manikandan Muralidharan <[email protected]>
> [[email protected]: update the attribute field for each layer]
> Signed-off-by: Hari Prasath Gujulan Elango <[email protected]>
> [[email protected]: implement status flag to seprate register update]
> Signed-off-by: Durai Manickam KR <[email protected]>
> ---
> .../gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c | 28 +-
> .../gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c | 297 ++++++++++++++----
> 2 files changed, 256 insertions(+), 69 deletions(-)
>
> diff --git a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c
> index 58184cd6ab0b..7c9cf7c0c75d 100644
> --- a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c
> +++ b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c
> @@ -139,10 +139,10 @@ static void atmel_hlcdc_crtc_mode_set_nofb(struct drm_crtc *c)
> state = drm_crtc_state_to_atmel_hlcdc_crtc_state(c->state);
> cfg = state->output_mode << 8;
>
> - if (adj->flags & DRM_MODE_FLAG_NVSYNC)
> + if (!crtc->dc->is_xlcdc && (adj->flags & DRM_MODE_FLAG_NVSYNC))
> cfg |= ATMEL_HLCDC_VSPOL;
>
> - if (adj->flags & DRM_MODE_FLAG_NHSYNC)
> + if (!crtc->dc->is_xlcdc && (adj->flags & DRM_MODE_FLAG_NHSYNC))
> cfg |= ATMEL_HLCDC_HSPOL;

From the above code I assume ATMEL_HLCDC_VSPOL and ATMEL_HLCDC_HSPOL are
specific to HLCDC and not part of XLCDC register set.

We can identify XLCDC specific registers as thy use "XLCDC" in the name.
But the "HLCDC" specific registers are not easy to spot.

Would it make sense to update the register definitions so we can see in
the register names which at XLCDC, which are HLCDC and which a common
(LCDC)?

It would require a little code crunch to do so as all users would need
an update. Dunno if this is worth it.
But then at least a comment in the register definition file.

>
> regmap_update_bits(regmap, ATMEL_HLCDC_CFG(5),
> @@ -177,6 +177,18 @@ static void atmel_hlcdc_crtc_atomic_disable(struct drm_crtc *c,
>
> pm_runtime_get_sync(dev->dev);
>
> + if (crtc->dc->is_xlcdc) {
> + regmap_write(regmap, ATMEL_HLCDC_DIS, ATMEL_XLCDC_CM);
> + while (!regmap_read(regmap, ATMEL_HLCDC_SR, &status) &&
> + (status & ATMEL_XLCDC_CM))
> + cpu_relax();
> +
> + regmap_write(regmap, ATMEL_HLCDC_DIS, ATMEL_XLCDC_SD);
> + while (!regmap_read(regmap, ATMEL_HLCDC_SR, &status) &&
> + !(status & ATMEL_XLCDC_SD))
> + cpu_relax();
> + }

A small helper atmel_xlcdc_disable()?

> +
> regmap_write(regmap, ATMEL_HLCDC_DIS, ATMEL_HLCDC_DISP);
> while (!regmap_read(regmap, ATMEL_HLCDC_SR, &status) &&
> (status & ATMEL_HLCDC_DISP))
> @@ -231,6 +243,18 @@ static void atmel_hlcdc_crtc_atomic_enable(struct drm_crtc *c,
> !(status & ATMEL_HLCDC_DISP))
> cpu_relax();
>
> + if (crtc->dc->is_xlcdc) {
> + regmap_write(regmap, ATMEL_HLCDC_EN, ATMEL_XLCDC_CM);
> + while (!regmap_read(regmap, ATMEL_HLCDC_SR, &status) &&
> + !(status & ATMEL_XLCDC_CM))
> + cpu_relax();
> +
> + regmap_write(regmap, ATMEL_HLCDC_EN, ATMEL_XLCDC_SD);
> + while (!regmap_read(regmap, ATMEL_HLCDC_SR, &status) &&
> + (status & ATMEL_XLCDC_SD))
> + cpu_relax();
> + }

A small helper atmel_xlcdc_enable()?

> +
> pm_runtime_put_sync(dev->dev);
>
> }
> diff --git a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c
> index daa508504f47..fe33476818c4 100644
> --- a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c
> +++ b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c
> @@ -330,11 +330,59 @@ static void atmel_hlcdc_plane_setup_scaler(struct atmel_hlcdc_plane *plane,
> yfactor));
> }
>
> +static void atmel_xlcdc_plane_setup_scaler(struct atmel_hlcdc_plane *plane,
> + struct atmel_hlcdc_plane_state *state)
> +{
> + const struct atmel_hlcdc_layer_desc *desc = plane->layer.desc;
> + u32 xfactor, yfactor;
> +
> + if (!desc->layout.scaler_config)
> + return;
> +
> + if (state->crtc_w == state->src_w && state->crtc_h == state->src_h) {
> + atmel_hlcdc_layer_write_cfg(&plane->layer,
> + desc->layout.scaler_config, 0);
> + return;
> + }
> +
> + /* xfactor = round[(2^20 * XMEMSIZE)/XSIZE)] */
> + xfactor = (1048576 * state->src_w) / state->crtc_w;
> +
> + /* yfactor = round[(2^20 * YMEMSIZE)/YSIZE)] */
> + yfactor = (1048576 * state->src_h) / state->crtc_h;
> +
> + atmel_hlcdc_layer_write_cfg(&plane->layer, desc->layout.scaler_config,
> + ATMEL_XLCDC_LAYER_VSCALER_LUMA_ENABLE |
> + ATMEL_XLCDC_LAYER_VSCALER_CHROMA_ENABLE |
> + ATMEL_XLCDC_LAYER_HSCALER_LUMA_ENABLE |
> + ATMEL_XLCDC_LAYER_HSCALER_CHROMA_ENABLE);
> +
> + atmel_hlcdc_layer_write_cfg(&plane->layer, desc->layout.scaler_config + 1,
> + yfactor);
> + atmel_hlcdc_layer_write_cfg(&plane->layer, desc->layout.scaler_config + 3,
> + xfactor);
> +
> + /* As per YCbCr window resampling configuration */
> + if (state->base.fb->format->format == DRM_FORMAT_YUV420) {
> + atmel_hlcdc_layer_write_cfg(&plane->layer, desc->layout.scaler_config + 2,
> + yfactor / 2);
> + atmel_hlcdc_layer_write_cfg(&plane->layer, desc->layout.scaler_config + 4,
> + xfactor / 2);
> + } else {
> + /* As per ARGB window resampling configuration */
> + atmel_hlcdc_layer_write_cfg(&plane->layer, desc->layout.scaler_config + 2,
> + yfactor);
> + atmel_hlcdc_layer_write_cfg(&plane->layer, desc->layout.scaler_config + 4,
> + xfactor);
> + }
> +}
> +
> static void
> atmel_hlcdc_plane_update_pos_and_size(struct atmel_hlcdc_plane *plane,
> struct atmel_hlcdc_plane_state *state)
> {
> const struct atmel_hlcdc_layer_desc *desc = plane->layer.desc;
> + struct atmel_hlcdc_dc *dc = plane->base.dev->dev_private;
>
> if (desc->layout.size)
> atmel_hlcdc_layer_write_cfg(&plane->layer, desc->layout.size,
> @@ -352,7 +400,10 @@ atmel_hlcdc_plane_update_pos_and_size(struct atmel_hlcdc_plane *plane,
> ATMEL_HLCDC_LAYER_POS(state->crtc_x,
> state->crtc_y));
>
> - atmel_hlcdc_plane_setup_scaler(plane, state);
> + if (!(dc->is_xlcdc))
> + atmel_hlcdc_plane_setup_scaler(plane, state);
> + else
> + atmel_xlcdc_plane_setup_scaler(plane, state);
> }
>
> static void
> @@ -362,33 +413,58 @@ atmel_hlcdc_plane_update_general_settings(struct atmel_hlcdc_plane *plane,
> unsigned int cfg = ATMEL_HLCDC_LAYER_DMA_BLEN_INCR16 | state->ahb_id;
> const struct atmel_hlcdc_layer_desc *desc = plane->layer.desc;
> const struct drm_format_info *format = state->base.fb->format;
> -
> + struct atmel_hlcdc_dc *dc = plane->base.dev->dev_private;
> /*
> * Rotation optimization is not working on RGB888 (rotation is still
> * working but without any optimization).
> */
> - if (format->format == DRM_FORMAT_RGB888)
> + if ((!(dc->is_xlcdc)) && format->format == DRM_FORMAT_RGB888)
> cfg |= ATMEL_HLCDC_LAYER_DMA_ROTDIS;
>
> - atmel_hlcdc_layer_write_cfg(&plane->layer, ATMEL_HLCDC_LAYER_DMA_CFG,
> - cfg);
> + if (!(dc->is_xlcdc)) {
> + atmel_hlcdc_layer_write_cfg(&plane->layer, ATMEL_HLCDC_LAYER_DMA_CFG,
> + cfg);
>
> - cfg = ATMEL_HLCDC_LAYER_DMA | ATMEL_HLCDC_LAYER_REP;
> + cfg = ATMEL_HLCDC_LAYER_DMA | ATMEL_HLCDC_LAYER_REP;
> + } else {
> + atmel_hlcdc_layer_write_cfg(&plane->layer, ATMEL_XLCDC_LAYER_DMA_CFG,
> + cfg);
> +
> + cfg = ATMEL_XLCDC_LAYER_DMA | ATMEL_XLCDC_LAYER_REP;
> + }
>
> if (plane->base.type != DRM_PLANE_TYPE_PRIMARY) {
> - cfg |= ATMEL_HLCDC_LAYER_OVR | ATMEL_HLCDC_LAYER_ITER2BL |
> - ATMEL_HLCDC_LAYER_ITER;
> + if (!(dc->is_xlcdc)) {
> + cfg |= ATMEL_HLCDC_LAYER_OVR | ATMEL_HLCDC_LAYER_ITER2BL |
> + ATMEL_HLCDC_LAYER_ITER;
> +
> + if (format->has_alpha)
> + cfg |= ATMEL_HLCDC_LAYER_LAEN;
> + else
> + cfg |= ATMEL_HLCDC_LAYER_GAEN |
> + ATMEL_HLCDC_LAYER_GA(state->base.alpha);
> + } else {
> + /*
> + * Alpha Blending bits specific to SAM9X7 SoC
> + */
> + cfg |= ATMEL_XLCDC_LAYER_SFACTC_A0_MULT_AS |
> + ATMEL_XLCDC_LAYER_SFACTA_ONE |
> + ATMEL_XLCDC_LAYER_DFACTC_M_A0_MULT_AS |
> + ATMEL_XLCDC_LAYER_DFACTA_ONE;
> + if (format->has_alpha)
> + cfg |= ATMEL_XLCDC_LAYER_A0(0xff);
> + else
> + cfg |= ATMEL_XLCDC_LAYER_A0(state->base.alpha);
> + }
> + }
>
> - if (format->has_alpha)
> - cfg |= ATMEL_HLCDC_LAYER_LAEN;
> + if (state->disc_h && state->disc_w) {
> + if (!(dc->is_xlcdc))
> + cfg |= ATMEL_HLCDC_LAYER_DISCEN;
> else
> - cfg |= ATMEL_HLCDC_LAYER_GAEN |
> - ATMEL_HLCDC_LAYER_GA(state->base.alpha);
> + cfg |= ATMEL_XLCDC_LAYER_DISCEN;
> }
>
> - if (state->disc_h && state->disc_w)
> - cfg |= ATMEL_HLCDC_LAYER_DISCEN;
> -
> atmel_hlcdc_layer_write_cfg(&plane->layer, desc->layout.general_config,
> cfg);
> }

There is almost no code in atmel_hlcdc_plane_update_general_settings
that are shared anymore - please try to split out in two helpers, one
for hlcdc and one for xlcdc. Maybe add a third with some common code if
it makes sense.
That should result in much more readable code in the ind.

> @@ -441,33 +517,42 @@ static void atmel_hlcdc_plane_update_buffers(struct atmel_hlcdc_plane *plane,
> struct atmel_hlcdc_plane_state *state)
> {
> const struct atmel_hlcdc_layer_desc *desc = plane->layer.desc;
> + struct atmel_hlcdc_dc *dc = plane->base.dev->dev_private;
> struct drm_framebuffer *fb = state->base.fb;
> u32 sr;
> int i;
>
> - sr = atmel_hlcdc_layer_read_reg(&plane->layer, ATMEL_HLCDC_LAYER_CHSR);
> + if (!(dc->is_xlcdc))
> + sr = atmel_hlcdc_layer_read_reg(&plane->layer, ATMEL_HLCDC_LAYER_CHSR);
> + else
> + sr = atmel_hlcdc_layer_read_reg(&plane->layer, ATMEL_XLCDC_LAYER_ENR);
>
> for (i = 0; i < state->nplanes; i++) {
> struct drm_gem_dma_object *gem = drm_fb_dma_get_gem_obj(fb, i);
>
> state->dscrs[i]->addr = gem->dma_addr + state->offsets[i];
>
> - atmel_hlcdc_layer_write_reg(&plane->layer,
> - ATMEL_HLCDC_LAYER_PLANE_HEAD(i),
> - state->dscrs[i]->self);
> -
> - if (!(sr & ATMEL_HLCDC_LAYER_EN)) {
> - atmel_hlcdc_layer_write_reg(&plane->layer,
> - ATMEL_HLCDC_LAYER_PLANE_ADDR(i),
> - state->dscrs[i]->addr);
> + if (!(dc->is_xlcdc)) {
> atmel_hlcdc_layer_write_reg(&plane->layer,
> - ATMEL_HLCDC_LAYER_PLANE_CTRL(i),
> - state->dscrs[i]->ctrl);
> + ATMEL_HLCDC_LAYER_PLANE_HEAD(i),
> + state->dscrs[i]->self);
> +
> + if (!(sr & ATMEL_HLCDC_LAYER_EN)) {
> + atmel_hlcdc_layer_write_reg(&plane->layer,
> + ATMEL_HLCDC_LAYER_PLANE_ADDR(i),
> + state->dscrs[i]->addr);
> + atmel_hlcdc_layer_write_reg(&plane->layer,
> + ATMEL_HLCDC_LAYER_PLANE_CTRL(i),
> + state->dscrs[i]->ctrl);
> + atmel_hlcdc_layer_write_reg(&plane->layer,
> + ATMEL_HLCDC_LAYER_PLANE_NEXT(i),
> + state->dscrs[i]->self);
> + }
> + } else {
> atmel_hlcdc_layer_write_reg(&plane->layer,
> - ATMEL_HLCDC_LAYER_PLANE_NEXT(i),
> - state->dscrs[i]->self);
> + ATMEL_XLCDC_LAYER_PLANE_ADDR(i),
> + state->dscrs[i]->addr);
> }
> -
> if (desc->layout.xstride[i])
> atmel_hlcdc_layer_write_cfg(&plane->layer,
> desc->layout.xstride[i],

The xstide stuff is shared the rest is more or less XLCDC / HLCDC
specific. Try to split it out in a few xlcdc/hlcdc helpers to increase
readability.
Maybe do it in two steps. Introduce helper for hlcdc and thenadd xlcdc
stuff.

> @@ -716,19 +801,31 @@ static void atmel_hlcdc_plane_atomic_disable(struct drm_plane *p,
> struct drm_atomic_state *state)
> {
> struct atmel_hlcdc_plane *plane = drm_plane_to_atmel_hlcdc_plane(p);
> -
> + struct atmel_hlcdc_dc *dc = plane->base.dev->dev_private;
> /* Disable interrupts */
> - atmel_hlcdc_layer_write_reg(&plane->layer, ATMEL_HLCDC_LAYER_IDR,
> - 0xffffffff);
> + if (!(dc->is_xlcdc))
> + atmel_hlcdc_layer_write_reg(&plane->layer, ATMEL_HLCDC_LAYER_IDR,
> + 0xffffffff);
> + else
> + atmel_hlcdc_layer_write_reg(&plane->layer, ATMEL_XLCDC_LAYER_IDR,
> + 0xffffffff);
>
> /* Disable the layer */
> - atmel_hlcdc_layer_write_reg(&plane->layer, ATMEL_HLCDC_LAYER_CHDR,
> - ATMEL_HLCDC_LAYER_RST |
> - ATMEL_HLCDC_LAYER_A2Q |
> - ATMEL_HLCDC_LAYER_UPDATE);
> + if (!(dc->is_xlcdc))
> + atmel_hlcdc_layer_write_reg(&plane->layer,
> + ATMEL_HLCDC_LAYER_CHDR,
> + ATMEL_HLCDC_LAYER_RST |
> + ATMEL_HLCDC_LAYER_A2Q |
> + ATMEL_HLCDC_LAYER_UPDATE);
> + else
> + atmel_hlcdc_layer_write_reg(&plane->layer,
> + ATMEL_XLCDC_LAYER_ENR, 0);
>
> /* Clear all pending interrupts */
> - atmel_hlcdc_layer_read_reg(&plane->layer, ATMEL_HLCDC_LAYER_ISR);
> + if (!(dc->is_xlcdc))
> + atmel_hlcdc_layer_read_reg(&plane->layer, ATMEL_HLCDC_LAYER_ISR);
> + else
> + atmel_hlcdc_layer_read_reg(&plane->layer, ATMEL_XLCDC_LAYER_ISR);
> }
This looks like another good candidate for two functions, one for xlcdc,
one for hlcdc.

>
> static void atmel_hlcdc_plane_atomic_update(struct drm_plane *p,
> @@ -739,6 +836,7 @@ static void atmel_hlcdc_plane_atomic_update(struct drm_plane *p,
> struct atmel_hlcdc_plane *plane = drm_plane_to_atmel_hlcdc_plane(p);
> struct atmel_hlcdc_plane_state *hstate =
> drm_plane_state_to_atmel_hlcdc_plane_state(new_s);
> + struct atmel_hlcdc_dc *dc = p->dev->dev_private;
> u32 sr;
>
> if (!new_s->crtc || !new_s->fb)
> @@ -756,23 +854,46 @@ static void atmel_hlcdc_plane_atomic_update(struct drm_plane *p,
> atmel_hlcdc_plane_update_buffers(plane, hstate);
> atmel_hlcdc_plane_update_disc_area(plane, hstate);
>
> - /* Enable the overrun interrupts. */
> - atmel_hlcdc_layer_write_reg(&plane->layer, ATMEL_HLCDC_LAYER_IER,
> - ATMEL_HLCDC_LAYER_OVR_IRQ(0) |
> - ATMEL_HLCDC_LAYER_OVR_IRQ(1) |
> - ATMEL_HLCDC_LAYER_OVR_IRQ(2));
> -
> - /* Apply the new config at the next SOF event. */
> - sr = atmel_hlcdc_layer_read_reg(&plane->layer, ATMEL_HLCDC_LAYER_CHSR);
> - atmel_hlcdc_layer_write_reg(&plane->layer, ATMEL_HLCDC_LAYER_CHER,
> - ATMEL_HLCDC_LAYER_UPDATE |
> - (sr & ATMEL_HLCDC_LAYER_EN ?
> - ATMEL_HLCDC_LAYER_A2Q : ATMEL_HLCDC_LAYER_EN));
> + if (!(dc->is_xlcdc)) {
> + /* Enable the overrun interrupts. */
> + atmel_hlcdc_layer_write_reg(&plane->layer, ATMEL_HLCDC_LAYER_IER,
> + ATMEL_HLCDC_LAYER_OVR_IRQ(0) |
> + ATMEL_HLCDC_LAYER_OVR_IRQ(1) |
> + ATMEL_HLCDC_LAYER_OVR_IRQ(2));
> +
> + /* Apply the new config at the next SOF event. */
> + sr = atmel_hlcdc_layer_read_reg(&plane->layer, ATMEL_HLCDC_LAYER_CHSR);
> + atmel_hlcdc_layer_write_reg(&plane->layer, ATMEL_HLCDC_LAYER_CHER,
> + ATMEL_HLCDC_LAYER_UPDATE |
> + (sr & ATMEL_HLCDC_LAYER_EN ?
> + ATMEL_HLCDC_LAYER_A2Q : ATMEL_HLCDC_LAYER_EN));
> + } else {
> + /* Enable the overrun interrupts. */
> + atmel_hlcdc_layer_write_reg(&plane->layer, ATMEL_XLCDC_LAYER_IER,
> + ATMEL_XLCDC_LAYER_OVR_IRQ(0) |
> + ATMEL_XLCDC_LAYER_OVR_IRQ(1) |
> + ATMEL_XLCDC_LAYER_OVR_IRQ(2));
> +
> + atmel_hlcdc_layer_write_reg(&plane->layer, ATMEL_XLCDC_LAYER_ENR,
> + ATMEL_XLCDC_LAYER_EN);
> + }
> +
> + /*
> + * Updating XLCDC_xxxCFGx, XLCDC_xxxFBA and XLCDC_xxxEN,
> + * (where xxx indicates each layer) requires writing one to the
> + * Update Attribute field for each layer in LCDC_ATTRE register for SAM9X7.
> + */
> + if (dc->is_xlcdc) {
> + regmap_write(dc->hlcdc->regmap, ATMEL_XLCDC_ATTRE, ATMEL_XLCDC_BASE_UPDATE |
> + ATMEL_XLCDC_OVR1_UPDATE | ATMEL_XLCDC_OVR3_UPDATE |
> + ATMEL_XLCDC_HEO_UPDATE);
> + }
> }
Likewise.

>
> static int atmel_hlcdc_plane_init_properties(struct atmel_hlcdc_plane *plane)
> {
> const struct atmel_hlcdc_layer_desc *desc = plane->layer.desc;
> + struct atmel_hlcdc_dc *dc = plane->base.dev->dev_private;
>
> if (desc->type == ATMEL_HLCDC_OVERLAY_LAYER ||
> desc->type == ATMEL_HLCDC_CURSOR_LAYER) {
> @@ -796,20 +917,50 @@ static int atmel_hlcdc_plane_init_properties(struct atmel_hlcdc_plane *plane)
> return ret;
> }
>
> - if (desc->layout.csc) {
> + if (!(dc->is_xlcdc)) {
> + if (desc->layout.csc) {
> + /*
> + * TODO: decare a "yuv-to-rgb-conv-factors" property to let
> + * userspace modify these factors (using a BLOB property ?).
> + */
> + atmel_hlcdc_layer_write_cfg(&plane->layer,
> + desc->layout.csc,
> + 0x4c900091);
> + atmel_hlcdc_layer_write_cfg(&plane->layer,
> + desc->layout.csc + 1,
> + 0x7a5f5090);
> + atmel_hlcdc_layer_write_cfg(&plane->layer,
> + desc->layout.csc + 2,
> + 0x40040890);
> + }
> + } else {
> /*
> - * TODO: decare a "yuv-to-rgb-conv-factors" property to let
> - * userspace modify these factors (using a BLOB property ?).
> + * yuv-to-rgb-conv-factors are now defined from LCDC_HEOCFG16 to
> + * LCDC_HEOCFG21 registers in SAM9X7.
> */
> - atmel_hlcdc_layer_write_cfg(&plane->layer,
> - desc->layout.csc,
> - 0x4c900091);
> - atmel_hlcdc_layer_write_cfg(&plane->layer,
> - desc->layout.csc + 1,
> - 0x7a5f5090);
> - atmel_hlcdc_layer_write_cfg(&plane->layer,
> - desc->layout.csc + 2,
> - 0x40040890);
> + if (desc->layout.csc) {
> + atmel_hlcdc_layer_write_cfg(&plane->layer,
> + desc->layout.csc,
> + 0x00000488);
> + atmel_hlcdc_layer_write_cfg(&plane->layer,
> + desc->layout.csc + 1,
> + 0x00000648);
> + atmel_hlcdc_layer_write_cfg(&plane->layer,
> + desc->layout.csc + 2,
> + 0x1EA00480);
> + atmel_hlcdc_layer_write_cfg(&plane->layer,
> + desc->layout.csc + 3,
> + 0x00001D28);
> + atmel_hlcdc_layer_write_cfg(&plane->layer,
> + desc->layout.csc + 4,
> + 0x08100480);
> + atmel_hlcdc_layer_write_cfg(&plane->layer,
> + desc->layout.csc + 5,
> + 0x00000000);
> + atmel_hlcdc_layer_write_cfg(&plane->layer,
> + desc->layout.csc + 6,
> + 0x00000007);
> + }

Refactor in two helpers?
atmel_xlcdc_layout_csc()
atmel_hlcdc_layout_csc()

> }
>
> return 0;
> @@ -819,19 +970,31 @@ void atmel_hlcdc_plane_irq(struct atmel_hlcdc_plane *plane)
> {
> const struct atmel_hlcdc_layer_desc *desc = plane->layer.desc;
> u32 isr;
> + struct atmel_hlcdc_dc *dc = plane->base.dev->dev_private;
>
> - isr = atmel_hlcdc_layer_read_reg(&plane->layer, ATMEL_HLCDC_LAYER_ISR);
> + if (!(dc->is_xlcdc))
> + isr = atmel_hlcdc_layer_read_reg(&plane->layer, ATMEL_HLCDC_LAYER_ISR);
> + else
> + isr = atmel_hlcdc_layer_read_reg(&plane->layer, ATMEL_XLCDC_LAYER_ISR);
>
> /*
> * There's not much we can do in case of overrun except informing
> * the user. However, we are in interrupt context here, hence the
> * use of dev_dbg().
> */
> - if (isr &
> - (ATMEL_HLCDC_LAYER_OVR_IRQ(0) | ATMEL_HLCDC_LAYER_OVR_IRQ(1) |
> - ATMEL_HLCDC_LAYER_OVR_IRQ(2)))
> - dev_dbg(plane->base.dev->dev, "overrun on plane %s\n",
> - desc->name);
> + if (!(dc->is_xlcdc)) {
> + if (isr &
> + (ATMEL_HLCDC_LAYER_OVR_IRQ(0) | ATMEL_HLCDC_LAYER_OVR_IRQ(1) |
> + ATMEL_HLCDC_LAYER_OVR_IRQ(2)))
> + dev_dbg(plane->base.dev->dev, "overrun on plane %s\n",
> + desc->name);
> + } else {
> + if (isr &
> + (ATMEL_XLCDC_LAYER_OVR_IRQ(0) | ATMEL_XLCDC_LAYER_OVR_IRQ(1) |
> + ATMEL_XLCDC_LAYER_OVR_IRQ(2)))
> + dev_dbg(plane->base.dev->dev, "overrun on plane %s\n",
> + desc->name);
> + }
> }
Again, split up in two functions. Maybe decide which to call in
atmel_hlcdc_layer_irq()
>
> static const struct drm_plane_helper_funcs atmel_hlcdc_layer_plane_helper_funcs = {
> --
> 2.25.1