This patch serises are to add PLL clocks driver and providers by writing
and reading syscon registers for the StarFive JH7110 RISC-V SoC. And add
documentation and nodes to describe StarFive System Controller(syscon)
Registers. This patch serises are based on Linux 6.4-rc1.
PLL are high speed, low jitter frequency synthesizers in JH7110.
Each PLL clocks work in integer mode or fraction mode by some dividers,
and the dividers are set in several syscon registers.
The formula for calculating frequency is:
Fvco = Fref * (NI + NF) / M / Q1
The first patch adds docunmentation to describe PLL clock bindings,
and the second patch adds documentation to decribe syscon registers.
The patch 3 modifies the SYSCRG dibindings and adds PLL clock inputs.
The patch 4 adds driver to support PLL clocks for JH7110.
The patch 5 modifies the system clock driver and can select the PLL clock
source from PLL clocks driver. And the patch 6 adds the
stg/sys/aon syscon nodes for JH7110 SoC. The last patch modifies the
syscrg node in JH7110 dts file.
Changes since v4:
- Rebased on Linux 6.4-rc6.
- Patch 2 dropped the example node about sys-syscon.
- Patch 3 used PLL clocks as one of optional items in SYSCRG bindings.
- Patch 4 used the patch instead about PLL clocks driver from Emil.
- Patch 5 retained the fixed factor PLL clocks as the optional source
about PLL clocks in SYSCRG clock driver.
- Patch 6 added the child node clock-controller as the complete
sys-syscon node and patch 7 dropped this part.
v4: https://lore.kernel.org/all/[email protected]/
Changes since v3:
- Rebased on Linux 6.4-rc1.
- Dropped the 'power-controller' property and used 'power-domain-cells'
instead in syscon binding.
- Used the data by of_device_id to get the syscon registers'
configuration include offset, mask and shift.
v3: https://lore.kernel.org/all/[email protected]/
Changes since v2:
- Rebased on latest JH7110 basic clock drivers.
- Added the complete documentation to describe syscon register.
- Added syscon node in JH7110 dts file.
- Modified the clock rate selection to match the closest rate in
PLL driver when setting rate.
v2: https://lore.kernel.org/all/[email protected]/
Changes since v1:
- Changed PLL clock node to be child of syscon node in dts.
- Modifed the definitions and names of function in PLL clock driver.
- Added commit to update syscon and syscrg dt-bindings.
v1: https://lore.kernel.org/all/[email protected]/
William Qiu (2):
dt-bindings: soc: starfive: Add StarFive syscon module
riscv: dts: starfive: jh7110: Add syscon nodes
Xingyu Wu (5):
dt-bindings: clock: Add StarFive JH7110 PLL clock generator
dt-bindings: clock: jh7110-syscrg: Add PLL clock inputs
clk: starfive: Add StarFive JH7110 PLL clock driver
clk: starfive: jh7110-sys: Add PLL clocks source from DTS
riscv: dts: starfive: jh7110: Add PLL clock source in SYSCRG node
.../bindings/clock/starfive,jh7110-pll.yaml | 46 ++
.../clock/starfive,jh7110-syscrg.yaml | 56 ++
.../soc/starfive/starfive,jh7110-syscon.yaml | 62 +++
MAINTAINERS | 13 +
arch/riscv/boot/dts/starfive/jh7110.dtsi | 30 +-
drivers/clk/starfive/Kconfig | 9 +
drivers/clk/starfive/Makefile | 1 +
.../clk/starfive/clk-starfive-jh7110-pll.c | 507 ++++++++++++++++++
.../clk/starfive/clk-starfive-jh7110-sys.c | 45 +-
.../dt-bindings/clock/starfive,jh7110-crg.h | 6 +
10 files changed, 755 insertions(+), 20 deletions(-)
create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh7110-pll.yaml
create mode 100644 Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
create mode 100644 drivers/clk/starfive/clk-starfive-jh7110-pll.c
--
2.25.1
Add optional PLL clock inputs from PLL clock generator.
Signed-off-by: Xingyu Wu <[email protected]>
---
.../clock/starfive,jh7110-syscrg.yaml | 56 +++++++++++++++++++
1 file changed, 56 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml b/Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml
index 84373ae31644..5536e5f9e20b 100644
--- a/Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml
+++ b/Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml
@@ -39,6 +39,33 @@ properties:
- description: External TDM clock
- description: External audio master clock
+ - items:
+ - description: Main Oscillator (24 MHz)
+ - description: GMAC1 RMII reference or GMAC1 RGMII RX
+ - description: External I2S TX bit clock
+ - description: External I2S TX left/right channel clock
+ - description: External I2S RX bit clock
+ - description: External I2S RX left/right channel clock
+ - description: External TDM clock
+ - description: External audio master clock
+ - description: PLL0
+ - description: PLL1
+ - description: PLL2
+
+ - items:
+ - description: Main Oscillator (24 MHz)
+ - description: GMAC1 RMII reference
+ - description: GMAC1 RGMII RX
+ - description: External I2S TX bit clock
+ - description: External I2S TX left/right channel clock
+ - description: External I2S RX bit clock
+ - description: External I2S RX left/right channel clock
+ - description: External TDM clock
+ - description: External audio master clock
+ - description: PLL0
+ - description: PLL1
+ - description: PLL2
+
clock-names:
oneOf:
- items:
@@ -64,6 +91,35 @@ properties:
- const: tdm_ext
- const: mclk_ext
+ - items:
+ - const: osc
+ - enum:
+ - gmac1_rmii_refin
+ - gmac1_rgmii_rxin
+ - const: i2stx_bclk_ext
+ - const: i2stx_lrck_ext
+ - const: i2srx_bclk_ext
+ - const: i2srx_lrck_ext
+ - const: tdm_ext
+ - const: mclk_ext
+ - const: pll0_out
+ - const: pll1_out
+ - const: pll2_out
+
+ - items:
+ - const: osc
+ - const: gmac1_rmii_refin
+ - const: gmac1_rgmii_rxin
+ - const: i2stx_bclk_ext
+ - const: i2stx_lrck_ext
+ - const: i2srx_bclk_ext
+ - const: i2srx_lrck_ext
+ - const: tdm_ext
+ - const: mclk_ext
+ - const: pll0_out
+ - const: pll1_out
+ - const: pll2_out
+
'#clock-cells':
const: 1
description:
--
2.25.1
Add bindings for the PLL clock generator on the JH7110 RISC-V SoC.
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Signed-off-by: Xingyu Wu <[email protected]>
---
.../bindings/clock/starfive,jh7110-pll.yaml | 46 +++++++++++++++++++
.../dt-bindings/clock/starfive,jh7110-crg.h | 6 +++
2 files changed, 52 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh7110-pll.yaml
diff --git a/Documentation/devicetree/bindings/clock/starfive,jh7110-pll.yaml b/Documentation/devicetree/bindings/clock/starfive,jh7110-pll.yaml
new file mode 100644
index 000000000000..8aa8c7b8e42f
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/starfive,jh7110-pll.yaml
@@ -0,0 +1,46 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/starfive,jh7110-pll.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: StarFive JH7110 PLL Clock Generator
+
+description:
+ This PLL are high speed, low jitter frequency synthesizers in JH7110.
+ Each PLL clocks work in integer mode or fraction mode by some dividers,
+ and the configuration registers and dividers are set in several syscon
+ registers. So pll node should be a child of SYS-SYSCON node.
+ The formula for calculating frequency is that,
+ Fvco = Fref * (NI + NF) / M / Q1
+
+maintainers:
+ - Xingyu Wu <[email protected]>
+
+properties:
+ compatible:
+ const: starfive,jh7110-pll
+
+ clocks:
+ maxItems: 1
+ description: Main Oscillator (24 MHz)
+
+ '#clock-cells':
+ const: 1
+ description:
+ See <dt-bindings/clock/starfive,jh7110-crg.h> for valid indices.
+
+required:
+ - compatible
+ - clocks
+ - '#clock-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ pll-clock-controller {
+ compatible = "starfive,jh7110-pll";
+ clocks = <&osc>;
+ #clock-cells = <1>;
+ };
diff --git a/include/dt-bindings/clock/starfive,jh7110-crg.h b/include/dt-bindings/clock/starfive,jh7110-crg.h
index 06257bfd9ac1..086a6ddcf380 100644
--- a/include/dt-bindings/clock/starfive,jh7110-crg.h
+++ b/include/dt-bindings/clock/starfive,jh7110-crg.h
@@ -6,6 +6,12 @@
#ifndef __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CRG_H__
#define __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CRG_H__
+/* PLL clocks */
+#define JH7110_CLK_PLL0_OUT 0
+#define JH7110_CLK_PLL1_OUT 1
+#define JH7110_CLK_PLL2_OUT 2
+#define JH7110_PLLCLK_END 3
+
/* SYSCRG clocks */
#define JH7110_SYSCLK_CPU_ROOT 0
#define JH7110_SYSCLK_CPU_CORE 1
--
2.25.1
From: William Qiu <[email protected]>
Add stg_syscon/sys_syscon/aon_syscon/PLL nodes for JH7110 Soc.
Co-developed-by: Xingyu Wu <[email protected]>
Signed-off-by: Xingyu Wu <[email protected]>
Signed-off-by: William Qiu <[email protected]>
---
arch/riscv/boot/dts/starfive/jh7110.dtsi | 22 ++++++++++++++++++++++
1 file changed, 22 insertions(+)
diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
index 4c5fdb905da8..11dd4c9d64b0 100644
--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
@@ -353,6 +353,11 @@ i2c2: i2c@10050000 {
status = "disabled";
};
+ stg_syscon: syscon@10240000 {
+ compatible = "starfive,jh7110-stg-syscon", "syscon";
+ reg = <0x0 0x10240000 0x0 0x1000>;
+ };
+
uart3: serial@12000000 {
compatible = "snps,dw-apb-uart";
reg = <0x0 0x12000000 0x0 0x10000>;
@@ -457,6 +462,17 @@ syscrg: clock-controller@13020000 {
#reset-cells = <1>;
};
+ sys_syscon: syscon@13030000 {
+ compatible = "starfive,jh7110-sys-syscon", "syscon", "simple-mfd";
+ reg = <0x0 0x13030000 0x0 0x1000>;
+
+ pllclk: clock-controller {
+ compatible = "starfive,jh7110-pll";
+ clocks = <&osc>;
+ #clock-cells = <1>;
+ };
+ };
+
sysgpio: pinctrl@13040000 {
compatible = "starfive,jh7110-sys-pinctrl";
reg = <0x0 0x13040000 0x0 0x10000>;
@@ -486,6 +502,12 @@ aoncrg: clock-controller@17000000 {
#reset-cells = <1>;
};
+ aon_syscon: syscon@17010000 {
+ compatible = "starfive,jh7110-aon-syscon", "syscon";
+ reg = <0x0 0x17010000 0x0 0x1000>;
+ #power-domain-cells = <1>;
+ };
+
aongpio: pinctrl@17020000 {
compatible = "starfive,jh7110-aon-pinctrl";
reg = <0x0 0x17020000 0x0 0x10000>;
--
2.25.1
From: William Qiu <[email protected]>
Add documentation to describe StarFive System Controller Registers.
Co-developed-by: Xingyu Wu <[email protected]>
Signed-off-by: Xingyu Wu <[email protected]>
Signed-off-by: William Qiu <[email protected]>
---
.../soc/starfive/starfive,jh7110-syscon.yaml | 62 +++++++++++++++++++
MAINTAINERS | 7 +++
2 files changed, 69 insertions(+)
create mode 100644 Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
diff --git a/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml b/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
new file mode 100644
index 000000000000..a81190f8a54d
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
@@ -0,0 +1,62 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/starfive/starfive,jh7110-syscon.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: StarFive JH7110 SoC system controller
+
+maintainers:
+ - William Qiu <[email protected]>
+
+description: |
+ The StarFive JH7110 SoC system controller provides register information such
+ as offset, mask and shift to configure related modules such as MMC and PCIe.
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - const: starfive,jh7110-sys-syscon
+ - const: syscon
+ - const: simple-mfd
+ - items:
+ - enum:
+ - starfive,jh7110-aon-syscon
+ - starfive,jh7110-stg-syscon
+ - const: syscon
+
+ reg:
+ maxItems: 1
+
+ clock-controller:
+ $ref: /schemas/clock/starfive,jh7110-pll.yaml#
+ type: object
+
+ "#power-domain-cells":
+ const: 1
+
+required:
+ - compatible
+ - reg
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: starfive,jh7110-aon-syscon
+ then:
+ required:
+ - "#power-domain-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ syscon@10240000 {
+ compatible = "starfive,jh7110-stg-syscon", "syscon";
+ reg = <0x10240000 0x1000>;
+ };
+
+...
diff --git a/MAINTAINERS b/MAINTAINERS
index f794002a192e..ae037ba7fc47 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -20122,6 +20122,12 @@ S: Supported
F: Documentation/devicetree/bindings/mmc/starfive*
F: drivers/mmc/host/dw_mmc-starfive.c
+STARFIVE JH7110 SYSCON
+M: William Qiu <[email protected]>
+M: Xingyu Wu <[email protected]>
+S: Supported
+F: Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
+
STARFIVE JH71X0 CLOCK DRIVERS
M: Emil Renner Berthing <[email protected]>
M: Hal Feng <[email protected]>
@@ -20159,6 +20165,7 @@ STARFIVE SOC DRIVERS
M: Conor Dooley <[email protected]>
S: Maintained
T: git https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/
+F: Documentation/devicetree/bindings/soc/starfive/
F: drivers/soc/starfive/
STARFIVE TRNG DRIVER
--
2.25.1
Modify PLL clocks source to be got from DTS or
the fixed factor clocks.
Signed-off-by: Xingyu Wu <[email protected]>
---
drivers/clk/starfive/Kconfig | 1 +
.../clk/starfive/clk-starfive-jh7110-sys.c | 45 +++++++++++--------
2 files changed, 28 insertions(+), 18 deletions(-)
diff --git a/drivers/clk/starfive/Kconfig b/drivers/clk/starfive/Kconfig
index 5195f7be5213..978b78ec08b1 100644
--- a/drivers/clk/starfive/Kconfig
+++ b/drivers/clk/starfive/Kconfig
@@ -35,6 +35,7 @@ config CLK_STARFIVE_JH7110_SYS
select AUXILIARY_BUS
select CLK_STARFIVE_JH71X0
select RESET_STARFIVE_JH7110 if RESET_CONTROLLER
+ select CLK_STARFIVE_JH7110_PLL
default ARCH_STARFIVE
help
Say yes here to support the system clock controller on the
diff --git a/drivers/clk/starfive/clk-starfive-jh7110-sys.c b/drivers/clk/starfive/clk-starfive-jh7110-sys.c
index e6031345ef05..d56f48013388 100644
--- a/drivers/clk/starfive/clk-starfive-jh7110-sys.c
+++ b/drivers/clk/starfive/clk-starfive-jh7110-sys.c
@@ -7,6 +7,7 @@
*/
#include <linux/auxiliary_bus.h>
+#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/init.h>
#include <linux/io.h>
@@ -386,6 +387,7 @@ EXPORT_SYMBOL_GPL(jh7110_reset_controller_register);
static int __init jh7110_syscrg_probe(struct platform_device *pdev)
{
+ bool use_fixed_pll = true; /* PLL clocks use fixed factor clocks or PLL driver */
struct jh71x0_clk_priv *priv;
unsigned int idx;
int ret;
@@ -402,28 +404,29 @@ static int __init jh7110_syscrg_probe(struct platform_device *pdev)
if (IS_ERR(priv->base))
return PTR_ERR(priv->base);
- /*
- * These PLL clocks are not actually fixed factor clocks and can be
- * controlled by the syscon registers of JH7110. They will be dropped
- * and registered in the PLL clock driver instead.
- */
+ if (!IS_ERR(devm_clk_get(priv->dev, "pll0_out")))
+ use_fixed_pll = false; /* can get pll clocks from PLL driver */
+
+ /* Use fixed factor clocks if can not get the PLL clocks from DTS */
+ if (use_fixed_pll) {
/* 24MHz -> 1000.0MHz */
- priv->pll[0] = devm_clk_hw_register_fixed_factor(priv->dev, "pll0_out",
- "osc", 0, 125, 3);
- if (IS_ERR(priv->pll[0]))
- return PTR_ERR(priv->pll[0]);
+ priv->pll[0] = devm_clk_hw_register_fixed_factor(priv->dev, "pll0_out",
+ "osc", 0, 125, 3);
+ if (IS_ERR(priv->pll[0]))
+ return PTR_ERR(priv->pll[0]);
/* 24MHz -> 1066.0MHz */
- priv->pll[1] = devm_clk_hw_register_fixed_factor(priv->dev, "pll1_out",
- "osc", 0, 533, 12);
- if (IS_ERR(priv->pll[1]))
- return PTR_ERR(priv->pll[1]);
+ priv->pll[1] = devm_clk_hw_register_fixed_factor(priv->dev, "pll1_out",
+ "osc", 0, 533, 12);
+ if (IS_ERR(priv->pll[1]))
+ return PTR_ERR(priv->pll[1]);
/* 24MHz -> 1188.0MHz */
- priv->pll[2] = devm_clk_hw_register_fixed_factor(priv->dev, "pll2_out",
- "osc", 0, 99, 2);
- if (IS_ERR(priv->pll[2]))
- return PTR_ERR(priv->pll[2]);
+ priv->pll[2] = devm_clk_hw_register_fixed_factor(priv->dev, "pll2_out",
+ "osc", 0, 99, 2);
+ if (IS_ERR(priv->pll[2]))
+ return PTR_ERR(priv->pll[2]);
+ }
for (idx = 0; idx < JH7110_SYSCLK_END; idx++) {
u32 max = jh7110_sysclk_data[idx].max;
@@ -462,8 +465,14 @@ static int __init jh7110_syscrg_probe(struct platform_device *pdev)
parents[i].fw_name = "tdm_ext";
else if (pidx == JH7110_SYSCLK_MCLK_EXT)
parents[i].fw_name = "mclk_ext";
- else
+ else if (use_fixed_pll)
parents[i].hw = priv->pll[pidx - JH7110_SYSCLK_PLL0_OUT];
+ else if (pidx == JH7110_SYSCLK_PLL0_OUT)
+ parents[i].fw_name = "pll0_out";
+ else if (pidx == JH7110_SYSCLK_PLL1_OUT)
+ parents[i].fw_name = "pll1_out";
+ else if (pidx == JH7110_SYSCLK_PLL2_OUT)
+ parents[i].fw_name = "pll2_out";
}
clk->hw.init = &init;
--
2.25.1
Modify the SYSCRG node to add PLL clocks input from
PLL clocks driver.
Signed-off-by: Xingyu Wu <[email protected]>
---
arch/riscv/boot/dts/starfive/jh7110.dtsi | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
index 11dd4c9d64b0..cdfd036a0e6c 100644
--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
@@ -452,12 +452,16 @@ syscrg: clock-controller@13020000 {
<&gmac1_rgmii_rxin>,
<&i2stx_bclk_ext>, <&i2stx_lrck_ext>,
<&i2srx_bclk_ext>, <&i2srx_lrck_ext>,
- <&tdm_ext>, <&mclk_ext>;
+ <&tdm_ext>, <&mclk_ext>,
+ <&pllclk JH7110_CLK_PLL0_OUT>,
+ <&pllclk JH7110_CLK_PLL1_OUT>,
+ <&pllclk JH7110_CLK_PLL2_OUT>;
clock-names = "osc", "gmac1_rmii_refin",
"gmac1_rgmii_rxin",
"i2stx_bclk_ext", "i2stx_lrck_ext",
"i2srx_bclk_ext", "i2srx_lrck_ext",
- "tdm_ext", "mclk_ext";
+ "tdm_ext", "mclk_ext",
+ "pll0_out", "pll1_out", "pll2_out";
#clock-cells = <1>;
#reset-cells = <1>;
};
--
2.25.1
On 13/06/2023 14:58, Xingyu Wu wrote:
> Add optional PLL clock inputs from PLL clock generator.
Are you sure that PLLs are optional? Usually they are not...
>
> Signed-off-by: Xingyu Wu <[email protected]>
> ---
> .../clock/starfive,jh7110-syscrg.yaml | 56 +++++++++++++++++++
> 1 file changed, 56 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml b/Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml
> index 84373ae31644..5536e5f9e20b 100644
> --- a/Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml
> +++ b/Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml
> @@ -39,6 +39,33 @@ properties:
> - description: External TDM clock
> - description: External audio master clock
>
> + - items:
> + - description: Main Oscillator (24 MHz)
> + - description: GMAC1 RMII reference or GMAC1 RGMII RX
> + - description: External I2S TX bit clock
> + - description: External I2S TX left/right channel clock
> + - description: External I2S RX bit clock
> + - description: External I2S RX left/right channel clock
> + - description: External TDM clock
> + - description: External audio master clock
> + - description: PLL0
> + - description: PLL1
> + - description: PLL2
Add these three to the existing entry with minItems.
> +
> + - items:
> + - description: Main Oscillator (24 MHz)
> + - description: GMAC1 RMII reference
> + - description: GMAC1 RGMII RX
> + - description: External I2S TX bit clock
> + - description: External I2S TX left/right channel clock
> + - description: External I2S RX bit clock
> + - description: External I2S RX left/right channel clock
> + - description: External TDM clock
> + - description: External audio master clock
> + - description: PLL0
> + - description: PLL1
> + - description: PLL2
Add these three to the existing entry with minItems.
> +
> clock-names:
> oneOf:
> - items:
> @@ -64,6 +91,35 @@ properties:
> - const: tdm_ext
> - const: mclk_ext
>
> + - items:
> + - const: osc
> + - enum:
> + - gmac1_rmii_refin
> + - gmac1_rgmii_rxin
> + - const: i2stx_bclk_ext
> + - const: i2stx_lrck_ext
> + - const: i2srx_bclk_ext
> + - const: i2srx_lrck_ext
> + - const: tdm_ext
> + - const: mclk_ext
> + - const: pll0_out
> + - const: pll1_out
> + - const: pll2_out
Add these three to the existing entry with minItems.
> +
> + - items:
> + - const: osc
> + - const: gmac1_rmii_refin
> + - const: gmac1_rgmii_rxin
> + - const: i2stx_bclk_ext
> + - const: i2stx_lrck_ext
> + - const: i2srx_bclk_ext
> + - const: i2srx_lrck_ext
> + - const: tdm_ext
> + - const: mclk_ext
> + - const: pll0_out
> + - const: pll1_out
> + - const: pll2_out
Add these three to the existing entry with minItems.
Best regards,
Krzysztof
On 13/06/2023 14:58, Xingyu Wu wrote:
> From: William Qiu <[email protected]>
>
> Add documentation to describe StarFive System Controller Registers.
>
> Co-developed-by: Xingyu Wu <[email protected]>
> Signed-off-by: Xingyu Wu <[email protected]>
> Signed-off-by: William Qiu <[email protected]>
> ---
> .../soc/starfive/starfive,jh7110-syscon.yaml | 62 +++++++++++++++++++
> MAINTAINERS | 7 +++
> 2 files changed, 69 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
>
> diff --git a/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml b/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
> new file mode 100644
> index 000000000000..a81190f8a54d
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
> @@ -0,0 +1,62 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/soc/starfive/starfive,jh7110-syscon.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: StarFive JH7110 SoC system controller
> +
> +maintainers:
> + - William Qiu <[email protected]>
> +
> +description: |
Do not need '|' unless you need to preserve formatting.
> + The StarFive JH7110 SoC system controller provides register information such
> + as offset, mask and shift to configure related modules such as MMC and PCIe.
> +
> +properties:
> + compatible:
> + oneOf:
> + - items:
> + - const: starfive,jh7110-sys-syscon
> + - const: syscon
> + - const: simple-mfd
> + - items:
> + - enum:
> + - starfive,jh7110-aon-syscon
> + - starfive,jh7110-stg-syscon
> + - const: syscon
> +
> + reg:
> + maxItems: 1
> +
> + clock-controller:
> + $ref: /schemas/clock/starfive,jh7110-pll.yaml#
> + type: object
> +
> + "#power-domain-cells":
> + const: 1
> +
> +required:
> + - compatible
> + - reg
> +
> +allOf:
> + - if:
> + properties:
> + compatible:
> + contains:
> + const: starfive,jh7110-aon-syscon
> + then:
> + required:
> + - "#power-domain-cells"
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + syscon@10240000 {
> + compatible = "starfive,jh7110-stg-syscon", "syscon";
> + reg = <0x10240000 0x1000>;
Extend example - add clock controller, add power-domains to STG (since
it has them, as you claim in the binding).
Make this one example complete.
Best regards,
Krzysztof
On 13/06/2023 14:58, Xingyu Wu wrote:
> From: William Qiu <[email protected]>
>
> Add documentation to describe StarFive System Controller Registers.
>
> Co-developed-by: Xingyu Wu <[email protected]>
> Signed-off-by: Xingyu Wu <[email protected]>
> Signed-off-by: William Qiu <[email protected]>
> ---
> .../soc/starfive/starfive,jh7110-syscon.yaml | 62 +++++++++++++++++++
> MAINTAINERS | 7 +++
> 2 files changed, 69 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
>
> diff --git a/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml b/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
> new file mode 100644
> index 000000000000..a81190f8a54d
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
> @@ -0,0 +1,62 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/soc/starfive/starfive,jh7110-syscon.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: StarFive JH7110 SoC system controller
> +
> +maintainers:
> + - William Qiu <[email protected]>
> +
> +description: |
> + The StarFive JH7110 SoC system controller provides register information such
> + as offset, mask and shift to configure related modules such as MMC and PCIe.
> +
> +properties:
> + compatible:
> + oneOf:
> + - items:
> + - const: starfive,jh7110-sys-syscon
> + - const: syscon
> + - const: simple-mfd
> + - items:
> + - enum:
> + - starfive,jh7110-aon-syscon
> + - starfive,jh7110-stg-syscon
> + - const: syscon
> +
> + reg:
> + maxItems: 1
> +
> + clock-controller:
> + $ref: /schemas/clock/starfive,jh7110-pll.yaml#
> + type: object
> +
> + "#power-domain-cells":
> + const: 1
> +
> +required:
> + - compatible
> + - reg
> +
> +allOf:
> + - if:
> + properties:
> + compatible:
> + contains:
> + const: starfive,jh7110-aon-syscon
> + then:
> + required:
> + - "#power-domain-cells"
Where did you implement the results of the discussion that only some
devices can have power and clock controller?
According to your code all of above - sys, aon and stg - have clock and
power controllers. If not, then the code is not correct, so please do
not respond with what is where (like you did last time) but actually
implement what you say.
Best regards,
Krzysztof
Hey Xingyu,
Couple nitpick items to be fixed if you resubmit.
On Tue, Jun 13, 2023 at 08:58:46PM +0800, Xingyu Wu wrote:
> + This PLL are high speed, low jitter frequency synthesizers in JH7110.
nit: These PLLs are
> + Each PLL clocks work in integer mode or fraction mode by some dividers,
> + and the configuration registers and dividers are set in several syscon
> + registers. So pll node should be a child of SYS-SYSCON node.
nit: Each PLL can work in integer or fractional mode, with controlled by
configuration registers in the sys syscon.
> + The formula for calculating frequency is that,
nit: s/ that//
> +examples:
> + - |
> + pll-clock-controller {
nit: s/pll-//
> diff --git a/include/dt-bindings/clock/starfive,jh7110-crg.h b/include/dt-bindings/clock/starfive,jh7110-crg.h
> index 06257bfd9ac1..086a6ddcf380 100644
> --- a/include/dt-bindings/clock/starfive,jh7110-crg.h
> +++ b/include/dt-bindings/clock/starfive,jh7110-crg.h
> @@ -6,6 +6,12 @@
> #ifndef __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CRG_H__
> #define __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CRG_H__
>
> +/* PLL clocks */
> +#define JH7110_CLK_PLL0_OUT 0
> +#define JH7110_CLK_PLL1_OUT 1
> +#define JH7110_CLK_PLL2_OUT 2
> +#define JH7110_PLLCLK_END 3
Please CC me on the patches fixing this for U-Boot :)
Nitpicking aside, which only needs to be fixed if you end up submitting
a new version for other reasons,
Reviewed-by: Conor Dooley <[email protected]>
Thanks,
Conor.
On Tue, Jun 13, 2023 at 08:34:25PM +0200, Krzysztof Kozlowski wrote:
> On 13/06/2023 14:58, Xingyu Wu wrote:
> > Add optional PLL clock inputs from PLL clock generator.
>
> Are you sure that PLLs are optional? Usually they are not...
They're not. What's happening here is the original binding was defined
without these clocks (obviously, since they're only being added now) so
for the driver they are still "optional" to keep compatibility.
In mainline, the driver takes the "osc" input and registers some
fixed-factor clocks to mimic these PLLs & after this patchset that is
only done as a fallback if the clock inputs to the clock controller,
from the PLLs, are missing.
They should not be optional in the dt-binding because they're not
optional in the hardware afaik!
Cheers,
Conor.
On Tue, Jun 13, 2023 at 08:58:51PM +0800, Xingyu Wu wrote:
> From: William Qiu <[email protected]>
>
> Add stg_syscon/sys_syscon/aon_syscon/PLL nodes for JH7110 Soc.
>
> Co-developed-by: Xingyu Wu <[email protected]>
> Signed-off-by: Xingyu Wu <[email protected]>
> Signed-off-by: William Qiu <[email protected]>
Reviewed-by: Conor Dooley <[email protected]>
Thanks,
Conor.
On Tue, Jun 13, 2023 at 08:58:52PM +0800, Xingyu Wu wrote:
> Modify the SYSCRG node to add PLL clocks input from
> PLL clocks driver.
>
> Signed-off-by: Xingyu Wu <[email protected]>
Reviewed-by: Conor Dooley <[email protected]>
Cheers,
Conor.
On 2023/6/14 2:31, Krzysztof Kozlowski wrote:
> On 13/06/2023 14:58, Xingyu Wu wrote:
>> From: William Qiu <[email protected]>
>>
>> Add documentation to describe StarFive System Controller Registers.
>>
>> Co-developed-by: Xingyu Wu <[email protected]>
>> Signed-off-by: Xingyu Wu <[email protected]>
>> Signed-off-by: William Qiu <[email protected]>
>> ---
>> .../soc/starfive/starfive,jh7110-syscon.yaml | 62 +++++++++++++++++++
>> MAINTAINERS | 7 +++
>> 2 files changed, 69 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
>>
>> diff --git a/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml b/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
>> new file mode 100644
>> index 000000000000..a81190f8a54d
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
>> @@ -0,0 +1,62 @@
>> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/soc/starfive/starfive,jh7110-syscon.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: StarFive JH7110 SoC system controller
>> +
>> +maintainers:
>> + - William Qiu <[email protected]>
>> +
>> +description: |
>> + The StarFive JH7110 SoC system controller provides register information such
>> + as offset, mask and shift to configure related modules such as MMC and PCIe.
>> +
>> +properties:
>> + compatible:
>> + oneOf:
>> + - items:
>> + - const: starfive,jh7110-sys-syscon
>> + - const: syscon
>> + - const: simple-mfd
>> + - items:
>> + - enum:
>> + - starfive,jh7110-aon-syscon
>> + - starfive,jh7110-stg-syscon
>> + - const: syscon
>> +
>> + reg:
>> + maxItems: 1
>> +
>> + clock-controller:
>> + $ref: /schemas/clock/starfive,jh7110-pll.yaml#
>> + type: object
>> +
>> + "#power-domain-cells":
>> + const: 1
>> +
>> +required:
>> + - compatible
>> + - reg
>> +
>> +allOf:
>> + - if:
>> + properties:
>> + compatible:
>> + contains:
>> + const: starfive,jh7110-aon-syscon
>> + then:
>> + required:
>> + - "#power-domain-cells"
>
> Where did you implement the results of the discussion that only some
> devices can have power and clock controller?
>
> According to your code all of above - sys, aon and stg - have clock and
> power controllers. If not, then the code is not correct, so please do
> not respond with what is where (like you did last time) but actually
> implement what you say.
>
Hi Krzysztof, I need to modify the code to implement it.
If I drop the 'clock-controller' and '"#power-domain-cells"' in properites, and change to this:
--- a/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
+++ b/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
@@ -29,28 +29,33 @@ properties:
reg:
maxItems: 1
- clock-controller:
- $ref: /schemas/clock/starfive,jh7110-pll.yaml#
- type: object
-
- "#power-domain-cells":
- const: 1
-
required:
- compatible
- reg
allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: starfive,jh7110-sys-syscon
+ then:
+ properties:
+ clock-controller:
+ $ref: /schemas/clock/starfive,jh7110-pll.yaml#
+ type: object
+
- if:
properties:
compatible:
contains:
const: starfive,jh7110-aon-syscon
then:
- required:
- - "#power-domain-cells"
+ properties:
+ "#power-domain-cells":
+ const: 1
-additionalProperties: false
+additionalProperties: true
Would it be better to show that sys-syscon only has clock-controller and aon-syscon is power controller?
Best regards,
Xingyu Wu
On Wed, Jun 28, 2023 at 02:44:10PM +0800, Xingyu Wu wrote:
> On 2023/6/14 2:31, Krzysztof Kozlowski wrote:
> > On 13/06/2023 14:58, Xingyu Wu wrote:
> >> From: William Qiu <[email protected]>
> >>
> >> Add documentation to describe StarFive System Controller Registers.
> >>
> >> Co-developed-by: Xingyu Wu <[email protected]>
> >> Signed-off-by: Xingyu Wu <[email protected]>
> >> Signed-off-by: William Qiu <[email protected]>
> >> ---
> >> .../soc/starfive/starfive,jh7110-syscon.yaml | 62 +++++++++++++++++++
> >> MAINTAINERS | 7 +++
> >> 2 files changed, 69 insertions(+)
> >> create mode 100644 Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
> >>
> >> diff --git a/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml b/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
> >> new file mode 100644
> >> index 000000000000..a81190f8a54d
> >> --- /dev/null
> >> +++ b/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
> >> @@ -0,0 +1,62 @@
> >> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> >> +%YAML 1.2
> >> +---
> >> +$id: http://devicetree.org/schemas/soc/starfive/starfive,jh7110-syscon.yaml#
> >> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> >> +
> >> +title: StarFive JH7110 SoC system controller
> >> +
> >> +maintainers:
> >> + - William Qiu <[email protected]>
> >> +
> >> +description: |
> >> + The StarFive JH7110 SoC system controller provides register information such
> >> + as offset, mask and shift to configure related modules such as MMC and PCIe.
> >> +
> >> +properties:
> >> + compatible:
> >> + oneOf:
> >> + - items:
> >> + - const: starfive,jh7110-sys-syscon
> >> + - const: syscon
> >> + - const: simple-mfd
> >> + - items:
> >> + - enum:
> >> + - starfive,jh7110-aon-syscon
> >> + - starfive,jh7110-stg-syscon
> >> + - const: syscon
> >> +
> >> + reg:
> >> + maxItems: 1
> >> +
> >> + clock-controller:
> >> + $ref: /schemas/clock/starfive,jh7110-pll.yaml#
> >> + type: object
> >> +
> >> + "#power-domain-cells":
> >> + const: 1
> >> +
> >> +required:
> >> + - compatible
> >> + - reg
> >> +
> >> +allOf:
> >> + - if:
> >> + properties:
> >> + compatible:
> >> + contains:
> >> + const: starfive,jh7110-aon-syscon
> >> + then:
> >> + required:
> >> + - "#power-domain-cells"
> >
> > Where did you implement the results of the discussion that only some
> > devices can have power and clock controller?
> >
> > According to your code all of above - sys, aon and stg - have clock and
> > power controllers. If not, then the code is not correct, so please do
> > not respond with what is where (like you did last time) but actually
> > implement what you say.
> >
>
> Hi Krzysztof, I need to modify the code to implement it.
> If I drop the 'clock-controller' and '"#power-domain-cells"' in properites, and change to this:
>
> --- a/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
> +++ b/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
> @@ -29,28 +29,33 @@ properties:
> reg:
> maxItems: 1
>
> - clock-controller:
> - $ref: /schemas/clock/starfive,jh7110-pll.yaml#
> - type: object
> -
> - "#power-domain-cells":
> - const: 1
> -
> required:
> - compatible
> - reg
>
> allOf:
> + - if:
> + properties:
> + compatible:
> + contains:
> + const: starfive,jh7110-sys-syscon
> + then:
> + properties:
> + clock-controller:
> + $ref: /schemas/clock/starfive,jh7110-pll.yaml#
> + type: object
Why do this?
Why not define the property has you have been doing, but only allow it
on the syscons that support it?
See the section starting at L205 of example-schema.yaml.
> +
> - if:
> properties:
> compatible:
> contains:
> const: starfive,jh7110-aon-syscon
> then:
> - required:
> - - "#power-domain-cells"
> + properties:
> + "#power-domain-cells":
> + const: 1
>
> -additionalProperties: false
> +additionalProperties: true
Why do you need this?
Allowing "additionalProperties: true" sounds like you've got some prblem
that you are trying to hide...
> Would it be better to show that sys-syscon only has clock-controller and aon-syscon is power controller?
You should only permit the properties where they are valid, yes.
Cheers,
Conor.
On 2023/6/29 1:34, Conor Dooley wrote:
> On Wed, Jun 28, 2023 at 02:44:10PM +0800, Xingyu Wu wrote:
>> On 2023/6/14 2:31, Krzysztof Kozlowski wrote:
>> > On 13/06/2023 14:58, Xingyu Wu wrote:
>> >> From: William Qiu <[email protected]>
>> >>
>> >> Add documentation to describe StarFive System Controller Registers.
>> >>
>> >> Co-developed-by: Xingyu Wu <[email protected]>
>> >> Signed-off-by: Xingyu Wu <[email protected]>
>> >> Signed-off-by: William Qiu <[email protected]>
>> >> ---
>> >> .../soc/starfive/starfive,jh7110-syscon.yaml | 62 +++++++++++++++++++
>> >> MAINTAINERS | 7 +++
>> >> 2 files changed, 69 insertions(+)
>> >> create mode 100644 Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
>> >>
>> >> diff --git a/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml b/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
>> >> new file mode 100644
>> >> index 000000000000..a81190f8a54d
>> >> --- /dev/null
>> >> +++ b/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
>> >> @@ -0,0 +1,62 @@
>> >> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
>> >> +%YAML 1.2
>> >> +---
>> >> +$id: http://devicetree.org/schemas/soc/starfive/starfive,jh7110-syscon.yaml#
>> >> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> >> +
>> >> +title: StarFive JH7110 SoC system controller
>> >> +
>> >> +maintainers:
>> >> + - William Qiu <[email protected]>
>> >> +
>> >> +description: |
>> >> + The StarFive JH7110 SoC system controller provides register information such
>> >> + as offset, mask and shift to configure related modules such as MMC and PCIe.
>> >> +
>> >> +properties:
>> >> + compatible:
>> >> + oneOf:
>> >> + - items:
>> >> + - const: starfive,jh7110-sys-syscon
>> >> + - const: syscon
>> >> + - const: simple-mfd
>> >> + - items:
>> >> + - enum:
>> >> + - starfive,jh7110-aon-syscon
>> >> + - starfive,jh7110-stg-syscon
>> >> + - const: syscon
>> >> +
>> >> + reg:
>> >> + maxItems: 1
>> >> +
>> >> + clock-controller:
>> >> + $ref: /schemas/clock/starfive,jh7110-pll.yaml#
>> >> + type: object
>> >> +
>> >> + "#power-domain-cells":
>> >> + const: 1
>> >> +
>> >> +required:
>> >> + - compatible
>> >> + - reg
>> >> +
>> >> +allOf:
>> >> + - if:
>> >> + properties:
>> >> + compatible:
>> >> + contains:
>> >> + const: starfive,jh7110-aon-syscon
>> >> + then:
>> >> + required:
>> >> + - "#power-domain-cells"
>> >
>> > Where did you implement the results of the discussion that only some
>> > devices can have power and clock controller?
>> >
>> > According to your code all of above - sys, aon and stg - have clock and
>> > power controllers. If not, then the code is not correct, so please do
>> > not respond with what is where (like you did last time) but actually
>> > implement what you say.
>> >
>>
>> Hi Krzysztof, I need to modify the code to implement it.
>> If I drop the 'clock-controller' and '"#power-domain-cells"' in properites, and change to this:
>>
>> --- a/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
>> +++ b/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
>> @@ -29,28 +29,33 @@ properties:
>> reg:
>> maxItems: 1
>>
>> - clock-controller:
>> - $ref: /schemas/clock/starfive,jh7110-pll.yaml#
>> - type: object
>> -
>> - "#power-domain-cells":
>> - const: 1
>> -
>> required:
>> - compatible
>> - reg
>>
>> allOf:
>> + - if:
>> + properties:
>> + compatible:
>> + contains:
>> + const: starfive,jh7110-sys-syscon
>> + then:
>> + properties:
>> + clock-controller:
>> + $ref: /schemas/clock/starfive,jh7110-pll.yaml#
>> + type: object
>
> Why do this?
> Why not define the property has you have been doing, but only allow it
> on the syscons that support it?
> See the section starting at L205 of example-schema.yaml.
>
>> +
>> - if:
>> properties:
>> compatible:
>> contains:
>> const: starfive,jh7110-aon-syscon
>> then:
>> - required:
>> - - "#power-domain-cells"
>> + properties:
>> + "#power-domain-cells":
>> + const: 1
>>
>
>> -additionalProperties: false
>> +additionalProperties: true
>
> Why do you need this?
> Allowing "additionalProperties: true" sounds like you've got some prblem
> that you are trying to hide...
>
>> Would it be better to show that sys-syscon only has clock-controller and aon-syscon is power controller?
>
> You should only permit the properties where they are valid, yes.
>
Yeah, following your advice, I modified the codes and there are two options:
--- a/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
+++ b/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
@@ -41,6 +41,16 @@ required:
- reg
allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: starfive,jh7110-sys-syscon
+ then:
+ required:
+ - clock-controller
+ properties:
+ "#power-domain-cells": false
- if:
properties:
compatible:
contains:
const: starfive,jh7110-aon-syscon
then:
required:
- "#power-domain-cells"
+ properties:
+ clock-controller: false
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: starfive,jh7110-stg-syscon
+ then:
+ properties:
+ clock-controller: false
+ "#power-domain-cells": false
additionalProperties: false
Or :
--- a/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
+++ b/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
@@ -41,6 +41,17 @@ required:
- reg
allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: starfive,jh7110-sys-syscon
+ then:
+ required:
+ - clock-controller
+ else:
+ properties:
+ clock-controller: false
- if:
properties:
compatible:
contains:
const: starfive,jh7110-aon-syscon
then:
required:
- "#power-domain-cells"
+ else:
+ properties:
+ "#power-domain-cells": false
additionalProperties: false
Which one is better? Thanks.
Best regards,
Xingyu Wu
On Thu, Jun 29, 2023 at 02:42:39PM +0800, Xingyu Wu wrote:
> On 2023/6/29 1:34, Conor Dooley wrote:
> > On Wed, Jun 28, 2023 at 02:44:10PM +0800, Xingyu Wu wrote:
> >> On 2023/6/14 2:31, Krzysztof Kozlowski wrote:
> >> > On 13/06/2023 14:58, Xingyu Wu wrote:
> >> >> From: William Qiu <[email protected]>
> >> >> +allOf:
> >> >> + - if:
> >> >> + properties:
> >> >> + compatible:
> >> >> + contains:
> >> >> + const: starfive,jh7110-aon-syscon
> >> >> + then:
> >> >> + required:
> >> >> + - "#power-domain-cells"
> >> >
> >> > Where did you implement the results of the discussion that only some
> >> > devices can have power and clock controller?
> >> >
> >> > According to your code all of above - sys, aon and stg - have clock and
> >> > power controllers. If not, then the code is not correct, so please do
> >> > not respond with what is where (like you did last time) but actually
> >> > implement what you say.
> Yeah, following your advice, I modified the codes and there are two options:
>
> --- a/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
> +++ b/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
> @@ -41,6 +41,16 @@ required:
> - reg
>
> allOf:
> + - if:
> + properties:
> + compatible:
> + contains:
> + const: starfive,jh7110-sys-syscon
> + then:
> + required:
> + - clock-controller
> + properties:
> + "#power-domain-cells": false
> - if:
> properties:
> compatible:
> contains:
> const: starfive,jh7110-aon-syscon
> then:
> required:
> - "#power-domain-cells"
> + properties:
> + clock-controller: false
> + - if:
> + properties:
> + compatible:
> + contains:
> + const: starfive,jh7110-stg-syscon
> + then:
> + properties:
> + clock-controller: false
> + "#power-domain-cells": false
>
> additionalProperties: false
>
> Or :
>
> --- a/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
> +++ b/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
> @@ -41,6 +41,17 @@ required:
> - reg
>
> allOf:
> + - if:
> + properties:
> + compatible:
> + contains:
> + const: starfive,jh7110-sys-syscon
> + then:
> + required:
> + - clock-controller
> + else:
> + properties:
> + clock-controller: false
> - if:
> properties:
> compatible:
> contains:
> const: starfive,jh7110-aon-syscon
> then:
> required:
> - "#power-domain-cells"
> + else:
> + properties:
> + "#power-domain-cells": false
>
> additionalProperties: false
>
> Which one is better? Thanks.
This second one looks better to me, as it achieves the same thing in a
simpler way.
Cheers,
Conor.