The st,m95640 is a 64 Kbit SPI eeprom in the same family as the two
existing st,m95* compatibles.
Signed-off-by: Rasmus Villemoes <[email protected]>
---
In case its relevant the data sheet is easily available from
https://www.st.com/en/memories/m95640-w.html . It seems odd they chose
right-pad with a 0, 640 instead of 064 (m02 means 2 Mbit, 256 means
256 Kbit, so there's some logic to that), but here we are.
Documentation/devicetree/bindings/eeprom/at25.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/eeprom/at25.yaml b/Documentation/devicetree/bindings/eeprom/at25.yaml
index 11e2a95a7bcb..0e31bb36ebb1 100644
--- a/Documentation/devicetree/bindings/eeprom/at25.yaml
+++ b/Documentation/devicetree/bindings/eeprom/at25.yaml
@@ -33,6 +33,7 @@ properties:
- microchip,25lc040
- st,m95m02
- st,m95256
+ - st,m95640
- cypress,fm25
- const: atmel,at25
--
2.37.2
On 14/06/2023 22:10, Rasmus Villemoes wrote:
> The st,m95640 is a 64 Kbit SPI eeprom in the same family as the two
> existing st,m95* compatibles.
>
> Signed-off-by: Rasmus Villemoes <[email protected]>
> ---
>
Acked-by: Krzysztof Kozlowski <[email protected]>
Best regards,
Krzysztof
On Wed, 14 Jun 2023 22:10:56 +0200, Rasmus Villemoes wrote:
> The st,m95640 is a 64 Kbit SPI eeprom in the same family as the two
> existing st,m95* compatibles.
>
> Signed-off-by: Rasmus Villemoes <[email protected]>
> ---
>
> In case its relevant the data sheet is easily available from
> https://www.st.com/en/memories/m95640-w.html . It seems odd they chose
> right-pad with a 0, 640 instead of 064 (m02 means 2 Mbit, 256 means
> 256 Kbit, so there's some logic to that), but here we are.
>
> Documentation/devicetree/bindings/eeprom/at25.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
Applied, thanks!