2023-06-15 10:27:19

by Thomas Bogendoerfer

Subject: [PATCH] MIPS: mm: Remove special handling for OCTEON CPUs

Macro cpu_has_mips_r2_exec_hazard correctly handles OCTEON CPUs,
so we don't need the extra switch cases for them.

Signed-off-by: Thomas Bogendoerfer <[email protected]>
---
arch/mips/mm/tlbex.c | 24 ++++--------------------
1 file changed, 4 insertions(+), 20 deletions(-)

diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
index 80e05ee98d62..8d514a9082c6 100644
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@ -2123,16 +2123,8 @@ static void build_r4000_tlb_load_handler(void)

uasm_i_tlbr(&p);

- switch (current_cpu_type()) {
- case CPU_CAVIUM_OCTEON:
- case CPU_CAVIUM_OCTEON_PLUS:
- case CPU_CAVIUM_OCTEON2:
- break;
- default:
- if (cpu_has_mips_r2_exec_hazard)
- uasm_i_ehb(&p);
- break;
- }
+ if (cpu_has_mips_r2_exec_hazard)
+ uasm_i_ehb(&p);

/* Examine entrylo 0 or 1 based on ptr. */
if (use_bbit_insns()) {
@@ -2197,16 +2189,8 @@ static void build_r4000_tlb_load_handler(void)

uasm_i_tlbr(&p);

- switch (current_cpu_type()) {
- case CPU_CAVIUM_OCTEON:
- case CPU_CAVIUM_OCTEON_PLUS:
- case CPU_CAVIUM_OCTEON2:
- break;
- default:
- if (cpu_has_mips_r2_exec_hazard)
- uasm_i_ehb(&p);
- break;
- }
+ if (cpu_has_mips_r2_exec_hazard)
+ uasm_i_ehb(&p);

/* Examine entrylo 0 or 1 based on ptr. */
if (use_bbit_insns()) {
--
2.35.3

2023-06-20 13:04:39

by Thomas Bogendoerfer

Subject: Re: [PATCH] MIPS: mm: Remove special handling for OCTEON CPUs

On Thu, Jun 15, 2023 at 11:39:33AM +0200, Thomas Bogendoerfer wrote:
> Macro cpu_has_mips_r2_exec_hazard correctly handles OCTEON CPUs,
> so we don't need the extra switch cases for them.
>
> Signed-off-by: Thomas Bogendoerfer <[email protected]>
> ---
> arch/mips/mm/tlbex.c | 24 ++++--------------------
> 1 file changed, 4 insertions(+), 20 deletions(-)

applied to mips-next.

Thomas.

--
Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
good idea. [ RFC1925, 2.3 ]