This contains only small changes to the last version, but in one case
a really important one: As Sebastian noted there is sometimes wrong data
reported. This is fixed in this version.
Other than that there are only small changes, see below in the changelog.
Overall I think this series this series is ready for primetime now.
Sascha
Changes since v5:
- Add missing initialization of &dfi->last_perf_count which resulted
in wrong data sometimes
- Drop interrupt-names property from binding
- Add patch to add rockchip,rk3588-pmugrf to dt-bindings
- Add more reviewed-by tags
Changes since v4:
- Add device tree changes for RK3588
- Use seqlock to protect perf counter values from hrtimer
- Unconditionally enable DFI when perf is enabled
- Bring back changes to dts/binding patches that were lost in v4
Changes since v3:
- Add RK3588 support
Changes since v2:
- Fix broken reference to binding
- Add Reviewed-by from Rob
Changes since v1:
- Fix example to actually match the binding and fix the warnings resulted thereof
- Make addition of rockchip,rk3568-dfi an extra patch
Sascha Hauer (26):
PM / devfreq: rockchip-dfi: Make pmu regmap mandatory
PM / devfreq: rockchip-dfi: Embed desc into private data struct
PM / devfreq: rockchip-dfi: use consistent name for private data
struct
PM / devfreq: rockchip-dfi: Add SoC specific init function
PM / devfreq: rockchip-dfi: dfi store raw values in counter struct
PM / devfreq: rockchip-dfi: Use free running counter
PM / devfreq: rockchip-dfi: introduce channel mask
PM / devfreq: rk3399_dmc,dfi: generalize DDRTYPE defines
PM / devfreq: rockchip-dfi: Clean up DDR type register defines
PM / devfreq: rockchip-dfi: Add RK3568 support
PM / devfreq: rockchip-dfi: Handle LPDDR2 correctly
PM / devfreq: rockchip-dfi: Handle LPDDR4X
PM / devfreq: rockchip-dfi: Pass private data struct to internal
functions
PM / devfreq: rockchip-dfi: Prepare for multiple users
PM / devfreq: rockchip-dfi: give variable a better name
PM / devfreq: rockchip-dfi: Add perf support
PM / devfreq: rockchip-dfi: make register stride SoC specific
PM / devfreq: rockchip-dfi: account for multiple DDRMON_CTRL registers
PM / devfreq: rockchip-dfi: add support for RK3588
dt-bindings: devfreq: event: convert Rockchip DFI binding to yaml
dt-bindings: devfreq: event: rockchip,dfi: Add rk3568 support
dt-bindings: devfreq: event: rockchip,dfi: Add rk3588 support
dt-bindings: soc: rockchip: grf: add rockchip,rk3588-pmugrf
arm64: dts: rockchip: rk3399: Enable DFI
arm64: dts: rockchip: rk356x: Add DFI
arm64: dts: rockchip: rk3588s: Add DFI
.../bindings/devfreq/event/rockchip,dfi.yaml | 74 ++
.../bindings/devfreq/event/rockchip-dfi.txt | 18 -
.../rockchip,rk3399-dmc.yaml | 2 +-
.../devicetree/bindings/soc/rockchip/grf.yaml | 1 +
arch/arm64/boot/dts/rockchip/rk3399.dtsi | 1 -
arch/arm64/boot/dts/rockchip/rk356x.dtsi | 7 +
arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 16 +
drivers/devfreq/event/rockchip-dfi.c | 799 +++++++++++++++---
drivers/devfreq/rk3399_dmc.c | 10 +-
include/soc/rockchip/rk3399_grf.h | 9 +-
include/soc/rockchip/rk3568_grf.h | 13 +
include/soc/rockchip/rk3588_grf.h | 18 +
include/soc/rockchip/rockchip_grf.h | 18 +
13 files changed, 848 insertions(+), 138 deletions(-)
create mode 100644 Documentation/devicetree/bindings/devfreq/event/rockchip,dfi.yaml
delete mode 100644 Documentation/devicetree/bindings/devfreq/event/rockchip-dfi.txt
create mode 100644 include/soc/rockchip/rk3568_grf.h
create mode 100644 include/soc/rockchip/rk3588_grf.h
create mode 100644 include/soc/rockchip/rockchip_grf.h
--
2.39.2
Move the RK3399 specifics to a SoC specific init function to make
the way free for supporting other SoCs later.
Reviewed-by: Sebastian Reichel <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Sascha Hauer <[email protected]>
---
Notes:
Changes since v4:
- use of_device_get_match_data()
- use a callback rather than a struct type as driver data
drivers/devfreq/event/rockchip-dfi.c | 48 +++++++++++++++++++---------
1 file changed, 33 insertions(+), 15 deletions(-)
diff --git a/drivers/devfreq/event/rockchip-dfi.c b/drivers/devfreq/event/rockchip-dfi.c
index e19e5acaa362c..6b1ef29df7048 100644
--- a/drivers/devfreq/event/rockchip-dfi.c
+++ b/drivers/devfreq/event/rockchip-dfi.c
@@ -17,6 +17,7 @@
#include <linux/slab.h>
#include <linux/list.h>
#include <linux/of.h>
+#include <linux/of_device.h>
#include <soc/rockchip/rk3399_grf.h>
@@ -55,27 +56,21 @@ struct rockchip_dfi {
void __iomem *regs;
struct regmap *regmap_pmu;
struct clk *clk;
+ u32 ddr_type;
};
static void rockchip_dfi_start_hardware_counter(struct devfreq_event_dev *edev)
{
struct rockchip_dfi *dfi = devfreq_event_get_drvdata(edev);
void __iomem *dfi_regs = dfi->regs;
- u32 val;
- u32 ddr_type;
-
- /* get ddr type */
- regmap_read(dfi->regmap_pmu, RK3399_PMUGRF_OS_REG2, &val);
- ddr_type = (val >> RK3399_PMUGRF_DDRTYPE_SHIFT) &
- RK3399_PMUGRF_DDRTYPE_MASK;
/* clear DDRMON_CTRL setting */
writel_relaxed(CLR_DDRMON_CTRL, dfi_regs + DDRMON_CTRL);
/* set ddr type to dfi */
- if (ddr_type == RK3399_PMUGRF_DDRTYPE_LPDDR3)
+ if (dfi->ddr_type == RK3399_PMUGRF_DDRTYPE_LPDDR3)
writel_relaxed(LPDDR3_EN, dfi_regs + DDRMON_CTRL);
- else if (ddr_type == RK3399_PMUGRF_DDRTYPE_LPDDR4)
+ else if (dfi->ddr_type == RK3399_PMUGRF_DDRTYPE_LPDDR4)
writel_relaxed(LPDDR4_EN, dfi_regs + DDRMON_CTRL);
/* enable count, use software mode */
@@ -167,8 +162,26 @@ static const struct devfreq_event_ops rockchip_dfi_ops = {
.set_event = rockchip_dfi_set_event,
};
+static int rk3399_dfi_init(struct rockchip_dfi *dfi)
+{
+ struct regmap *regmap_pmu = dfi->regmap_pmu;
+ u32 val;
+
+ dfi->clk = devm_clk_get(dfi->dev, "pclk_ddr_mon");
+ if (IS_ERR(dfi->clk))
+ return dev_err_probe(dfi->dev, PTR_ERR(dfi->clk),
+ "Cannot get the clk pclk_ddr_mon\n");
+
+ /* get ddr type */
+ regmap_read(regmap_pmu, RK3399_PMUGRF_OS_REG2, &val);
+ dfi->ddr_type = (val >> RK3399_PMUGRF_DDRTYPE_SHIFT) &
+ RK3399_PMUGRF_DDRTYPE_MASK;
+
+ return 0;
+};
+
static const struct of_device_id rockchip_dfi_id_match[] = {
- { .compatible = "rockchip,rk3399-dfi" },
+ { .compatible = "rockchip,rk3399-dfi", .data = rk3399_dfi_init },
{ },
};
MODULE_DEVICE_TABLE(of, rockchip_dfi_id_match);
@@ -179,6 +192,12 @@ static int rockchip_dfi_probe(struct platform_device *pdev)
struct rockchip_dfi *dfi;
struct devfreq_event_desc *desc;
struct device_node *np = pdev->dev.of_node, *node;
+ int (*soc_init)(struct rockchip_dfi *dfi);
+ int ret;
+
+ soc_init = of_device_get_match_data(&pdev->dev);
+ if (!soc_init)
+ return -EINVAL;
dfi = devm_kzalloc(dev, sizeof(*dfi), GFP_KERNEL);
if (!dfi)
@@ -188,11 +207,6 @@ static int rockchip_dfi_probe(struct platform_device *pdev)
if (IS_ERR(dfi->regs))
return PTR_ERR(dfi->regs);
- dfi->clk = devm_clk_get(dev, "pclk_ddr_mon");
- if (IS_ERR(dfi->clk))
- return dev_err_probe(dev, PTR_ERR(dfi->clk),
- "Cannot get the clk pclk_ddr_mon\n");
-
node = of_parse_phandle(np, "rockchip,pmu", 0);
if (!node)
return dev_err_probe(&pdev->dev, -ENODEV, "Can't find pmu_grf registers\n");
@@ -209,6 +223,10 @@ static int rockchip_dfi_probe(struct platform_device *pdev)
desc->driver_data = dfi;
desc->name = np->name;
+ ret = soc_init(dfi);
+ if (ret)
+ return ret;
+
dfi->edev = devm_devfreq_event_add_edev(&pdev->dev, desc);
if (IS_ERR(dfi->edev)) {
dev_err(&pdev->dev,
--
2.39.2
The DFI is a unit which is suitable for measuring DDR utilization, but
so far it could only be used as an event driver for the DDR frequency
scaling driver. This adds perf support to the DFI driver.
Usage with the 'perf' tool can look like:
perf stat -a -e rockchip_ddr/cycles/,\
rockchip_ddr/read-bytes/,\
rockchip_ddr/write-bytes/,\
rockchip_ddr/bytes/ sleep 1
Performance counter stats for 'system wide':
1582524826 rockchip_ddr/cycles/
1802.25 MB rockchip_ddr/read-bytes/
1793.72 MB rockchip_ddr/write-bytes/
3595.90 MB rockchip_ddr/bytes/
1.014369709 seconds time elapsed
perf support has been tested on a RK3568 and a RK3399, the latter with
dual channel DDR.
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Sascha Hauer <[email protected]>
Reviewed-by: Sebastian Reichel <[email protected]>
---
Notes:
Changes since v5:
- Add missing initialization of &dfi->last_perf_count
Changes since v4:
- use __stringify to ensure event type definitions and event numbers in sysfs are consistent
- only use 64bit values in structs holding counters
- support monitoring individual DDR channels
- fix return value in rockchip_ddr_perf_event_init(): -EOPNOTSUPP -> -EINVAL
- check for invalid event->attr.config values
- start hrtimer to trigger in one second, not immediately
- use devm_add_action_or_reset()
- add suppress_bind_attrs
- enable DDRMON during probe when perf is enabled
- use a seqlock to protect perf reading the counters from the hrtimer callback modifying them
drivers/devfreq/event/rockchip-dfi.c | 442 ++++++++++++++++++++++++++-
include/soc/rockchip/rk3399_grf.h | 2 +
include/soc/rockchip/rk3568_grf.h | 1 +
3 files changed, 440 insertions(+), 5 deletions(-)
diff --git a/drivers/devfreq/event/rockchip-dfi.c b/drivers/devfreq/event/rockchip-dfi.c
index 50e497455dc69..969b62f071b83 100644
--- a/drivers/devfreq/event/rockchip-dfi.c
+++ b/drivers/devfreq/event/rockchip-dfi.c
@@ -16,10 +16,12 @@
#include <linux/regmap.h>
#include <linux/slab.h>
#include <linux/list.h>
+#include <linux/seqlock.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/bitfield.h>
#include <linux/bits.h>
+#include <linux/perf_event.h>
#include <soc/rockchip/rockchip_grf.h>
#include <soc/rockchip/rk3399_grf.h>
@@ -41,19 +43,39 @@
DDRMON_CTRL_LPDDR4 | \
DDRMON_CTRL_LPDDR23)
+#define DDRMON_CH0_WR_NUM 0x20
+#define DDRMON_CH0_RD_NUM 0x24
#define DDRMON_CH0_COUNT_NUM 0x28
#define DDRMON_CH0_DFI_ACCESS_NUM 0x2c
#define DDRMON_CH1_COUNT_NUM 0x3c
#define DDRMON_CH1_DFI_ACCESS_NUM 0x40
+#define PERF_EVENT_CYCLES 0x0
+#define PERF_EVENT_READ_BYTES 0x1
+#define PERF_EVENT_WRITE_BYTES 0x2
+#define PERF_EVENT_READ_BYTES0 0x3
+#define PERF_EVENT_WRITE_BYTES0 0x4
+#define PERF_EVENT_READ_BYTES1 0x5
+#define PERF_EVENT_WRITE_BYTES1 0x6
+#define PERF_EVENT_READ_BYTES2 0x7
+#define PERF_EVENT_WRITE_BYTES2 0x8
+#define PERF_EVENT_READ_BYTES3 0x9
+#define PERF_EVENT_WRITE_BYTES3 0xa
+#define PERF_EVENT_BYTES 0xb
+#define PERF_ACCESS_TYPE_MAX 0xc
+
/**
* struct dmc_count_channel - structure to hold counter values from the DDR controller
* @access: Number of read and write accesses
* @clock_cycles: DDR clock cycles
+ * @read_access: number of read accesses
+ * @write_acccess: number of write accesses
*/
struct dmc_count_channel {
- u32 access;
- u32 clock_cycles;
+ u64 access;
+ u64 clock_cycles;
+ u64 read_access;
+ u64 write_access;
};
struct dmc_count {
@@ -69,6 +91,11 @@ struct rockchip_dfi {
struct devfreq_event_dev *edev;
struct devfreq_event_desc desc;
struct dmc_count last_event_count;
+
+ struct dmc_count last_perf_count;
+ struct dmc_count total_count;
+ seqlock_t count_seqlock; /* protects last_perf_count and total_count */
+
struct device *dev;
void __iomem *regs;
struct regmap *regmap_pmu;
@@ -77,6 +104,14 @@ struct rockchip_dfi {
struct mutex mutex;
u32 ddr_type;
unsigned int channel_mask;
+ enum cpuhp_state cpuhp_state;
+ struct hlist_node node;
+ struct pmu pmu;
+ struct hrtimer timer;
+ unsigned int cpu;
+ int active_events;
+ int burst_len;
+ int buswidth[DMC_MAX_CHANNELS];
};
static int rockchip_dfi_enable(struct rockchip_dfi *dfi)
@@ -145,7 +180,7 @@ static void rockchip_dfi_disable(struct rockchip_dfi *dfi)
mutex_unlock(&dfi->mutex);
}
-static void rockchip_dfi_read_counters(struct rockchip_dfi *dfi, struct dmc_count *count)
+static void rockchip_dfi_read_counters(struct rockchip_dfi *dfi, struct dmc_count *c)
{
u32 i;
void __iomem *dfi_regs = dfi->regs;
@@ -153,13 +188,36 @@ static void rockchip_dfi_read_counters(struct rockchip_dfi *dfi, struct dmc_coun
for (i = 0; i < DMC_MAX_CHANNELS; i++) {
if (!(dfi->channel_mask & BIT(i)))
continue;
- count->c[i].access = readl_relaxed(dfi_regs +
+ c->c[i].read_access = readl_relaxed(dfi_regs +
+ DDRMON_CH0_RD_NUM + i * 20);
+ c->c[i].write_access = readl_relaxed(dfi_regs +
+ DDRMON_CH0_WR_NUM + i * 20);
+ c->c[i].access = readl_relaxed(dfi_regs +
DDRMON_CH0_DFI_ACCESS_NUM + i * 20);
- count->c[i].clock_cycles = readl_relaxed(dfi_regs +
+ c->c[i].clock_cycles = readl_relaxed(dfi_regs +
DDRMON_CH0_COUNT_NUM + i * 20);
}
}
+static void rockchip_ddr_perf_counters_add(struct rockchip_dfi *dfi,
+ const struct dmc_count *now,
+ struct dmc_count *res)
+{
+ const struct dmc_count *last = &dfi->last_perf_count;
+ int i;
+
+ for (i = 0; i < DMC_MAX_CHANNELS; i++) {
+ res->c[i].read_access = dfi->total_count.c[i].read_access +
+ (u32)(now->c[i].read_access - last->c[i].read_access);
+ res->c[i].write_access = dfi->total_count.c[i].write_access +
+ (u32)(now->c[i].write_access - last->c[i].write_access);
+ res->c[i].access = dfi->total_count.c[i].access +
+ (u32)(now->c[i].access - last->c[i].access);
+ res->c[i].clock_cycles = dfi->total_count.c[i].clock_cycles +
+ (u32)(now->c[i].clock_cycles - last->c[i].clock_cycles);
+ }
+}
+
static int rockchip_dfi_event_disable(struct devfreq_event_dev *edev)
{
struct rockchip_dfi *dfi = devfreq_event_get_drvdata(edev);
@@ -223,6 +281,370 @@ static const struct devfreq_event_ops rockchip_dfi_ops = {
.set_event = rockchip_dfi_set_event,
};
+#ifdef CONFIG_PERF_EVENTS
+
+static ssize_t ddr_perf_cpumask_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct pmu *pmu = dev_get_drvdata(dev);
+ struct rockchip_dfi *dfi = container_of(pmu, struct rockchip_dfi, pmu);
+
+ return cpumap_print_to_pagebuf(true, buf, cpumask_of(dfi->cpu));
+}
+
+static struct device_attribute ddr_perf_cpumask_attr =
+ __ATTR(cpumask, 0444, ddr_perf_cpumask_show, NULL);
+
+static struct attribute *ddr_perf_cpumask_attrs[] = {
+ &ddr_perf_cpumask_attr.attr,
+ NULL,
+};
+
+static const struct attribute_group ddr_perf_cpumask_attr_group = {
+ .attrs = ddr_perf_cpumask_attrs,
+};
+
+PMU_EVENT_ATTR_STRING(cycles, ddr_pmu_cycles, "event="__stringify(PERF_EVENT_CYCLES))
+
+#define DFI_PMU_EVENT_ATTR(_name, _var, _str) \
+ PMU_EVENT_ATTR_STRING(_name, _var, _str); \
+ PMU_EVENT_ATTR_STRING(_name.unit, _var##_unit, "MB"); \
+ PMU_EVENT_ATTR_STRING(_name.scale, _var##_scale, "9.536743164e-07")
+
+DFI_PMU_EVENT_ATTR(read-bytes0, ddr_pmu_read_bytes0, "event="__stringify(PERF_EVENT_READ_BYTES0));
+DFI_PMU_EVENT_ATTR(write-bytes0, ddr_pmu_write_bytes0, "event="__stringify(PERF_EVENT_WRITE_BYTES0));
+
+DFI_PMU_EVENT_ATTR(read-bytes1, ddr_pmu_read_bytes1, "event="__stringify(PERF_EVENT_READ_BYTES1));
+DFI_PMU_EVENT_ATTR(write-bytes1, ddr_pmu_write_bytes1, "event="__stringify(PERF_EVENT_WRITE_BYTES1));
+
+DFI_PMU_EVENT_ATTR(read-bytes2, ddr_pmu_read_bytes2, "event="__stringify(PERF_EVENT_READ_BYTES2));
+DFI_PMU_EVENT_ATTR(write-bytes2, ddr_pmu_write_bytes2, "event="__stringify(PERF_EVENT_WRITE_BYTES2));
+
+DFI_PMU_EVENT_ATTR(read-bytes3, ddr_pmu_read_bytes3, "event="__stringify(PERF_EVENT_READ_BYTES3));
+DFI_PMU_EVENT_ATTR(write-bytes3, ddr_pmu_write_bytes3, "event="__stringify(PERF_EVENT_WRITE_BYTES3));
+
+DFI_PMU_EVENT_ATTR(read-bytes, ddr_pmu_read_bytes, "event="__stringify(PERF_EVENT_READ_BYTES));
+DFI_PMU_EVENT_ATTR(write-bytes, ddr_pmu_write_bytes, "event="__stringify(PERF_EVENT_WRITE_BYTES));
+
+DFI_PMU_EVENT_ATTR(bytes, ddr_pmu_bytes, "event="__stringify(PERF_EVENT_BYTES));
+
+#define DFI_ATTR_MB(_name) \
+ &_name.attr.attr, \
+ &_name##_unit.attr.attr, \
+ &_name##_scale.attr.attr
+
+static struct attribute *ddr_perf_events_attrs[] = {
+ &ddr_pmu_cycles.attr.attr,
+ DFI_ATTR_MB(ddr_pmu_read_bytes),
+ DFI_ATTR_MB(ddr_pmu_write_bytes),
+ DFI_ATTR_MB(ddr_pmu_read_bytes0),
+ DFI_ATTR_MB(ddr_pmu_write_bytes0),
+ DFI_ATTR_MB(ddr_pmu_read_bytes1),
+ DFI_ATTR_MB(ddr_pmu_write_bytes1),
+ DFI_ATTR_MB(ddr_pmu_read_bytes2),
+ DFI_ATTR_MB(ddr_pmu_write_bytes2),
+ DFI_ATTR_MB(ddr_pmu_read_bytes3),
+ DFI_ATTR_MB(ddr_pmu_write_bytes3),
+ DFI_ATTR_MB(ddr_pmu_bytes),
+ NULL,
+};
+
+static const struct attribute_group ddr_perf_events_attr_group = {
+ .name = "events",
+ .attrs = ddr_perf_events_attrs,
+};
+
+PMU_FORMAT_ATTR(event, "config:0-7");
+
+static struct attribute *ddr_perf_format_attrs[] = {
+ &format_attr_event.attr,
+ NULL,
+};
+
+static const struct attribute_group ddr_perf_format_attr_group = {
+ .name = "format",
+ .attrs = ddr_perf_format_attrs,
+};
+
+static const struct attribute_group *attr_groups[] = {
+ &ddr_perf_events_attr_group,
+ &ddr_perf_cpumask_attr_group,
+ &ddr_perf_format_attr_group,
+ NULL,
+};
+
+static int rockchip_ddr_perf_event_init(struct perf_event *event)
+{
+ struct rockchip_dfi *dfi = container_of(event->pmu, struct rockchip_dfi, pmu);
+
+ if (event->attr.type != event->pmu->type)
+ return -ENOENT;
+
+ if (event->attach_state & PERF_ATTACH_TASK)
+ return -EINVAL;
+
+ if (event->cpu < 0) {
+ dev_warn(dfi->dev, "Can't provide per-task data!\n");
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static u64 rockchip_ddr_perf_event_get_count(struct perf_event *event)
+{
+ struct rockchip_dfi *dfi = container_of(event->pmu, struct rockchip_dfi, pmu);
+ int blen = dfi->burst_len;
+ struct dmc_count total, now;
+ unsigned int seq;
+ u64 c = 0;
+ int i;
+
+ rockchip_dfi_read_counters(dfi, &now);
+
+ do {
+ seq = read_seqbegin(&dfi->count_seqlock);
+
+ rockchip_ddr_perf_counters_add(dfi, &now, &total);
+
+ } while (read_seqretry(&dfi->count_seqlock, seq));
+
+ switch (event->attr.config) {
+ case PERF_EVENT_CYCLES:
+ c = total.c[0].clock_cycles;
+ break;
+ case PERF_EVENT_READ_BYTES:
+ for (i = 0; i < DMC_MAX_CHANNELS; i++)
+ c += total.c[i].read_access * blen * dfi->buswidth[i];
+ break;
+ case PERF_EVENT_WRITE_BYTES:
+ for (i = 0; i < DMC_MAX_CHANNELS; i++)
+ c += total.c[i].write_access * blen * dfi->buswidth[i];
+ break;
+ case PERF_EVENT_READ_BYTES0:
+ c = total.c[0].read_access * blen * dfi->buswidth[0];
+ break;
+ case PERF_EVENT_WRITE_BYTES0:
+ c = total.c[0].write_access * blen * dfi->buswidth[0];
+ break;
+ case PERF_EVENT_READ_BYTES1:
+ c = total.c[1].read_access * blen * dfi->buswidth[1];
+ break;
+ case PERF_EVENT_WRITE_BYTES1:
+ c = total.c[1].write_access * blen * dfi->buswidth[1];
+ break;
+ case PERF_EVENT_READ_BYTES2:
+ c = total.c[2].read_access * blen * dfi->buswidth[2];
+ break;
+ case PERF_EVENT_WRITE_BYTES2:
+ c = total.c[2].write_access * blen * dfi->buswidth[2];
+ break;
+ case PERF_EVENT_READ_BYTES3:
+ c = total.c[3].read_access * blen * dfi->buswidth[3];
+ break;
+ case PERF_EVENT_WRITE_BYTES3:
+ c = total.c[3].write_access * blen * dfi->buswidth[3];
+ break;
+ case PERF_EVENT_BYTES:
+ for (i = 0; i < DMC_MAX_CHANNELS; i++)
+ c += total.c[i].access * blen * dfi->buswidth[i];
+ break;
+ }
+
+ return c;
+}
+
+static void rockchip_ddr_perf_event_update(struct perf_event *event)
+{
+ u64 now;
+ s64 prev;
+
+ if (event->attr.config >= PERF_ACCESS_TYPE_MAX)
+ return;
+
+ now = rockchip_ddr_perf_event_get_count(event);
+ prev = local64_xchg(&event->hw.prev_count, now);
+ local64_add(now - prev, &event->count);
+}
+
+static void rockchip_ddr_perf_event_start(struct perf_event *event, int flags)
+{
+ u64 now = rockchip_ddr_perf_event_get_count(event);
+
+ local64_set(&event->hw.prev_count, now);
+}
+
+static int rockchip_ddr_perf_event_add(struct perf_event *event, int flags)
+{
+ struct rockchip_dfi *dfi = container_of(event->pmu, struct rockchip_dfi, pmu);
+
+ dfi->active_events++;
+
+ if (dfi->active_events == 1) {
+ dfi->total_count = (struct dmc_count){};
+ rockchip_dfi_read_counters(dfi, &dfi->last_perf_count);
+ hrtimer_start(&dfi->timer, ns_to_ktime(NSEC_PER_SEC), HRTIMER_MODE_REL);
+ }
+
+ if (flags & PERF_EF_START)
+ rockchip_ddr_perf_event_start(event, flags);
+
+ return 0;
+}
+
+static void rockchip_ddr_perf_event_stop(struct perf_event *event, int flags)
+{
+ rockchip_ddr_perf_event_update(event);
+}
+
+static void rockchip_ddr_perf_event_del(struct perf_event *event, int flags)
+{
+ struct rockchip_dfi *dfi = container_of(event->pmu, struct rockchip_dfi, pmu);
+
+ rockchip_ddr_perf_event_stop(event, PERF_EF_UPDATE);
+
+ dfi->active_events--;
+
+ if (dfi->active_events == 0)
+ hrtimer_cancel(&dfi->timer);
+}
+
+static enum hrtimer_restart rockchip_dfi_timer(struct hrtimer *timer)
+{
+ struct rockchip_dfi *dfi = container_of(timer, struct rockchip_dfi, timer);
+ struct dmc_count now, total;
+
+ rockchip_dfi_read_counters(dfi, &now);
+
+ write_seqlock(&dfi->count_seqlock);
+
+ rockchip_ddr_perf_counters_add(dfi, &now, &total);
+ dfi->total_count = total;
+ dfi->last_perf_count = now;
+
+ write_sequnlock(&dfi->count_seqlock);
+
+ hrtimer_forward_now(&dfi->timer, ns_to_ktime(NSEC_PER_SEC));
+
+ return HRTIMER_RESTART;
+};
+
+static int ddr_perf_offline_cpu(unsigned int cpu, struct hlist_node *node)
+{
+ struct rockchip_dfi *dfi = hlist_entry_safe(node, struct rockchip_dfi, node);
+ int target;
+
+ if (cpu != dfi->cpu)
+ return 0;
+
+ target = cpumask_any_but(cpu_online_mask, cpu);
+ if (target >= nr_cpu_ids)
+ return 0;
+
+ perf_pmu_migrate_context(&dfi->pmu, cpu, target);
+ dfi->cpu = target;
+
+ return 0;
+}
+
+static void rockchip_ddr_cpuhp_remove_state(void *data)
+{
+ struct rockchip_dfi *dfi = data;
+
+ cpuhp_remove_multi_state(dfi->cpuhp_state);
+
+ rockchip_dfi_disable(dfi);
+}
+
+static void rockchip_ddr_cpuhp_remove_instance(void *data)
+{
+ struct rockchip_dfi *dfi = data;
+
+ cpuhp_state_remove_instance_nocalls(dfi->cpuhp_state, &dfi->node);
+}
+
+static void rockchip_ddr_perf_remove(void *data)
+{
+ struct rockchip_dfi *dfi = data;
+
+ perf_pmu_unregister(&dfi->pmu);
+}
+
+static int rockchip_ddr_perf_init(struct rockchip_dfi *dfi)
+{
+ struct pmu *pmu = &dfi->pmu;
+ int ret;
+
+ seqlock_init(&dfi->count_seqlock);
+
+ pmu->module = THIS_MODULE;
+ pmu->capabilities = PERF_PMU_CAP_NO_EXCLUDE;
+ pmu->task_ctx_nr = perf_invalid_context;
+ pmu->attr_groups = attr_groups;
+ pmu->event_init = rockchip_ddr_perf_event_init;
+ pmu->add = rockchip_ddr_perf_event_add;
+ pmu->del = rockchip_ddr_perf_event_del;
+ pmu->start = rockchip_ddr_perf_event_start;
+ pmu->stop = rockchip_ddr_perf_event_stop;
+ pmu->read = rockchip_ddr_perf_event_update;
+
+ dfi->cpu = raw_smp_processor_id();
+
+ ret = cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN,
+ "rockchip_ddr_perf_pmu",
+ NULL,
+ ddr_perf_offline_cpu);
+
+ if (ret < 0) {
+ dev_err(dfi->dev, "cpuhp_setup_state_multi failed: %d\n", ret);
+ return ret;
+ }
+
+ dfi->cpuhp_state = ret;
+
+ rockchip_dfi_enable(dfi);
+
+ ret = devm_add_action_or_reset(dfi->dev, rockchip_ddr_cpuhp_remove_state, dfi);
+ if (ret)
+ return ret;
+
+ ret = cpuhp_state_add_instance_nocalls(dfi->cpuhp_state, &dfi->node);
+ if (ret) {
+ dev_err(dfi->dev, "Error %d registering hotplug\n", ret);
+ return ret;
+ }
+
+ ret = devm_add_action_or_reset(dfi->dev, rockchip_ddr_cpuhp_remove_instance, dfi);
+ if (ret)
+ return ret;
+
+ hrtimer_init(&dfi->timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
+ dfi->timer.function = rockchip_dfi_timer;
+
+ switch (dfi->ddr_type) {
+ case ROCKCHIP_DDRTYPE_LPDDR2:
+ case ROCKCHIP_DDRTYPE_LPDDR3:
+ dfi->burst_len = 8;
+ break;
+ case ROCKCHIP_DDRTYPE_LPDDR4:
+ case ROCKCHIP_DDRTYPE_LPDDR4X:
+ dfi->burst_len = 16;
+ break;
+ }
+
+ ret = perf_pmu_register(pmu, "rockchip_ddr", -1);
+ if (ret)
+ return ret;
+
+ return devm_add_action_or_reset(dfi->dev, rockchip_ddr_perf_remove, dfi);
+}
+#else
+static int rockchip_ddr_perf_init(struct rockchip_dfi *dfi)
+{
+ return 0;
+}
+#endif
+
static int rk3399_dfi_init(struct rockchip_dfi *dfi)
{
struct regmap *regmap_pmu = dfi->regmap_pmu;
@@ -239,6 +661,9 @@ static int rk3399_dfi_init(struct rockchip_dfi *dfi)
dfi->channel_mask = GENMASK(1, 0);
+ dfi->buswidth[0] = FIELD_GET(RK3399_PMUGRF_OS_REG2_BW_CH0, val) == 0 ? 4 : 2;
+ dfi->buswidth[1] = FIELD_GET(RK3399_PMUGRF_OS_REG2_BW_CH1, val) == 0 ? 4 : 2;
+
return 0;
};
@@ -255,6 +680,8 @@ static int rk3568_dfi_init(struct rockchip_dfi *dfi)
if (FIELD_GET(RK3568_PMUGRF_OS_REG3_SYSREG_VERSION, reg3) >= 0x3)
dfi->ddr_type |= FIELD_GET(RK3568_PMUGRF_OS_REG3_DRAMTYPE_INFO_V3, reg3) << 3;
+ dfi->buswidth[0] = FIELD_GET(RK3568_PMUGRF_OS_REG2_BW_CH0, reg2) == 0 ? 4 : 2;
+
dfi->channel_mask = 1;
return 0;
@@ -317,6 +744,10 @@ static int rockchip_dfi_probe(struct platform_device *pdev)
return PTR_ERR(dfi->edev);
}
+ ret = rockchip_ddr_perf_init(dfi);
+ if (ret)
+ return ret;
+
platform_set_drvdata(pdev, dfi);
return 0;
@@ -327,6 +758,7 @@ static struct platform_driver rockchip_dfi_driver = {
.driver = {
.name = "rockchip-dfi",
.of_match_table = rockchip_dfi_id_match,
+ .suppress_bind_attrs = true,
},
};
module_platform_driver(rockchip_dfi_driver);
diff --git a/include/soc/rockchip/rk3399_grf.h b/include/soc/rockchip/rk3399_grf.h
index 775f8444bea8d..39cd44cec982f 100644
--- a/include/soc/rockchip/rk3399_grf.h
+++ b/include/soc/rockchip/rk3399_grf.h
@@ -12,5 +12,7 @@
/* PMU GRF Registers */
#define RK3399_PMUGRF_OS_REG2 0x308
#define RK3399_PMUGRF_OS_REG2_DDRTYPE GENMASK(15, 13)
+#define RK3399_PMUGRF_OS_REG2_BW_CH0 GENMASK(3, 2)
+#define RK3399_PMUGRF_OS_REG2_BW_CH1 GENMASK(19, 18)
#endif
diff --git a/include/soc/rockchip/rk3568_grf.h b/include/soc/rockchip/rk3568_grf.h
index 575584e9d8834..52853efd6720e 100644
--- a/include/soc/rockchip/rk3568_grf.h
+++ b/include/soc/rockchip/rk3568_grf.h
@@ -4,6 +4,7 @@
#define RK3568_PMUGRF_OS_REG2 0x208
#define RK3568_PMUGRF_OS_REG2_DRAMTYPE_INFO GENMASK(15, 13)
+#define RK3568_PMUGRF_OS_REG2_BW_CH0 GENMASK(3, 2)
#define RK3568_PMUGRF_OS_REG3 0x20c
#define RK3568_PMUGRF_OS_REG3_DRAMTYPE_INFO_V3 GENMASK(13, 12)
--
2.39.2
In the DFI driver LPDDR4X can be handled in the same way as LPDDR4. Add
the missing case.
Reviewed-by: Jonathan Cameron <[email protected]>
Reviewed-by: Sebastian Reichel <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Sascha Hauer <[email protected]>
---
drivers/devfreq/event/rockchip-dfi.c | 1 +
include/soc/rockchip/rockchip_grf.h | 1 +
2 files changed, 2 insertions(+)
diff --git a/drivers/devfreq/event/rockchip-dfi.c b/drivers/devfreq/event/rockchip-dfi.c
index 16cd5365671f7..0a568c5551699 100644
--- a/drivers/devfreq/event/rockchip-dfi.c
+++ b/drivers/devfreq/event/rockchip-dfi.c
@@ -89,6 +89,7 @@ static void rockchip_dfi_start_hardware_counter(struct devfreq_event_dev *edev)
dfi_regs + DDRMON_CTRL);
break;
case ROCKCHIP_DDRTYPE_LPDDR4:
+ case ROCKCHIP_DDRTYPE_LPDDR4X:
writel_relaxed(HIWORD_UPDATE(DDRMON_CTRL_LPDDR4, DDRMON_CTRL_DDR_TYPE_MASK),
dfi_regs + DDRMON_CTRL);
break;
diff --git a/include/soc/rockchip/rockchip_grf.h b/include/soc/rockchip/rockchip_grf.h
index dde1a9796ccb5..e46fd72aea8d1 100644
--- a/include/soc/rockchip/rockchip_grf.h
+++ b/include/soc/rockchip/rockchip_grf.h
@@ -12,6 +12,7 @@ enum {
ROCKCHIP_DDRTYPE_LPDDR2 = 5,
ROCKCHIP_DDRTYPE_LPDDR3 = 6,
ROCKCHIP_DDRTYPE_LPDDR4 = 7,
+ ROCKCHIP_DDRTYPE_LPDDR4X = 8,
};
#endif /* __SOC_ROCKCHIP_GRF_H */
--
2.39.2
The DFI unit can be used to measure DRAM utilization using perf. Add the
node to the device tree. The DFI needs a rockchip,pmu phandle to the pmu
containing registers for SDRAM configuration details. This is added in
this patch as well.
Reviewed-by: Sebastian Reichel <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Sascha Hauer <[email protected]>
---
Notes:
Changes since v4:
- new patch
arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
index 657c019d27fa9..4a445d8704c8f 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
@@ -388,6 +388,11 @@ scmi_shmem: sram@0 {
};
};
+ pmu1grf: syscon@fd58a000 {
+ compatible = "rockchip,rk3588-pmugrf", "syscon", "simple-mfd";
+ reg = <0x0 0xfd58a000 0x0 0x10000>;
+ };
+
sys_grf: syscon@fd58c000 {
compatible = "rockchip,rk3588-sys-grf", "syscon";
reg = <0x0 0xfd58c000 0x0 0x1000>;
@@ -1112,6 +1117,17 @@ qos_vop_m1: qos@fdf82200 {
reg = <0x0 0xfdf82200 0x0 0x20>;
};
+ dfi: dfi@fe060000 {
+ reg = <0x00 0xfe060000 0x00 0x10000>;
+ compatible = "rockchip,rk3588-dfi";
+ interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "ch0", "ch1", "ch2", "ch3";
+ rockchip,pmu = <&pmu1grf>;
+ };
+
gmac1: ethernet@fe1c0000 {
compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a";
reg = <0x0 0xfe1c0000 0x0 0x10000>;
--
2.39.2
This adds rockchip,rk3588-dfi to the list of compatibles. Unlike ealier
SoCs the rk3588 has four interrupts (one for each channel) instead of
only one, so increase the number of allowed interrupts to four.
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Sascha Hauer <[email protected]>
---
Notes:
Changes since v4:
- new patch
Changes since v5:
- drop interrupt-names property
Changes since v4:
- new patch
.../devicetree/bindings/devfreq/event/rockchip,dfi.yaml | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/devfreq/event/rockchip,dfi.yaml b/Documentation/devicetree/bindings/devfreq/event/rockchip,dfi.yaml
index e8b64494ee8bd..50d3fabe958d5 100644
--- a/Documentation/devicetree/bindings/devfreq/event/rockchip,dfi.yaml
+++ b/Documentation/devicetree/bindings/devfreq/event/rockchip,dfi.yaml
@@ -14,6 +14,7 @@ properties:
enum:
- rockchip,rk3399-dfi
- rockchip,rk3568-dfi
+ - rockchip,rk3588-dfi
clocks:
maxItems: 1
@@ -23,7 +24,8 @@ properties:
- const: pclk_ddr_mon
interrupts:
- maxItems: 1
+ minItems: 1
+ maxItems: 4
reg:
maxItems: 1
--
2.39.2
According to the downstream driver the DDRMON_CTRL_LPDDR23 bit must be
set for both LPDDR2 and LPDDR3. Add the missing LPDDR2 case and while
at it turn the if/else if/else into switch/case which makes it easier
to read.
Reviewed-by: Jonathan Cameron <[email protected]>
Reviewed-by: Sebastian Reichel <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Sascha Hauer <[email protected]>
---
drivers/devfreq/event/rockchip-dfi.c | 11 +++++++++--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/drivers/devfreq/event/rockchip-dfi.c b/drivers/devfreq/event/rockchip-dfi.c
index 261d112580c9e..16cd5365671f7 100644
--- a/drivers/devfreq/event/rockchip-dfi.c
+++ b/drivers/devfreq/event/rockchip-dfi.c
@@ -82,12 +82,19 @@ static void rockchip_dfi_start_hardware_counter(struct devfreq_event_dev *edev)
DDRMON_CTRL_HARDWARE_EN), dfi_regs + DDRMON_CTRL);
/* set ddr type to dfi */
- if (dfi->ddr_type == ROCKCHIP_DDRTYPE_LPDDR3)
+ switch (dfi->ddr_type) {
+ case ROCKCHIP_DDRTYPE_LPDDR2:
+ case ROCKCHIP_DDRTYPE_LPDDR3:
writel_relaxed(HIWORD_UPDATE(DDRMON_CTRL_LPDDR23, DDRMON_CTRL_DDR_TYPE_MASK),
dfi_regs + DDRMON_CTRL);
- else if (dfi->ddr_type == ROCKCHIP_DDRTYPE_LPDDR4)
+ break;
+ case ROCKCHIP_DDRTYPE_LPDDR4:
writel_relaxed(HIWORD_UPDATE(DDRMON_CTRL_LPDDR4, DDRMON_CTRL_DDR_TYPE_MASK),
dfi_regs + DDRMON_CTRL);
+ break;
+ default:
+ break;
+ }
/* enable count, use software mode */
writel_relaxed(HIWORD_UPDATE(DDRMON_CTRL_SOFTWARE_EN, DDRMON_CTRL_SOFTWARE_EN),
--
2.39.2
the DFI unit can provide useful data for measuring DDR utilization
and works without any configuration from the board, so enable it in the
dtsi file directly.
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Sascha Hauer <[email protected]>
---
arch/arm64/boot/dts/rockchip/rk3399.dtsi | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index 928948e7c7bbb..fa0a5dbd1b0ec 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -1331,7 +1331,6 @@ dfi: dfi@ff630000 {
interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&cru PCLK_DDR_MON>;
clock-names = "pclk_ddr_mon";
- status = "disabled";
};
vpu: video-codec@ff650000 {
--
2.39.2
The DDR_MON counters are free running counters. These are resetted to 0
when starting them over like currently done when reading the current
counter values.
Resetting the counters becomes a problem with perf support we want to
add later, because perf needs counters that are not modified elsewhere.
This patch removes resetting the counters and keeps them running
instead. That means we no longer use the absolute counter values but
instead compare them with the counter values we read last time. Not
stopping the counters also has the impact that they are running while
we are reading them. We cannot read multiple timers atomically, so
the values do not exactly fit together. The effect should be negligible
though as the time between two measurements is some orders of magnitude
bigger than the time we need to read multiple registers.
Reviewed-by: Sebastian Reichel <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Sascha Hauer <[email protected]>
---
Notes:
Changes since v4:
- rephrase commit message
- Drop unused variable
drivers/devfreq/event/rockchip-dfi.c | 52 ++++++++++++++++------------
1 file changed, 30 insertions(+), 22 deletions(-)
diff --git a/drivers/devfreq/event/rockchip-dfi.c b/drivers/devfreq/event/rockchip-dfi.c
index 680f629da64fc..126bb744645b6 100644
--- a/drivers/devfreq/event/rockchip-dfi.c
+++ b/drivers/devfreq/event/rockchip-dfi.c
@@ -38,11 +38,15 @@
#define DDRMON_CH1_COUNT_NUM 0x3c
#define DDRMON_CH1_DFI_ACCESS_NUM 0x40
-struct dmc_usage {
+struct dmc_count_channel {
u32 access;
u32 total;
};
+struct dmc_count {
+ struct dmc_count_channel c[RK3399_DMC_NUM_CH];
+};
+
/*
* The dfi controller can monitor DDR load. It has an upper and lower threshold
* for the operating points. Whenever the usage leaves these bounds an event is
@@ -51,7 +55,7 @@ struct dmc_usage {
struct rockchip_dfi {
struct devfreq_event_dev *edev;
struct devfreq_event_desc desc;
- struct dmc_usage ch_usage[RK3399_DMC_NUM_CH];
+ struct dmc_count last_event_count;
struct device *dev;
void __iomem *regs;
struct regmap *regmap_pmu;
@@ -85,30 +89,18 @@ static void rockchip_dfi_stop_hardware_counter(struct devfreq_event_dev *edev)
writel_relaxed(SOFTWARE_DIS, dfi_regs + DDRMON_CTRL);
}
-static int rockchip_dfi_get_busier_ch(struct devfreq_event_dev *edev)
+static void rockchip_dfi_read_counters(struct devfreq_event_dev *edev, struct dmc_count *count)
{
struct rockchip_dfi *dfi = devfreq_event_get_drvdata(edev);
- u32 tmp, max = 0;
- u32 i, busier_ch = 0;
+ u32 i;
void __iomem *dfi_regs = dfi->regs;
- rockchip_dfi_stop_hardware_counter(edev);
-
- /* Find out which channel is busier */
for (i = 0; i < RK3399_DMC_NUM_CH; i++) {
- dfi->ch_usage[i].access = readl_relaxed(dfi_regs +
+ count->c[i].access = readl_relaxed(dfi_regs +
DDRMON_CH0_DFI_ACCESS_NUM + i * 20);
- dfi->ch_usage[i].total = readl_relaxed(dfi_regs +
+ count->c[i].total = readl_relaxed(dfi_regs +
DDRMON_CH0_COUNT_NUM + i * 20);
- tmp = dfi->ch_usage[i].access;
- if (tmp > max) {
- busier_ch = i;
- max = tmp;
- }
}
- rockchip_dfi_start_hardware_counter(edev);
-
- return busier_ch;
}
static int rockchip_dfi_disable(struct devfreq_event_dev *edev)
@@ -145,12 +137,28 @@ static int rockchip_dfi_get_event(struct devfreq_event_dev *edev,
struct devfreq_event_data *edata)
{
struct rockchip_dfi *dfi = devfreq_event_get_drvdata(edev);
- int busier_ch;
+ struct dmc_count count;
+ struct dmc_count *last = &dfi->last_event_count;
+ u32 access = 0, total = 0;
+ int i;
+
+ rockchip_dfi_read_counters(edev, &count);
+
+ /* We can only report one channel, so find the busiest one */
+ for (i = 0; i < RK3399_DMC_NUM_CH; i++) {
+ u32 a = count.c[i].access - last->c[i].access;
+ u32 t = count.c[i].total - last->c[i].total;
+
+ if (a > access) {
+ access = a;
+ total = t;
+ }
+ }
- busier_ch = rockchip_dfi_get_busier_ch(edev);
+ edata->load_count = access * 4;
+ edata->total_count = total;
- edata->load_count = dfi->ch_usage[busier_ch].access * 4;
- edata->total_count = dfi->ch_usage[busier_ch].total;
+ dfi->last_event_count = count;
return 0;
}
--
2.39.2
Convert the Rockchip DFI binding to yaml.
Reviewed-by: Rob Herring <[email protected]>
Reviewed-by: Sebastian Reichel <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Sascha Hauer <[email protected]>
---
Notes:
Changes since v4:
- Revert to state of v3 (changes were lost in v4)
.../bindings/devfreq/event/rockchip,dfi.yaml | 61 +++++++++++++++++++
.../bindings/devfreq/event/rockchip-dfi.txt | 18 ------
.../rockchip,rk3399-dmc.yaml | 2 +-
3 files changed, 62 insertions(+), 19 deletions(-)
create mode 100644 Documentation/devicetree/bindings/devfreq/event/rockchip,dfi.yaml
delete mode 100644 Documentation/devicetree/bindings/devfreq/event/rockchip-dfi.txt
diff --git a/Documentation/devicetree/bindings/devfreq/event/rockchip,dfi.yaml b/Documentation/devicetree/bindings/devfreq/event/rockchip,dfi.yaml
new file mode 100644
index 0000000000000..7a82f6ae0701e
--- /dev/null
+++ b/Documentation/devicetree/bindings/devfreq/event/rockchip,dfi.yaml
@@ -0,0 +1,61 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/devfreq/event/rockchip,dfi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Rockchip DFI
+
+maintainers:
+ - Sascha Hauer <[email protected]>
+
+properties:
+ compatible:
+ enum:
+ - rockchip,rk3399-dfi
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ items:
+ - const: pclk_ddr_mon
+
+ interrupts:
+ maxItems: 1
+
+ reg:
+ maxItems: 1
+
+ rockchip,pmu:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ Phandle to the syscon managing the "PMU general register files".
+
+required:
+ - compatible
+ - clocks
+ - clock-names
+ - interrupts
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/rk3308-cru.h>
+
+ bus {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ dfi: dfi@ff630000 {
+ compatible = "rockchip,rk3399-dfi";
+ reg = <0x00 0xff630000 0x00 0x4000>;
+ interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>;
+ rockchip,pmu = <&pmugrf>;
+ clocks = <&cru PCLK_DDR_MON>;
+ clock-names = "pclk_ddr_mon";
+ };
+ };
diff --git a/Documentation/devicetree/bindings/devfreq/event/rockchip-dfi.txt b/Documentation/devicetree/bindings/devfreq/event/rockchip-dfi.txt
deleted file mode 100644
index 148191b0fc158..0000000000000
--- a/Documentation/devicetree/bindings/devfreq/event/rockchip-dfi.txt
+++ /dev/null
@@ -1,18 +0,0 @@
-
-* Rockchip rk3399 DFI device
-
-Required properties:
-- compatible: Must be "rockchip,rk3399-dfi".
-- reg: physical base address of each DFI and length of memory mapped region
-- rockchip,pmu: phandle to the syscon managing the "pmu general register files"
-- clocks: phandles for clock specified in "clock-names" property
-- clock-names : the name of clock used by the DFI, must be "pclk_ddr_mon";
-
-Example:
- dfi: dfi@ff630000 {
- compatible = "rockchip,rk3399-dfi";
- reg = <0x00 0xff630000 0x00 0x4000>;
- rockchip,pmu = <&pmugrf>;
- clocks = <&cru PCLK_DDR_MON>;
- clock-names = "pclk_ddr_mon";
- };
diff --git a/Documentation/devicetree/bindings/memory-controllers/rockchip,rk3399-dmc.yaml b/Documentation/devicetree/bindings/memory-controllers/rockchip,rk3399-dmc.yaml
index fb4920397d08e..aba8649aaeb10 100644
--- a/Documentation/devicetree/bindings/memory-controllers/rockchip,rk3399-dmc.yaml
+++ b/Documentation/devicetree/bindings/memory-controllers/rockchip,rk3399-dmc.yaml
@@ -18,7 +18,7 @@ properties:
$ref: /schemas/types.yaml#/definitions/phandle
description:
Node to get DDR loading. Refer to
- Documentation/devicetree/bindings/devfreq/event/rockchip-dfi.txt.
+ Documentation/devicetree/bindings/devfreq/event/rockchip,dfi.yaml.
clocks:
maxItems: 1
--
2.39.2
struct dmc_count_channel::total counts the clock cycles of the DDR
controller. Rename it accordingly to give the reader a better idea
what this is about. While at it, at some documentation to struct
dmc_count_channel.
Reviewed-by: Sebastian Reichel <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Sascha Hauer <[email protected]>
---
drivers/devfreq/event/rockchip-dfi.c | 19 ++++++++++++-------
1 file changed, 12 insertions(+), 7 deletions(-)
diff --git a/drivers/devfreq/event/rockchip-dfi.c b/drivers/devfreq/event/rockchip-dfi.c
index 8a7af7c32ae0d..50e497455dc69 100644
--- a/drivers/devfreq/event/rockchip-dfi.c
+++ b/drivers/devfreq/event/rockchip-dfi.c
@@ -46,9 +46,14 @@
#define DDRMON_CH1_COUNT_NUM 0x3c
#define DDRMON_CH1_DFI_ACCESS_NUM 0x40
+/**
+ * struct dmc_count_channel - structure to hold counter values from the DDR controller
+ * @access: Number of read and write accesses
+ * @clock_cycles: DDR clock cycles
+ */
struct dmc_count_channel {
u32 access;
- u32 total;
+ u32 clock_cycles;
};
struct dmc_count {
@@ -150,7 +155,7 @@ static void rockchip_dfi_read_counters(struct rockchip_dfi *dfi, struct dmc_coun
continue;
count->c[i].access = readl_relaxed(dfi_regs +
DDRMON_CH0_DFI_ACCESS_NUM + i * 20);
- count->c[i].total = readl_relaxed(dfi_regs +
+ count->c[i].clock_cycles = readl_relaxed(dfi_regs +
DDRMON_CH0_COUNT_NUM + i * 20);
}
}
@@ -182,29 +187,29 @@ static int rockchip_dfi_get_event(struct devfreq_event_dev *edev,
struct rockchip_dfi *dfi = devfreq_event_get_drvdata(edev);
struct dmc_count count;
struct dmc_count *last = &dfi->last_event_count;
- u32 access = 0, total = 0;
+ u32 access = 0, clock_cycles = 0;
int i;
rockchip_dfi_read_counters(dfi, &count);
/* We can only report one channel, so find the busiest one */
for (i = 0; i < DMC_MAX_CHANNELS; i++) {
- u32 a, t;
+ u32 a, c;
if (!(dfi->channel_mask & BIT(i)))
continue;
a = count.c[i].access - last->c[i].access;
- t = count.c[i].total - last->c[i].total;
+ c = count.c[i].clock_cycles - last->c[i].clock_cycles;
if (a > access) {
access = a;
- total = t;
+ clock_cycles = c;
}
}
edata->load_count = access * 4;
- edata->total_count = total;
+ edata->total_count = clock_cycles;
dfi->last_event_count = count;
--
2.39.2
Add rockchip,rk3588-pmugrf compatible string.
Signed-off-by: Sascha Hauer <[email protected]>
---
Notes:
Changes since v5:
- new patch
Documentation/devicetree/bindings/soc/rockchip/grf.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml
index 65a2d5a4f28d8..12f8fe4435584 100644
--- a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml
+++ b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml
@@ -52,6 +52,7 @@ properties:
- rockchip,rk3399-pmugrf
- rockchip,rk3568-grf
- rockchip,rk3568-pmugrf
+ - rockchip,rk3588-pmugrf
- rockchip,rv1108-grf
- rockchip,rv1108-pmugrf
- rockchip,rv1126-grf
--
2.39.2
This adds the rockchip,rk3568-dfi compatible to the binding. Make clocks
optional for this SoC as the RK3568 doesn't have a kernel controllable
PCLK.
Reviewed-by: Conor Dooley <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Sascha Hauer <[email protected]>
---
.../bindings/devfreq/event/rockchip,dfi.yaml | 15 +++++++++++++--
1 file changed, 13 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/devfreq/event/rockchip,dfi.yaml b/Documentation/devicetree/bindings/devfreq/event/rockchip,dfi.yaml
index 7a82f6ae0701e..e8b64494ee8bd 100644
--- a/Documentation/devicetree/bindings/devfreq/event/rockchip,dfi.yaml
+++ b/Documentation/devicetree/bindings/devfreq/event/rockchip,dfi.yaml
@@ -13,6 +13,7 @@ properties:
compatible:
enum:
- rockchip,rk3399-dfi
+ - rockchip,rk3568-dfi
clocks:
maxItems: 1
@@ -34,11 +35,21 @@ properties:
required:
- compatible
- - clocks
- - clock-names
- interrupts
- reg
+if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - rockchip,rk3399-dfi
+
+then:
+ required:
+ - clocks
+ - clock-names
+
additionalProperties: false
examples:
--
2.39.2
Hello Sascha,
On Fri, Jun 16, 2023 at 6:22 AM Sascha Hauer <[email protected]> wrote:
> - Add more reviewed-by tags
Can you explain how the Tested-Bys are handled, I don't see any patch
with those tags, not Sebastians, nor mine. Is the testing useful ? Should I
retest the new patchset ?
Regards
--
Vincent Legoll
On Fri, Jun 16, 2023 at 08:20:58AM +0200, Sascha Hauer wrote:
> Add rockchip,rk3588-pmugrf compatible string.
>
> Signed-off-by: Sascha Hauer <[email protected]>
Acked-by: Conor Dooley <[email protected]>
Cheers,
Conor.
On Fri, Jun 16, 2023 at 08:20:57AM +0200, Sascha Hauer wrote:
> This adds rockchip,rk3588-dfi to the list of compatibles. Unlike ealier
> SoCs the rk3588 has four interrupts (one for each channel) instead of
> only one, so increase the number of allowed interrupts to four.
>
> Link: https://lore.kernel.org/r/[email protected]
It's unclear what the point of this link is.
My comment still stands about whether only the new compatible should be
permitted to have more than one interrupt. I don't recall a response to
that question on the last version.
Cheers,
Conor.
> Signed-off-by: Sascha Hauer <[email protected]>
> ---
>
> Notes:
> Changes since v4:
> - new patch
>
> Changes since v5:
> - drop interrupt-names property
>
> Changes since v4:
> - new patch
>
> .../devicetree/bindings/devfreq/event/rockchip,dfi.yaml | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/devfreq/event/rockchip,dfi.yaml b/Documentation/devicetree/bindings/devfreq/event/rockchip,dfi.yaml
> index e8b64494ee8bd..50d3fabe958d5 100644
> --- a/Documentation/devicetree/bindings/devfreq/event/rockchip,dfi.yaml
> +++ b/Documentation/devicetree/bindings/devfreq/event/rockchip,dfi.yaml
> @@ -14,6 +14,7 @@ properties:
> enum:
> - rockchip,rk3399-dfi
> - rockchip,rk3568-dfi
> + - rockchip,rk3588-dfi
>
> clocks:
> maxItems: 1
> @@ -23,7 +24,8 @@ properties:
> - const: pclk_ddr_mon
>
> interrupts:
> - maxItems: 1
> + minItems: 1
> + maxItems: 4
>
> reg:
> maxItems: 1
> --
> 2.39.2
>
Hi Vincent,
On Fri, Jun 16, 2023 at 01:50:42PM +0000, Vincent Legoll wrote:
> Hello Sascha,
>
> On Fri, Jun 16, 2023 at 6:22 AM Sascha Hauer <[email protected]> wrote:
> > - Add more reviewed-by tags
>
> Can you explain how the Tested-Bys are handled, I don't see any patch
> with those tags, not Sebastians, nor mine. Is the testing useful ? Should I
> retest the new patchset ?
I really appreciate that you are testing this series. However, changes
to the series often invlidate the testing, that's why I haven't added
your tested-by tags when sending a new series. The tested-by tags would
have to be collected from the person finally applying the series.
Regards,
Sascha
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
On Fri, Jun 16, 2023 at 08:05:33PM +0100, Conor Dooley wrote:
> On Fri, Jun 16, 2023 at 08:20:57AM +0200, Sascha Hauer wrote:
> > This adds rockchip,rk3588-dfi to the list of compatibles. Unlike ealier
> > SoCs the rk3588 has four interrupts (one for each channel) instead of
> > only one, so increase the number of allowed interrupts to four.
> >
> > Link: https://lore.kernel.org/r/[email protected]
>
> It's unclear what the point of this link is.
The link was added automatically by b4. I re-applied the series from the
last one I sent just to be sure that I base my work for the new series
on the one I sent last time. I didn't remember that b4 adds these links,
I should have disabled that option.
> My comment still stands about whether only the new compatible should be
> permitted to have more than one interrupt. I don't recall a response to
> that question on the last version.
My personal take on this is that such additions make the bindings more
readable by machines, but less by humans. That's why I don't have enough
intrinsic motivation to make this change. Anyway, if you insist then
I'll make it for the next round.
Sascha
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
On Wed, Jun 21, 2023 at 09:41:59AM +0200, Sascha Hauer wrote:
> On Fri, Jun 16, 2023 at 08:05:33PM +0100, Conor Dooley wrote:
> > On Fri, Jun 16, 2023 at 08:20:57AM +0200, Sascha Hauer wrote:
> > > This adds rockchip,rk3588-dfi to the list of compatibles. Unlike ealier
> > > SoCs the rk3588 has four interrupts (one for each channel) instead of
> > > only one, so increase the number of allowed interrupts to four.
> > >
> > > Link: https://lore.kernel.org/r/[email protected]
> >
> > It's unclear what the point of this link is.
>
> The link was added automatically by b4. I re-applied the series from the
> last one I sent just to be sure that I base my work for the new series
> on the one I sent last time. I didn't remember that b4 adds these links,
> I should have disabled that option.
Ah, I see.
> > My comment still stands about whether only the new compatible should be
> > permitted to have more than one interrupt. I don't recall a response to
> > that question on the last version.
>
> My personal take on this is that such additions make the bindings more
> readable by machines, but less by humans. That's why I don't have enough
> intrinsic motivation to make this change.
> Anyway, if you insist then I'll make it for the next round.
No, I don't insist. I just wanted to not be ignored.
Acked-by: Conor Dooley <[email protected]>
Cheers,
Conor.
Hi,
On Fri, Oct 06, 2023 at 11:20:09AM +0900, Chanwoo Choi wrote:
> Hi Sascha,
> The Cc of this series doesn't contain me so that I didn't know thise
> series.
> Anyway, I'll review them today.
I wasn't aware that I forgot to Cc you, sorry for that. Thanks for your
feedback, I'll address the comments soon and send an updated series.
Thanks
Sascha
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |