From: Kory Maincent <[email protected]>
The current check of ch_en enabled to know the maximum number of available
hardware channels is wrong as it check the number of ch_en register set
but all of them are unset at probe. This register is set at the
dw_hdma_v0_core_start function which is run lately before a DMA transfer.
The HDMA IP have no way to know the number of hardware channels available
like the eDMA IP, then let set it to maximum channels and let the platform
set the right number of channels.
Fixes: e74c39573d35 ("dmaengine: dw-edma: Add support for native HDMA")
Signed-off-by: Kory Maincent <[email protected]>
---
See the following thread mail that talk about this issue:
https://lore.kernel.org/lkml/20230607095832.6d6b1a73@kmaincent-XPS-13-7390/
This patch is fixing a commit which is only in dmaengine tree and not
merged mainline.
---
drivers/dma/dw-edma/dw-hdma-v0-core.c | 13 +------------
1 file changed, 1 insertion(+), 12 deletions(-)
diff --git a/drivers/dma/dw-edma/dw-hdma-v0-core.c b/drivers/dma/dw-edma/dw-hdma-v0-core.c
index 00b735a0202a..de87ce6b8585 100644
--- a/drivers/dma/dw-edma/dw-hdma-v0-core.c
+++ b/drivers/dma/dw-edma/dw-hdma-v0-core.c
@@ -65,18 +65,7 @@ static void dw_hdma_v0_core_off(struct dw_edma *dw)
static u16 dw_hdma_v0_core_ch_count(struct dw_edma *dw, enum dw_edma_dir dir)
{
- u32 num_ch = 0;
- int id;
-
- for (id = 0; id < HDMA_V0_MAX_NR_CH; id++) {
- if (GET_CH_32(dw, id, dir, ch_en) & BIT(0))
- num_ch++;
- }
-
- if (num_ch > HDMA_V0_MAX_NR_CH)
- num_ch = HDMA_V0_MAX_NR_CH;
-
- return (u16)num_ch;
+ return HDMA_V0_MAX_NR_CH;
}
static enum dma_status dw_hdma_v0_core_ch_status(struct dw_edma_chan *chan)
--
2.25.1
On Fri, Jun 09, 2023 at 10:16:46AM +0200, K?ry Maincent wrote:
> From: Kory Maincent <[email protected]>
>
> The current check of ch_en enabled to know the maximum number of available
> hardware channels is wrong as it check the number of ch_en register set
> but all of them are unset at probe. This register is set at the
> dw_hdma_v0_core_start function which is run lately before a DMA transfer.
>
> The HDMA IP have no way to know the number of hardware channels available
> like the eDMA IP, then let set it to maximum channels and let the platform
> set the right number of channels.
>
> Fixes: e74c39573d35 ("dmaengine: dw-edma: Add support for native HDMA")
> Signed-off-by: Kory Maincent <[email protected]>
> ---
>
> See the following thread mail that talk about this issue:
> https://lore.kernel.org/lkml/20230607095832.6d6b1a73@kmaincent-XPS-13-7390/
>
> This patch is fixing a commit which is only in dmaengine tree and not
> merged mainline.
> ---
> drivers/dma/dw-edma/dw-hdma-v0-core.c | 13 +------------
> 1 file changed, 1 insertion(+), 12 deletions(-)
>
> diff --git a/drivers/dma/dw-edma/dw-hdma-v0-core.c b/drivers/dma/dw-edma/dw-hdma-v0-core.c
> index 00b735a0202a..de87ce6b8585 100644
> --- a/drivers/dma/dw-edma/dw-hdma-v0-core.c
> +++ b/drivers/dma/dw-edma/dw-hdma-v0-core.c
> @@ -65,18 +65,7 @@ static void dw_hdma_v0_core_off(struct dw_edma *dw)
>
> static u16 dw_hdma_v0_core_ch_count(struct dw_edma *dw, enum dw_edma_dir dir)
> {
> - u32 num_ch = 0;
> - int id;
> -
> - for (id = 0; id < HDMA_V0_MAX_NR_CH; id++) {
> - if (GET_CH_32(dw, id, dir, ch_en) & BIT(0))
> - num_ch++;
> - }
> -
> - if (num_ch > HDMA_V0_MAX_NR_CH)
> - num_ch = HDMA_V0_MAX_NR_CH;
> -
> - return (u16)num_ch;
> + return HDMA_V0_MAX_NR_CH;
Mainly I am ok with this change. But it would be nice to have a
comment inlined here of why the number of channels is fixed and that
the platform is responsible for specifying the real number of channels
(it's basically what you described in the patch log).
Cai, what do you think about the patch? Is it suitable for you? Do you
have any idea of how to workaround the denoted problem without always
returning the maximum number of channels?
-Serge(y)
> }
>
> static enum dma_status dw_hdma_v0_core_ch_status(struct dw_edma_chan *chan)
> --
> 2.25.1
>
On Mon, 19 Jun 2023 00:07:09 +0300
Serge Semin <[email protected]> wrote:
> > diff --git a/drivers/dma/dw-edma/dw-hdma-v0-core.c
> > b/drivers/dma/dw-edma/dw-hdma-v0-core.c index 00b735a0202a..de87ce6b8585
> > 100644 --- a/drivers/dma/dw-edma/dw-hdma-v0-core.c
> > +++ b/drivers/dma/dw-edma/dw-hdma-v0-core.c
> > @@ -65,18 +65,7 @@ static void dw_hdma_v0_core_off(struct dw_edma *dw)
> >
> > static u16 dw_hdma_v0_core_ch_count(struct dw_edma *dw, enum dw_edma_dir
> > dir) {
> > - u32 num_ch = 0;
> > - int id;
> > -
> > - for (id = 0; id < HDMA_V0_MAX_NR_CH; id++) {
> > - if (GET_CH_32(dw, id, dir, ch_en) & BIT(0))
> > - num_ch++;
> > - }
> > -
> > - if (num_ch > HDMA_V0_MAX_NR_CH)
> > - num_ch = HDMA_V0_MAX_NR_CH;
> > -
> > - return (u16)num_ch;
> > + return HDMA_V0_MAX_NR_CH;
>
> Mainly I am ok with this change. But it would be nice to have a
> comment inlined here of why the number of channels is fixed and that
> the platform is responsible for specifying the real number of channels
> (it's basically what you described in the patch log).
Ok I will, thanks for your review.
Köry