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Subject: [PATCH v5 8/9] mips: ralink: get cpu rate from new driver code

At very early stage on boot, there is a need to set 'mips_hpt_frequency'.
This timer frequency is a half of the CPU frequency. To get clocks properly
set we need to call to 'of_clk_init()' and properly get cpu clock frequency
afterwards. Depending on the SoC, CPU clock index and compatible differs, so
use them to get the proper clock frm the clock provider. Hence, adapt code
to be aligned with new clock driver.

Signed-off-by: Sergio Paracuellos <[email protected]>
---
arch/mips/ralink/clk.c | 61 +++++++++++++++++++++++++++++++++++-------
1 file changed, 52 insertions(+), 9 deletions(-)

diff --git a/arch/mips/ralink/clk.c b/arch/mips/ralink/clk.c
index 5b02bb7e0829..9db73fcac522 100644
--- a/arch/mips/ralink/clk.c
+++ b/arch/mips/ralink/clk.c
@@ -11,29 +11,72 @@
#include <linux/clkdev.h>
#include <linux/clk.h>
#include <linux/clk-provider.h>
+#include <asm/mach-ralink/ralink_regs.h>

#include <asm/time.h>

#include "common.h"

-void ralink_clk_add(const char *dev, unsigned long rate)
+static const char *clk_cpu(int *idx)
{
- struct clk *clk = clk_register_fixed_rate(NULL, dev, NULL, 0, rate);
-
- if (!clk)
- panic("failed to add clock");
-
- clkdev_create(clk, NULL, "%s", dev);
+ switch (ralink_soc) {
+ case RT2880_SOC:
+ *idx = 0;
+ return "ralink,rt2880-sysc";
+ case RT3883_SOC:
+ *idx = 0;
+ return "ralink,rt3883-sysc";
+ case RT305X_SOC_RT3050:
+ *idx = 0;
+ return "ralink,rt3050-sysc";
+ case RT305X_SOC_RT3052:
+ *idx = 0;
+ return "ralink,rt3052-sysc";
+ case RT305X_SOC_RT3350:
+ *idx = 1;
+ return "ralink,rt3350-sysc";
+ case RT305X_SOC_RT3352:
+ *idx = 1;
+ return "ralink,rt3352-sysc";
+ case RT305X_SOC_RT5350:
+ *idx = 1;
+ return "ralink,rt5350-sysc";
+ case MT762X_SOC_MT7620A:
+ *idx = 2;
+ return "ralink,mt7620-sysc";
+ case MT762X_SOC_MT7620N:
+ *idx = 2;
+ return "ralink,mt7620-sysc";
+ case MT762X_SOC_MT7628AN:
+ *idx = 1;
+ return "ralink,mt7628-sysc";
+ case MT762X_SOC_MT7688:
+ *idx = 1;
+ return "ralink,mt7688-sysc";
+ default:
+ *idx = -1;
+ return "invalid";
+ }
}

void __init plat_time_init(void)
{
+ struct of_phandle_args clkspec;
+ const char *compatible;
struct clk *clk;
+ int cpu_clk_idx;

ralink_of_remap();

- ralink_clk_init();
- clk = clk_get_sys("cpu", NULL);
+ compatible = clk_cpu(&cpu_clk_idx);
+ if (cpu_clk_idx == -1)
+ panic("unable to get CPU clock index");
+
+ of_clk_init(NULL);
+ clkspec.np = of_find_compatible_node(NULL, NULL, compatible);
+ clkspec.args_count = 1;
+ clkspec.args[0] = cpu_clk_idx;
+ clk = of_clk_get_from_provider(&clkspec);
if (IS_ERR(clk))
panic("unable to get CPU clock, err=%ld", PTR_ERR(clk));
pr_info("CPU Clock: %ldMHz\n", clk_get_rate(clk) / 1000000);
--
2.25.1

2023-06-19 04:43:57

by Sergio Paracuellos

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Subject: [PATCH v5 4/9] mips: ralink: rt305x: remove clock related code

A properly clock driver for ralink SoCs has been added. Hence there is no
need to have clock related code in 'arch/mips/ralink' folder anymore.

Signed-off-by: Sergio Paracuellos <[email protected]>
---
arch/mips/include/asm/mach-ralink/rt305x.h | 21 ------
arch/mips/ralink/rt305x.c | 78 ----------------------
2 files changed, 99 deletions(-)

diff --git a/arch/mips/include/asm/mach-ralink/rt305x.h b/arch/mips/include/asm/mach-ralink/rt305x.h
index ef58f7bff957..4fc5c279cd75 100644
--- a/arch/mips/include/asm/mach-ralink/rt305x.h
+++ b/arch/mips/include/asm/mach-ralink/rt305x.h
@@ -67,26 +67,9 @@ static inline int soc_is_rt5350(void)
#define CHIP_ID_ID_SHIFT 8
#define CHIP_ID_REV_MASK 0xff

-#define RT305X_SYSCFG_CPUCLK_SHIFT 18
-#define RT305X_SYSCFG_CPUCLK_MASK 0x1
-#define RT305X_SYSCFG_CPUCLK_LOW 0x0
-#define RT305X_SYSCFG_CPUCLK_HIGH 0x1
-
#define RT305X_SYSCFG_SRAM_CS0_MODE_SHIFT 2
-#define RT305X_SYSCFG_CPUCLK_MASK 0x1
#define RT305X_SYSCFG_SRAM_CS0_MODE_WDT 0x1

-#define RT3352_SYSCFG0_CPUCLK_SHIFT 8
-#define RT3352_SYSCFG0_CPUCLK_MASK 0x1
-#define RT3352_SYSCFG0_CPUCLK_LOW 0x0
-#define RT3352_SYSCFG0_CPUCLK_HIGH 0x1
-
-#define RT5350_SYSCFG0_CPUCLK_SHIFT 8
-#define RT5350_SYSCFG0_CPUCLK_MASK 0x3
-#define RT5350_SYSCFG0_CPUCLK_360 0x0
-#define RT5350_SYSCFG0_CPUCLK_320 0x2
-#define RT5350_SYSCFG0_CPUCLK_300 0x3
-
#define RT5350_SYSCFG0_DRAM_SIZE_SHIFT 12
#define RT5350_SYSCFG0_DRAM_SIZE_MASK 7
#define RT5350_SYSCFG0_DRAM_SIZE_2M 0
@@ -117,13 +100,9 @@ static inline int soc_is_rt5350(void)

#define RT3352_SYSC_REG_SYSCFG0 0x010
#define RT3352_SYSC_REG_SYSCFG1 0x014
-#define RT3352_SYSC_REG_CLKCFG1 0x030
#define RT3352_SYSC_REG_RSTCTRL 0x034
#define RT3352_SYSC_REG_USB_PS 0x05c

-#define RT3352_CLKCFG0_XTAL_SEL BIT(20)
-#define RT3352_CLKCFG1_UPHY0_CLK_EN BIT(18)
-#define RT3352_CLKCFG1_UPHY1_CLK_EN BIT(20)
#define RT3352_RSTCTRL_UHST BIT(22)
#define RT3352_RSTCTRL_UDEV BIT(25)
#define RT3352_SYSCFG1_USB0_HOST_MODE BIT(10)
diff --git a/arch/mips/ralink/rt305x.c b/arch/mips/ralink/rt305x.c
index d8dcc5cc66cc..9cffe69dd11d 100644
--- a/arch/mips/ralink/rt305x.c
+++ b/arch/mips/ralink/rt305x.c
@@ -56,84 +56,6 @@ static unsigned long rt5350_get_mem_size(void)
return ret;
}

-void __init ralink_clk_init(void)
-{
- unsigned long cpu_rate, sys_rate, wdt_rate, uart_rate;
- unsigned long wmac_rate = 40000000;
-
- u32 t = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG);
-
- if (soc_is_rt305x() || soc_is_rt3350()) {
- t = (t >> RT305X_SYSCFG_CPUCLK_SHIFT) &
- RT305X_SYSCFG_CPUCLK_MASK;
- switch (t) {
- case RT305X_SYSCFG_CPUCLK_LOW:
- cpu_rate = 320000000;
- break;
- case RT305X_SYSCFG_CPUCLK_HIGH:
- cpu_rate = 384000000;
- break;
- }
- sys_rate = uart_rate = wdt_rate = cpu_rate / 3;
- } else if (soc_is_rt3352()) {
- t = (t >> RT3352_SYSCFG0_CPUCLK_SHIFT) &
- RT3352_SYSCFG0_CPUCLK_MASK;
- switch (t) {
- case RT3352_SYSCFG0_CPUCLK_LOW:
- cpu_rate = 384000000;
- break;
- case RT3352_SYSCFG0_CPUCLK_HIGH:
- cpu_rate = 400000000;
- break;
- }
- sys_rate = wdt_rate = cpu_rate / 3;
- uart_rate = 40000000;
- } else if (soc_is_rt5350()) {
- t = (t >> RT5350_SYSCFG0_CPUCLK_SHIFT) &
- RT5350_SYSCFG0_CPUCLK_MASK;
- switch (t) {
- case RT5350_SYSCFG0_CPUCLK_360:
- cpu_rate = 360000000;
- sys_rate = cpu_rate / 3;
- break;
- case RT5350_SYSCFG0_CPUCLK_320:
- cpu_rate = 320000000;
- sys_rate = cpu_rate / 4;
- break;
- case RT5350_SYSCFG0_CPUCLK_300:
- cpu_rate = 300000000;
- sys_rate = cpu_rate / 3;
- break;
- default:
- BUG();
- }
- uart_rate = 40000000;
- wdt_rate = sys_rate;
- } else {
- BUG();
- }
-
- if (soc_is_rt3352() || soc_is_rt5350()) {
- u32 val = rt_sysc_r32(RT3352_SYSC_REG_SYSCFG0);
-
- if (!(val & RT3352_CLKCFG0_XTAL_SEL))
- wmac_rate = 20000000;
- }
-
- ralink_clk_add("cpu", cpu_rate);
- ralink_clk_add("sys", sys_rate);
- ralink_clk_add("10000900.i2c", uart_rate);
- ralink_clk_add("10000a00.i2s", uart_rate);
- ralink_clk_add("10000b00.spi", sys_rate);
- ralink_clk_add("10000b40.spi", sys_rate);
- ralink_clk_add("10000100.timer", wdt_rate);
- ralink_clk_add("10000120.watchdog", wdt_rate);
- ralink_clk_add("10000500.uart", uart_rate);
- ralink_clk_add("10000c00.uartlite", uart_rate);
- ralink_clk_add("10100000.ethernet", sys_rate);
- ralink_clk_add("10180000.wmac", wmac_rate);
-}
-
void __init ralink_of_remap(void)
{
rt_sysc_membase = plat_of_remap_node("ralink,rt3050-sysc");
--
2.25.1

2023-06-19 04:44:36

by Sergio Paracuellos

[permalink] [raw]

On Mon, Jun 19, 2023 at 06:09:32AM +0200, Sergio Paracuellos wrote:
> Hi all!
>
> This patchset is a big effort to properly implement a clock and reset
> driver for old ralink SoCs. This allow to properly define clocks in
> device tree and avoid to use fixed-clocks directly from 'arch/mips/ralink'
> architecture directory code.
>
> Device tree 'sysc' node will be both clock and reset provider using
> 'clock-cells' and 'reset-cells' properties.
>
> The ralink SoCs we are taking about are RT2880, RT3050, RT3052, RT3350,
> RT3352, RT3883, RT5350, MT7620, MT7628 and MT7688. Mostly the code in
> this new driver has been extracted from 'arch/mips/ralink' and cleanly
> put using kernel clock and reset driver APIs. The clock plans for this
> SoCs only talks about relation between CPU frequency and BUS frequency.
> This relation is different depending on the particular SoC. CPU clock is
> derived from XTAL frequencies.
>
> Depending on the SoC we have the following frequencies:
> * RT2880 SoC:
> - XTAL: 40 MHz.
> - CPU: 250, 266, 280 or 300 MHz.
> - BUS: CPU / 2 MHz.
> * RT3050, RT3052, RT3350:
> - XTAL: 40 MHz.
> - CPU: 320 or 384 MHz.
> - BUS: CPU / 3 MHz.
> * RT3352:
> - XTAL: 40 MHz.
> - CPU: 384 or 400 MHz.
> - BUS: CPU / 3 MHz.
> - PERIPH: 40 MHz.
> * RT3383:
> - XTAL: 40 MHz.
> - CPU: 250, 384, 480 or 500 MHz.
> - BUS: Depends on RAM Type and CPU:
> + RAM DDR2: 125. ELSE 83 MHz.
> + RAM DDR2: 128. ELSE 96 MHz.
> + RAM DDR2: 160. ELSE 120 MHz.
> + RAM DDR2: 166. ELSE 125 MHz.
> * RT5350:
> - XTAL: 40 MHz.
> - CPU: 300, 320 or 360 MHz.
> - BUS: CPU / 3, CPU / 4, CPU / 3 MHz.
> - PERIPH: 40 MHz.
> * MT7628 and MT7688:
> - XTAL: 20 MHz or 40 MHz.
> - CPU: 575 or 580 MHz.
> - BUS: CPU / 3.
> - PCMI2S: 480 MHz.
> - PERIPH: 40 MHz.
> * MT7620:
> - XTAL: 20 MHz or 40 MHz.
> - PLL: XTAL, 480, 600 MHz.
> - CPU: depends on PLL and some mult and dividers.
> - BUS: depends on PLL and some mult and dividers.
> - PERIPH: 40 or XTAL MHz.
>
> MT7620 is a bit more complex deriving CPU clock from a PLL and an bunch of
> register reads and predividers. To derive CPU and BUS frequencies in the
> MT7620 SoC 'mt7620_calc_rate()' helper is used.
> In the case XTAL can have different frequencies and we need a different
> clock frequency for peripherals 'periph' clock in introduced.
> The rest of the peripherals present in the SoC just follow their parent
> frequencies.
>
> I am using 'mtmips' inside for ralink clock driver. This is aligned with
> pinctrl series recently merged through pinctrl git tree [0].
>
> I am maintaining ralink as prefix for compatible strings after discussions
> between Rob and Arinc in v2 of this series [1].
>
> Changes have been compile tested for:
> - RT2880
> - RT3883
>
> Changes have been properly tested in:
> - RT5350 SoC based board (ALL5003 board)
> - MT7620A SoC based board (Haier HW-L1W)
> - MT7628AN SoC based board (Motorola MWR03)
>
> All of them resulting in a working platform.
>
> Dts files for these SoCs in-tree except MT7621 are incomplete. We are
> planning to align with openWRT files at some point and add extra needed
> changes. Hence I am not touching them at all in these series. If this is
> a problem, please let me know and I will update them.
>
> Talking about merging this series I'd like all of the patches going through
> the MIPS tree if possible.
>
> Thanks in advance for your time.
>
> Best regards,
> Sergio Paracuellos
>
> Changes in v5:
> - Address comments of Shiji Yang in v4.
> - Make use 'of_find_compatible_node()' instead of 'of_find_node_by_name()' since
> node names must not be an ABI (Thanks Krzysztof!!!)
> - Test this changes in mt7620a Soc based board and MT7628AN Soc based board (Thanks Shiji Yang!!!)
>
> Changes in v4:
> - Collect Reviewed-by and Acked-by tags.
> - Pass proper data for 'ralink,rt3352-sysc' and 'ralink,rt3883-sysc' compatible string.
>
> Changes in v3:
> - Address Stephen comments in v2:
> + Drop unsused include '<linux/clk.h>'.
> + Add fixed and factor clocks when it makes sense.
> + Make 'mtmips_periph_clk_ops' named variable.
> + WARN_ON -> WARN_ON_ONCE.
> + Avoid CONFIG_USB dependent code. Introduce new 'mtmips_clk_regs_init'.
> + Don't validate the bindings in the driver.
> + Make const 'struct clk_init_data' used inside macros.
> + do_div -> div_u64.
> + Make use of dev_err_probe.
>
> Changes in v2:
> - Address bindings documentation changes pointed out by Krzysztof:
> + Rename the file into 'mediatek,mtmips-sysc.yaml'.
> + Redo commit subject and log message.
> + Order compatibles alphabetically.
> + Redo bindings description taking into account this is a system
> controller node which provides both clocks and resets to the world.
> + Drop label from example.
> + Use 'syscon' as node name in example.
> + Drop no sense 'ralink,rt2880-reset' compatible string
> - Squash patches 6 and 7 together as pointed out by Stephen Boyd.
>
> Previoous series:
> v4: https://lore.kernel.org/linux-clk/[email protected]/T/#t
> v3: https://lore.kernel.org/linux-mips/[email protected]/T/#mafbc1704938b94a367c4b6240d9880a67be1f92f
> v2: https://lore.kernel.org/linux-clk/CAMhs-H-BfZb3mD8E=LeJ4vT22uibQ1DnaZsfTrtRxSiv=8L5RA@mail.gmail.com/T/#t
> v1: https://lore.kernel.org/linux-clk/[email protected]/T/#t
>
> [0]: https://lore.kernel.org/linux-gpio/[email protected]/T/#t
> [1]: https://lore.kernel.org/linux-clk/CAMhs-H-BfZb3mD8E=LeJ4vT22uibQ1DnaZsfTrtRxSiv=8L5RA@mail.gmail.com/T/#mfe725b6e3382c6fb09736472a846cbbc84f264dc
>
> Sergio Paracuellos (9):
> dt-bindings: clock: add mtmips SoCs system controller
> clk: ralink: add clock and reset driver for MTMIPS SoCs
> mips: ralink: rt288x: remove clock related code
> mips: ralink: rt305x: remove clock related code
> mips: ralink: rt3883: remove clock related code
> mips: ralink: mt7620: remove clock related code
> mips: ralink: remove reset related code
> mips: ralink: get cpu rate from new driver code
> MAINTAINERS: add Mediatek MTMIPS Clock maintainer
>
> .../bindings/clock/mediatek,mtmips-sysc.yaml | 64 +
> MAINTAINERS | 6 +
> arch/mips/include/asm/mach-ralink/mt7620.h | 35 -
> arch/mips/include/asm/mach-ralink/rt288x.h | 10 -
> arch/mips/include/asm/mach-ralink/rt305x.h | 21 -
> arch/mips/include/asm/mach-ralink/rt3883.h | 8 -
> arch/mips/ralink/clk.c | 61 +-
> arch/mips/ralink/common.h | 5 -
> arch/mips/ralink/mt7620.c | 226 ----
> arch/mips/ralink/of.c | 4 -
> arch/mips/ralink/reset.c | 61 -
> arch/mips/ralink/rt288x.c | 31 -
> arch/mips/ralink/rt305x.c | 78 --
> arch/mips/ralink/rt3883.c | 44 -
> drivers/clk/ralink/Kconfig | 7 +
> drivers/clk/ralink/Makefile | 1 +
> drivers/clk/ralink/clk-mtmips.c | 1115 +++++++++++++++++
> 17 files changed, 1245 insertions(+), 532 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mtmips-sysc.yaml
> create mode 100644 drivers/clk/ralink/clk-mtmips.c

series applied to mips-next.

Thomas.

--
Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
good idea. [ RFC1925, 2.3 ]