This series enables the hardware decoder present on mt8183. At first
glance, the only missing piece is the devicetree node for it, however,
simply adding it as is would cause an address collision between the
first register iospace and the clock-controller node, so a rework of the
dt-binding and driver, as well as addition of a new syscon phandle
property, were needed first.
Tested that H264 decoding works with the hardware decoder on
mt8183-kukui-jacuzzi-juniper-sku16, giving a fluster score of 98/135 on
the JVT-AVC_V1 test suite. And ensured other SoCs (MT8192 and MT8195)
still work as usual.
Changes in v3:
- Switched the handling of the VDEC_HW_ACTIVE bit to use a syscon
instead of the 'active' clock
Changes in v2:
- Merged commit 1 (media: dt-bindings: mediatek,vcodec: Allow single
clock for mt8183) into commit 3 (media: dt-bindings: mediatek,vcodec:
Remove VDEC_SYS for mt8183)
- Further constrained properties in dt-binding
- Added CLK_IGNORE_UNUSED flag to active clock
- Reformatted reg-names in DT node
Nícolas F. R. A. Prado (5):
media: dt-bindings: mediatek,vcodec: Allow single clock for mt8183
media: dt-bindings: mediatek,vcodec: Don't require assigned-clocks
media: dt-bindings: mediatek,vcodec: Remove VDEC_SYS for mt8183
media: mediatek: vcodec: Define address for VDEC_HW_ACTIVE
media: mediatek: vcodec: Read HW active status from syscon on MT8183
Yunfei Dong (1):
arm64: dts: mediatek: mt8183: Add decoder
.../media/mediatek,vcodec-decoder.yaml | 69 +++++++++++++++---
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 30 ++++++++
.../mediatek/vcodec/mtk_vcodec_dec_drv.c | 71 ++++++++++++++++---
.../mediatek/vcodec/mtk_vcodec_dec_hw.c | 4 +-
.../mediatek/vcodec/mtk_vcodec_dec_hw.h | 3 +-
.../platform/mediatek/vcodec/mtk_vcodec_drv.h | 1 +
6 files changed, 153 insertions(+), 25 deletions(-)
--
2.41.0
From: Yunfei Dong <[email protected]>
Add node for the hardware decoder present on the MT8183 SoC.
Signed-off-by: Yunfei Dong <[email protected]>
Signed-off-by: Qianqian Yan <[email protected]>
Signed-off-by: Frederic Chen <[email protected]>
Signed-off-by: Alexandre Courbot <[email protected]>
Signed-off-by: Nícolas F. R. A. Prado <[email protected]>
Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
---
Changes in v3:
- Dropped 'active' clock and added the 'mediatek,vdecsys' syscon phandle
property instead
Changes in v2:
- Reformatted reg-names to fit in fewer lines
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 30 ++++++++++++++++++++++++
1 file changed, 30 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index 5169779d01df..4144f1ed3ff0 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
@@ -2019,6 +2019,36 @@ vdecsys: syscon@16000000 {
#clock-cells = <1>;
};
+ vcodec_dec: video-codec@16020000 {
+ compatible = "mediatek,mt8183-vcodec-dec";
+ reg = <0 0x16020000 0 0x1000>, /* VDEC_MISC */
+ <0 0x16021000 0 0x800>, /* VDEC_VLD */
+ <0 0x16021800 0 0x800>, /* VDEC_TOP */
+ <0 0x16022000 0 0x1000>, /* VDEC_MC */
+ <0 0x16023000 0 0x1000>, /* VDEC_AVCVLD */
+ <0 0x16024000 0 0x1000>, /* VDEC_AVCMV */
+ <0 0x16025000 0 0x1000>, /* VDEC_PP */
+ <0 0x16026800 0 0x800>, /* VP8_VD */
+ <0 0x16027000 0 0x800>, /* VP6_VD */
+ <0 0x16027800 0 0x800>, /* VP8_VL */
+ <0 0x16028400 0 0x400>; /* VP9_VD */
+ reg-names = "misc", "ld", "top", "cm", "ad", "av", "pp",
+ "hwd", "hwq", "hwb", "hwg";
+ interrupts = <GIC_SPI 250 IRQ_TYPE_LEVEL_LOW>;
+ iommus = <&iommu M4U_PORT_HW_VDEC_MC_EXT>,
+ <&iommu M4U_PORT_HW_VDEC_PP_EXT>,
+ <&iommu M4U_PORT_HW_VDEC_VLD_EXT>,
+ <&iommu M4U_PORT_HW_VDEC_AVC_MV_EXT>,
+ <&iommu M4U_PORT_HW_VDEC_PRED_RD_EXT>,
+ <&iommu M4U_PORT_HW_VDEC_PRED_WR_EXT>,
+ <&iommu M4U_PORT_HW_VDEC_PPWRAP_EXT>;
+ mediatek,scp = <&scp>;
+ mediatek,vdecsys = <&vdecsys>;
+ power-domains = <&spm MT8183_POWER_DOMAIN_VDEC>;
+ clocks = <&vdecsys CLK_VDEC_VDEC>;
+ clock-names = "vdec";
+ };
+
larb1: larb@16010000 {
compatible = "mediatek,mt8183-smi-larb";
reg = <0 0x16010000 0 0x1000>;
--
2.41.0