This series adds support for the NAND Flash Controller on the AC5/AC5X SOC. It
needs to be applied on top of two other recent series [1] (applied to
mtd/fixes and mainline) [2] (applied to nand/next).
I've tried to stick to the minimal changes required to get the NFC working on
the board I have (AC5X + S34ML02G2). Marvell's SDK has hard coded tables of
ndtr values for the different timing modes but so far that seems unnecessary.
[1] - https://lore.kernel.org/linux-mtd/[email protected]/raw
[2] - https://lore.kernel.org/linux-mtd/[email protected]/raw
Chris Packham (3):
dt-bindings: mtd: Add AC5 specific binding
arm64: dts: marvell: Add NAND flash controller to AC5
mtd: rawnand: marvell: add support for AC5 SoC
.../bindings/mtd/marvell,nand-controller.yaml | 1 +
arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi | 10 ++++++++++
drivers/mtd/nand/raw/Kconfig | 2 +-
drivers/mtd/nand/raw/marvell_nand.c | 16 ++++++++++++++++
4 files changed, 28 insertions(+), 1 deletion(-)
--
2.41.0
Add binding for AC5 SoC. This SoC only supports NAND SDR timings up to
mode 3 so a specific compatible value is needed.
Signed-off-by: Chris Packham <[email protected]>
---
Notes:
Changes in v2:
- Keep compatibles in alphabetical order
- Explain AC5 limitations in commit message
.../devicetree/bindings/mtd/marvell,nand-controller.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/mtd/marvell,nand-controller.yaml b/Documentation/devicetree/bindings/mtd/marvell,nand-controller.yaml
index a10729bb1840..1ecea848e8b9 100644
--- a/Documentation/devicetree/bindings/mtd/marvell,nand-controller.yaml
+++ b/Documentation/devicetree/bindings/mtd/marvell,nand-controller.yaml
@@ -16,6 +16,7 @@ properties:
- const: marvell,armada-8k-nand-controller
- const: marvell,armada370-nand-controller
- enum:
+ - marvell,ac5-nand-controller
- marvell,armada370-nand-controller
- marvell,pxa3xx-nand-controller
- description: legacy bindings
--
2.41.0
On Mon, Jun 26, 2023 at 03:12:15PM +1200, Chris Packham wrote:
> Add binding for AC5 SoC. This SoC only supports NAND SDR timings up to
> mode 3 so a specific compatible value is needed.
>
> Signed-off-by: Chris Packham <[email protected]>
Acked-by: Conor Dooley <[email protected]>
Cheers,
Conor.
> ---
>
> Notes:
> Changes in v2:
> - Keep compatibles in alphabetical order
> - Explain AC5 limitations in commit message
>
> .../devicetree/bindings/mtd/marvell,nand-controller.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/mtd/marvell,nand-controller.yaml b/Documentation/devicetree/bindings/mtd/marvell,nand-controller.yaml
> index a10729bb1840..1ecea848e8b9 100644
> --- a/Documentation/devicetree/bindings/mtd/marvell,nand-controller.yaml
> +++ b/Documentation/devicetree/bindings/mtd/marvell,nand-controller.yaml
> @@ -16,6 +16,7 @@ properties:
> - const: marvell,armada-8k-nand-controller
> - const: marvell,armada370-nand-controller
> - enum:
> + - marvell,ac5-nand-controller
> - marvell,armada370-nand-controller
> - marvell,pxa3xx-nand-controller
> - description: legacy bindings
> --
> 2.41.0
>