This patch set corrects the lpuart compatible for imx8dxl and imx93 platforms,
also add the imx8ulp compatible string in fsl-lpuart dt-binding doc.
---
Changes in V2
1. drop the imx8ulp dts changes in last version patch set
2. add both "fsl,imx8ulp-lpuart" and "fsl,imx7ulp-lpuart" for imx93
3. correct the dt-bindings for imx93 lpuart compatible
---
Sherry Sun (3):
arm64: dts: imx8dxl: remove "fsl,imx7ulp-lpuart" compatible for
imx8dxl
arm64: dts: imx93: add "fsl,imx8ulp-lpuart" compatible for imx93
dt-bindings: serial: fsl-lpuart: add imx8ulp compatible string
.../devicetree/bindings/serial/fsl-lpuart.yaml | 9 ++++++---
.../boot/dts/freescale/imx8dxl-ss-adma.dtsi | 8 ++++----
arch/arm64/boot/dts/freescale/imx93.dtsi | 16 ++++++++--------
3 files changed, 18 insertions(+), 15 deletions(-)
--
2.17.1
i.MX93 and i.MX8ULP lpuart add some new featurs based on i.MX7ULP, for
example, i.MX93 and i.MX8ULP can support EOP(end-of-packet) function
while i.MX7ULP doesn't support, so add "fsl,imx8ulp-lpuart" compatible
string for i.MX93 to support those new features.
Signed-off-by: Sherry Sun <[email protected]>
---
arch/arm64/boot/dts/freescale/imx93.dtsi | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/imx93.dtsi b/arch/arm64/boot/dts/freescale/imx93.dtsi
index 8643612ace8c..16da5ef578c5 100644
--- a/arch/arm64/boot/dts/freescale/imx93.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx93.dtsi
@@ -252,7 +252,7 @@
};
lpuart1: serial@44380000 {
- compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart";
+ compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";
reg = <0x44380000 0x1000>;
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX93_CLK_LPUART1_GATE>;
@@ -261,7 +261,7 @@
};
lpuart2: serial@44390000 {
- compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart";
+ compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";
reg = <0x44390000 0x1000>;
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX93_CLK_LPUART2_GATE>;
@@ -486,7 +486,7 @@
};
lpuart3: serial@42570000 {
- compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart";
+ compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";
reg = <0x42570000 0x1000>;
interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX93_CLK_LPUART3_GATE>;
@@ -495,7 +495,7 @@
};
lpuart4: serial@42580000 {
- compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart";
+ compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";
reg = <0x42580000 0x1000>;
interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX93_CLK_LPUART4_GATE>;
@@ -504,7 +504,7 @@
};
lpuart5: serial@42590000 {
- compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart";
+ compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";
reg = <0x42590000 0x1000>;
interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX93_CLK_LPUART5_GATE>;
@@ -513,7 +513,7 @@
};
lpuart6: serial@425a0000 {
- compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart";
+ compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";
reg = <0x425a0000 0x1000>;
interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX93_CLK_LPUART6_GATE>;
@@ -551,7 +551,7 @@
};
lpuart7: serial@42690000 {
- compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart";
+ compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";
reg = <0x42690000 0x1000>;
interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX93_CLK_LPUART7_GATE>;
@@ -560,7 +560,7 @@
};
lpuart8: serial@426a0000 {
- compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart";
+ compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";
reg = <0x426a0000 0x1000>;
interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX93_CLK_LPUART8_GATE>;
--
2.17.1