2023-06-30 12:31:21

by Lad, Prabhakar

Subject: [RFC PATCH 4/4] riscv: dts: renesas: r9a07g043f: Update gpio-ranges property

From: Lad Prabhakar <[email protected]>

On RZ/Five we have additional pins compared to the RZ/G2UL SoC so update
the gpio-ranges property in RZ/Five SoC DTSI.

Signed-off-by: Lad Prabhakar <[email protected]>
---
arch/riscv/boot/dts/renesas/r9a07g043f.dtsi | 4 ++++
1 file changed, 4 insertions(+)

diff --git a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
index b0796015e36b..e68a91c9fe77 100644
--- a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
+++ b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
@@ -42,6 +42,10 @@ cpu0_intc: interrupt-controller {
};
};

+&pinctrl {
+ gpio-ranges = <&pinctrl 0 0 232>;
+};
+
&soc {
dma-noncoherent;
interrupt-parent = <&plic>;
--
2.34.1

2023-07-10 14:44:49

by Geert Uytterhoeven

Subject: Re: [RFC PATCH 4/4] riscv: dts: renesas: r9a07g043f: Update gpio-ranges property

Hi Prabhakar,

On Fri, Jun 30, 2023 at 2:05 PM Prabhakar <[email protected]> wrote:
> From: Lad Prabhakar <[email protected]>
>
> On RZ/Five we have additional pins compared to the RZ/G2UL SoC so update
> the gpio-ranges property in RZ/Five SoC DTSI.
>
> Signed-off-by: Lad Prabhakar <[email protected]>

Thanks for your patch!

> --- a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
> +++ b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
> @@ -42,6 +42,10 @@ cpu0_intc: interrupt-controller {
> };
> };
>
> +&pinctrl {
> + gpio-ranges = <&pinctrl 0 0 232>;

Is that correct? You only have 32 more pins than on r9a07g043u,
which uses:

gpio-ranges = <&pinctrl 0 0 152>;

> +};
> +
> &soc {
> dma-noncoherent;
> interrupt-parent = <&plic>;

Gr{oetje,eeting}s,

Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds