2023-07-06 05:06:07

by Achal Verma

Subject: [PATCH v2] PCI: j721e: Delay 100ms T_PVPERL from power stable to PERST# inactive

As per the PCIe Card Electromechanical specification REV. 5.0, PERST#
signal should be de-asserted after minimum 100ms from the time power-rails
become stable.
So, to ensure 100ms delay to give sufficient time for power-rails and
refclk to become stable, change delay from 100us to 100ms.

From PCIe Card Electromechanical specification REV. 5.0 section 2.9.2:
TPVPERL: Power stable to PERST# inactive - 100ms
T-PERST-CLK: REFCLK stable before PERST# inactive - 100 usec.

Fixes: f3e25911a430 ("PCI: j721e: Add TI J721E PCIe driver")
Signed-off-by: Achal Verma <[email protected]>
---
drivers/pci/controller/cadence/pci-j721e.c | 11 +++++------
drivers/pci/pci.h | 2 ++
2 files changed, 7 insertions(+), 6 deletions(-)

diff --git a/drivers/pci/controller/cadence/pci-j721e.c b/drivers/pci/controller/cadence/pci-j721e.c
index e70213c9060a..a3c8273b7320 100644
--- a/drivers/pci/controller/cadence/pci-j721e.c
+++ b/drivers/pci/controller/cadence/pci-j721e.c
@@ -498,14 +498,13 @@ static int j721e_pcie_probe(struct platform_device *pdev)

/*
* "Power Sequencing and Reset Signal Timings" table in
- * PCI EXPRESS CARD ELECTROMECHANICAL SPECIFICATION, REV. 3.0
- * indicates PERST# should be deasserted after minimum of 100us
- * once REFCLK is stable. The REFCLK to the connector in RC
- * mode is selected while enabling the PHY. So deassert PERST#
- * after 100 us.
+ * PCI EXPRESS CARD ELECTROMECHANICAL SPECIFICATION, REV. 5.0
+ * indicates PERST# should be deasserted after minimum of 100ms
+ * after power rails achieve specified operating limits and
+ * within this period reference clock should also become stable.
*/
if (gpiod) {
- usleep_range(100, 200);
+ msleep(PCI_TPVPERL_DELAY);
gpiod_set_value_cansleep(gpiod, 1);
}

diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h
index a4c397434057..7482cff16fef 100644
--- a/drivers/pci/pci.h
+++ b/drivers/pci/pci.h
@@ -13,6 +13,8 @@

#define PCIE_LINK_RETRAIN_TIMEOUT_MS 1000

+#define PCI_TPVPERL_DELAY 100 /* msec; see PCIe r5.0, sec 2.9.2 */
+
extern const unsigned char pcie_link_speed[];
extern bool pci_early_dump;

--
2.25.1

2023-07-06 18:17:04

by Bjorn Helgaas

Subject: Re: [PATCH v2] PCI: j721e: Delay 100ms T_PVPERL from power stable to PERST# inactive

On Thu, Jul 06, 2023 at 10:04:38AM +0530, Achal Verma wrote:
> As per the PCIe Card Electromechanical specification REV. 5.0, PERST#
> signal should be de-asserted after minimum 100ms from the time power-rails
> become stable.
> So, to ensure 100ms delay to give sufficient time for power-rails and
> refclk to become stable, change delay from 100us to 100ms.

Looks like the above is intended to be two paragraphs. Add a blank
line between, or rewrap into a single paragraph if you prefer that.

> From PCIe Card Electromechanical specification REV. 5.0 section 2.9.2:
> TPVPERL: Power stable to PERST# inactive - 100ms
> T-PERST-CLK: REFCLK stable before PERST# inactive - 100 usec.

Is T-PERST-CLK relevant here? Omit if not.

> Fixes: f3e25911a430 ("PCI: j721e: Add TI J721E PCIe driver")
> Signed-off-by: Achal Verma <[email protected]>
> ---
> drivers/pci/controller/cadence/pci-j721e.c | 11 +++++------
> drivers/pci/pci.h | 2 ++
> 2 files changed, 7 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/pci/controller/cadence/pci-j721e.c b/drivers/pci/controller/cadence/pci-j721e.c
> index e70213c9060a..a3c8273b7320 100644
> --- a/drivers/pci/controller/cadence/pci-j721e.c
> +++ b/drivers/pci/controller/cadence/pci-j721e.c
> @@ -498,14 +498,13 @@ static int j721e_pcie_probe(struct platform_device *pdev)
>
> /*
> * "Power Sequencing and Reset Signal Timings" table in
> - * PCI EXPRESS CARD ELECTROMECHANICAL SPECIFICATION, REV. 3.0
> - * indicates PERST# should be deasserted after minimum of 100us
> - * once REFCLK is stable. The REFCLK to the connector in RC
> - * mode is selected while enabling the PHY. So deassert PERST#
> - * after 100 us.
> + * PCI EXPRESS CARD ELECTROMECHANICAL SPECIFICATION, REV. 5.0
> + * indicates PERST# should be deasserted after minimum of 100ms
> + * after power rails achieve specified operating limits and
> + * within this period reference clock should also become stable.
> */
> if (gpiod) {
> - usleep_range(100, 200);
> + msleep(PCI_TPVPERL_DELAY);
> gpiod_set_value_cansleep(gpiod, 1);
> }
>
> diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h
> index a4c397434057..7482cff16fef 100644
> --- a/drivers/pci/pci.h
> +++ b/drivers/pci/pci.h
> @@ -13,6 +13,8 @@
>
> #define PCIE_LINK_RETRAIN_TIMEOUT_MS 1000
>
> +#define PCI_TPVPERL_DELAY 100 /* msec; see PCIe r5.0, sec 2.9.2 */

Perhaps make the name "PCIE_..." since this is a PCIe-specific time.

Also add "_MS" to the name so it's easy to verify that users are using
the correct mechanism (usleep/msleep/etc).

Otherwise looks good to me, thanks!

> extern const unsigned char pcie_link_speed[];
> extern bool pci_early_dump;
>
> --
> 2.25.1
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> [email protected]
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel