Add bindings, driver and devicetree node for camera clock controller on
SM8550.
Changes in v6:
- Updated parent map and frequency table of cam_cc_xo_clk_src to use
active only source P_BI_TCXO_AO instead of P_BI_TCXO
Changes in v5:
- Added clk_lucid_ole_pll_configure() to configure lucid ole PLL's
- Used module_platform_driver() instead of subsys_initcall()
- Fixed overloading .l config with CAL_L and RINGOSC_CAL_L fields
Changes in v4:
- Dropped the extra patches added in v2, since the review comments on
v3 recommended an alternate solution
Changes in v3:
- Squashed 2 extra patches added in v2 into single patch as per review
comments
Changes in v2:
- Took care of review comments from v1
+ Removed new YAML file and reused SM8450 CAMCC YAML file for SM8550
+ Sorted the PLL names in proper order
+ Updated all PLL configurations to lower case hex
+ Reused evo ops instead of adding new ops for ole pll
+ Moved few clocks to separate patch to fix patch too long error
+ Padded non-zero address part to 8 hex digits in DT change
- Added 2 extra patches updating .l config value across chipsets to
include CAL_L and RINGOSC_CAL_L fields and removed setting CAL_L
field explicitly in clk_lucid_evo_pll_configure().
v1:
- Initial CAMCC changes for SM8550
Previous series:
v5 - https://patchwork.kernel.org/project/linux-clk/list/?series=759863
v4 - https://patchwork.kernel.org/project/linux-clk/list/?series=755683
v3 - https://patchwork.kernel.org/project/linux-clk/list/?series=753150
v2 - https://patchwork.kernel.org/project/linux-clk/list/?series=751058
v1 - https://patchwork.kernel.org/project/linux-clk/list/?series=749294
Jagadeesh Kona (5):
dt-bindings: clock: qcom: Add SM8550 camera clock controller
clk: qcom: clk-alpha-pll: Add support for lucid ole pll configure
clk: qcom: camcc-sm8550: Add camera clock controller driver for SM8550
clk: qcom: camcc-sm8550: Add support for qdss, sleep and xo clocks
arm64: dts: qcom: sm8550: Add camera clock controller
.../bindings/clock/qcom,sm8450-camcc.yaml | 8 +-
arch/arm64/boot/dts/qcom/sm8550.dtsi | 15 +
drivers/clk/qcom/Kconfig | 7 +
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/camcc-sm8550.c | 3564 +++++++++++++++++
drivers/clk/qcom/clk-alpha-pll.c | 29 +
drivers/clk/qcom/clk-alpha-pll.h | 2 +
include/dt-bindings/clock/qcom,sm8550-camcc.h | 187 +
8 files changed, 3811 insertions(+), 2 deletions(-)
create mode 100644 drivers/clk/qcom/camcc-sm8550.c
create mode 100644 include/dt-bindings/clock/qcom,sm8550-camcc.h
--
2.40.1
Add device tree bindings for the camera clock controller on
Qualcomm SM8550 platform.
Co-developed-by: Taniya Das <[email protected]>
Signed-off-by: Taniya Das <[email protected]>
Signed-off-by: Jagadeesh Kona <[email protected]>
Reviewed-by: Krzysztof Kozlowski <[email protected]>
---
Changes since v5:
- No changes
Changes since v4:
- No changes
Changes since v3:
- No changes
Changes since v2:
- No changes
Changes since v1:
- Removed new YAML file and reused SM8450 CAMCC YAML file for SM8550
.../bindings/clock/qcom,sm8450-camcc.yaml | 8 +-
include/dt-bindings/clock/qcom,sm8550-camcc.h | 187 ++++++++++++++++++
2 files changed, 193 insertions(+), 2 deletions(-)
create mode 100644 include/dt-bindings/clock/qcom,sm8550-camcc.h
diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml
index 87ae74166807..8dbc9004202f 100644
--- a/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml
@@ -13,11 +13,15 @@ description: |
Qualcomm camera clock control module provides the clocks, resets and power
domains on SM8450.
- See also:: include/dt-bindings/clock/qcom,sm8450-camcc.h
+ See also::
+ include/dt-bindings/clock/qcom,sm8450-camcc.h
+ include/dt-bindings/clock/qcom,sm8550-camcc.h
properties:
compatible:
- const: qcom,sm8450-camcc
+ enum:
+ - qcom,sm8450-camcc
+ - qcom,sm8550-camcc
clocks:
items:
diff --git a/include/dt-bindings/clock/qcom,sm8550-camcc.h b/include/dt-bindings/clock/qcom,sm8550-camcc.h
new file mode 100644
index 000000000000..a2a256691c2b
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,sm8550-camcc.h
@@ -0,0 +1,187 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_CAM_CC_SM8550_H
+#define _DT_BINDINGS_CLK_QCOM_CAM_CC_SM8550_H
+
+/* CAM_CC clocks */
+#define CAM_CC_BPS_AHB_CLK 0
+#define CAM_CC_BPS_CLK 1
+#define CAM_CC_BPS_CLK_SRC 2
+#define CAM_CC_BPS_FAST_AHB_CLK 3
+#define CAM_CC_CAMNOC_AXI_CLK 4
+#define CAM_CC_CAMNOC_AXI_CLK_SRC 5
+#define CAM_CC_CAMNOC_DCD_XO_CLK 6
+#define CAM_CC_CAMNOC_XO_CLK 7
+#define CAM_CC_CCI_0_CLK 8
+#define CAM_CC_CCI_0_CLK_SRC 9
+#define CAM_CC_CCI_1_CLK 10
+#define CAM_CC_CCI_1_CLK_SRC 11
+#define CAM_CC_CCI_2_CLK 12
+#define CAM_CC_CCI_2_CLK_SRC 13
+#define CAM_CC_CORE_AHB_CLK 14
+#define CAM_CC_CPAS_AHB_CLK 15
+#define CAM_CC_CPAS_BPS_CLK 16
+#define CAM_CC_CPAS_CRE_CLK 17
+#define CAM_CC_CPAS_FAST_AHB_CLK 18
+#define CAM_CC_CPAS_IFE_0_CLK 19
+#define CAM_CC_CPAS_IFE_1_CLK 20
+#define CAM_CC_CPAS_IFE_2_CLK 21
+#define CAM_CC_CPAS_IFE_LITE_CLK 22
+#define CAM_CC_CPAS_IPE_NPS_CLK 23
+#define CAM_CC_CPAS_SBI_CLK 24
+#define CAM_CC_CPAS_SFE_0_CLK 25
+#define CAM_CC_CPAS_SFE_1_CLK 26
+#define CAM_CC_CPHY_RX_CLK_SRC 27
+#define CAM_CC_CRE_AHB_CLK 28
+#define CAM_CC_CRE_CLK 29
+#define CAM_CC_CRE_CLK_SRC 30
+#define CAM_CC_CSI0PHYTIMER_CLK 31
+#define CAM_CC_CSI0PHYTIMER_CLK_SRC 32
+#define CAM_CC_CSI1PHYTIMER_CLK 33
+#define CAM_CC_CSI1PHYTIMER_CLK_SRC 34
+#define CAM_CC_CSI2PHYTIMER_CLK 35
+#define CAM_CC_CSI2PHYTIMER_CLK_SRC 36
+#define CAM_CC_CSI3PHYTIMER_CLK 37
+#define CAM_CC_CSI3PHYTIMER_CLK_SRC 38
+#define CAM_CC_CSI4PHYTIMER_CLK 39
+#define CAM_CC_CSI4PHYTIMER_CLK_SRC 40
+#define CAM_CC_CSI5PHYTIMER_CLK 41
+#define CAM_CC_CSI5PHYTIMER_CLK_SRC 42
+#define CAM_CC_CSI6PHYTIMER_CLK 43
+#define CAM_CC_CSI6PHYTIMER_CLK_SRC 44
+#define CAM_CC_CSI7PHYTIMER_CLK 45
+#define CAM_CC_CSI7PHYTIMER_CLK_SRC 46
+#define CAM_CC_CSID_CLK 47
+#define CAM_CC_CSID_CLK_SRC 48
+#define CAM_CC_CSID_CSIPHY_RX_CLK 49
+#define CAM_CC_CSIPHY0_CLK 50
+#define CAM_CC_CSIPHY1_CLK 51
+#define CAM_CC_CSIPHY2_CLK 52
+#define CAM_CC_CSIPHY3_CLK 53
+#define CAM_CC_CSIPHY4_CLK 54
+#define CAM_CC_CSIPHY5_CLK 55
+#define CAM_CC_CSIPHY6_CLK 56
+#define CAM_CC_CSIPHY7_CLK 57
+#define CAM_CC_DRV_AHB_CLK 58
+#define CAM_CC_DRV_XO_CLK 59
+#define CAM_CC_FAST_AHB_CLK_SRC 60
+#define CAM_CC_GDSC_CLK 61
+#define CAM_CC_ICP_AHB_CLK 62
+#define CAM_CC_ICP_CLK 63
+#define CAM_CC_ICP_CLK_SRC 64
+#define CAM_CC_IFE_0_CLK 65
+#define CAM_CC_IFE_0_CLK_SRC 66
+#define CAM_CC_IFE_0_DSP_CLK 67
+#define CAM_CC_IFE_0_DSP_CLK_SRC 68
+#define CAM_CC_IFE_0_FAST_AHB_CLK 69
+#define CAM_CC_IFE_1_CLK 70
+#define CAM_CC_IFE_1_CLK_SRC 71
+#define CAM_CC_IFE_1_DSP_CLK 72
+#define CAM_CC_IFE_1_DSP_CLK_SRC 73
+#define CAM_CC_IFE_1_FAST_AHB_CLK 74
+#define CAM_CC_IFE_2_CLK 75
+#define CAM_CC_IFE_2_CLK_SRC 76
+#define CAM_CC_IFE_2_DSP_CLK 77
+#define CAM_CC_IFE_2_DSP_CLK_SRC 78
+#define CAM_CC_IFE_2_FAST_AHB_CLK 79
+#define CAM_CC_IFE_LITE_AHB_CLK 80
+#define CAM_CC_IFE_LITE_CLK 81
+#define CAM_CC_IFE_LITE_CLK_SRC 82
+#define CAM_CC_IFE_LITE_CPHY_RX_CLK 83
+#define CAM_CC_IFE_LITE_CSID_CLK 84
+#define CAM_CC_IFE_LITE_CSID_CLK_SRC 85
+#define CAM_CC_IPE_NPS_AHB_CLK 86
+#define CAM_CC_IPE_NPS_CLK 87
+#define CAM_CC_IPE_NPS_CLK_SRC 88
+#define CAM_CC_IPE_NPS_FAST_AHB_CLK 89
+#define CAM_CC_IPE_PPS_CLK 90
+#define CAM_CC_IPE_PPS_FAST_AHB_CLK 91
+#define CAM_CC_JPEG_1_CLK 92
+#define CAM_CC_JPEG_CLK 93
+#define CAM_CC_JPEG_CLK_SRC 94
+#define CAM_CC_MCLK0_CLK 95
+#define CAM_CC_MCLK0_CLK_SRC 96
+#define CAM_CC_MCLK1_CLK 97
+#define CAM_CC_MCLK1_CLK_SRC 98
+#define CAM_CC_MCLK2_CLK 99
+#define CAM_CC_MCLK2_CLK_SRC 100
+#define CAM_CC_MCLK3_CLK 101
+#define CAM_CC_MCLK3_CLK_SRC 102
+#define CAM_CC_MCLK4_CLK 103
+#define CAM_CC_MCLK4_CLK_SRC 104
+#define CAM_CC_MCLK5_CLK 105
+#define CAM_CC_MCLK5_CLK_SRC 106
+#define CAM_CC_MCLK6_CLK 107
+#define CAM_CC_MCLK6_CLK_SRC 108
+#define CAM_CC_MCLK7_CLK 109
+#define CAM_CC_MCLK7_CLK_SRC 110
+#define CAM_CC_PLL0 111
+#define CAM_CC_PLL0_OUT_EVEN 112
+#define CAM_CC_PLL0_OUT_ODD 113
+#define CAM_CC_PLL1 114
+#define CAM_CC_PLL1_OUT_EVEN 115
+#define CAM_CC_PLL2 116
+#define CAM_CC_PLL3 117
+#define CAM_CC_PLL3_OUT_EVEN 118
+#define CAM_CC_PLL4 119
+#define CAM_CC_PLL4_OUT_EVEN 120
+#define CAM_CC_PLL5 121
+#define CAM_CC_PLL5_OUT_EVEN 122
+#define CAM_CC_PLL6 123
+#define CAM_CC_PLL6_OUT_EVEN 124
+#define CAM_CC_PLL7 125
+#define CAM_CC_PLL7_OUT_EVEN 126
+#define CAM_CC_PLL8 127
+#define CAM_CC_PLL8_OUT_EVEN 128
+#define CAM_CC_PLL9 129
+#define CAM_CC_PLL9_OUT_EVEN 130
+#define CAM_CC_PLL10 131
+#define CAM_CC_PLL10_OUT_EVEN 132
+#define CAM_CC_PLL11 133
+#define CAM_CC_PLL11_OUT_EVEN 134
+#define CAM_CC_PLL12 135
+#define CAM_CC_PLL12_OUT_EVEN 136
+#define CAM_CC_QDSS_DEBUG_CLK 137
+#define CAM_CC_QDSS_DEBUG_CLK_SRC 138
+#define CAM_CC_QDSS_DEBUG_XO_CLK 139
+#define CAM_CC_SBI_CLK 140
+#define CAM_CC_SBI_FAST_AHB_CLK 141
+#define CAM_CC_SFE_0_CLK 142
+#define CAM_CC_SFE_0_CLK_SRC 143
+#define CAM_CC_SFE_0_FAST_AHB_CLK 144
+#define CAM_CC_SFE_1_CLK 145
+#define CAM_CC_SFE_1_CLK_SRC 146
+#define CAM_CC_SFE_1_FAST_AHB_CLK 147
+#define CAM_CC_SLEEP_CLK 148
+#define CAM_CC_SLEEP_CLK_SRC 149
+#define CAM_CC_SLOW_AHB_CLK_SRC 150
+#define CAM_CC_XO_CLK_SRC 151
+
+/* CAM_CC power domains */
+#define CAM_CC_BPS_GDSC 0
+#define CAM_CC_IFE_0_GDSC 1
+#define CAM_CC_IFE_1_GDSC 2
+#define CAM_CC_IFE_2_GDSC 3
+#define CAM_CC_IPE_0_GDSC 4
+#define CAM_CC_SBI_GDSC 5
+#define CAM_CC_SFE_0_GDSC 6
+#define CAM_CC_SFE_1_GDSC 7
+#define CAM_CC_TITAN_TOP_GDSC 8
+
+/* CAM_CC resets */
+#define CAM_CC_BPS_BCR 0
+#define CAM_CC_DRV_BCR 1
+#define CAM_CC_ICP_BCR 2
+#define CAM_CC_IFE_0_BCR 3
+#define CAM_CC_IFE_1_BCR 4
+#define CAM_CC_IFE_2_BCR 5
+#define CAM_CC_IPE_0_BCR 6
+#define CAM_CC_QDSS_DEBUG_BCR 7
+#define CAM_CC_SBI_BCR 8
+#define CAM_CC_SFE_0_BCR 9
+#define CAM_CC_SFE_1_BCR 10
+
+#endif
--
2.40.1
Add device node for camera clock controller on Qualcomm
SM8550 platform.
Signed-off-by: Jagadeesh Kona <[email protected]>
Reviewed-by: Dmitry Baryshkov <[email protected]>
---
Changes since v5:
- No changes
Changes since v4:
- No changes
Changes since v3:
- No changes
Changes since v2:
- No changes
Changes since v1:
- Padded non-zero address part to 8 hex digits
arch/arm64/boot/dts/qcom/sm8550.dtsi | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
index 41d60af93692..2df05c48f215 100644
--- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
@@ -5,6 +5,7 @@
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/clock/qcom,sm8450-videocc.h>
+#include <dt-bindings/clock/qcom,sm8550-camcc.h>
#include <dt-bindings/clock/qcom,sm8550-gcc.h>
#include <dt-bindings/clock/qcom,sm8550-gpucc.h>
#include <dt-bindings/clock/qcom,sm8550-tcsr.h>
@@ -2419,6 +2420,20 @@ videocc: clock-controller@aaf0000 {
#power-domain-cells = <1>;
};
+ camcc: clock-controller@ade0000 {
+ compatible = "qcom,sm8550-camcc";
+ reg = <0 0x0ade0000 0 0x20000>;
+ clocks = <&gcc GCC_CAMERA_AHB_CLK>,
+ <&bi_tcxo_div2>,
+ <&bi_tcxo_ao_div2>,
+ <&sleep_clk>;
+ power-domains = <&rpmhpd SM8550_MMCX>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
mdss: display-subsystem@ae00000 {
compatible = "qcom,sm8550-mdss";
reg = <0 0x0ae00000 0 0x1000>;
--
2.40.1
On 7/7/2023 9:27 AM, Jagadeesh Kona wrote:
> Add bindings, driver and devicetree node for camera clock controller on
> SM8550.
>
> Changes in v6:
> - Updated parent map and frequency table of cam_cc_xo_clk_src to use
> active only source P_BI_TCXO_AO instead of P_BI_TCXO
>
> Changes in v5:
> - Added clk_lucid_ole_pll_configure() to configure lucid ole PLL's
> - Used module_platform_driver() instead of subsys_initcall()
> - Fixed overloading .l config with CAL_L and RINGOSC_CAL_L fields
>
> Changes in v4:
> - Dropped the extra patches added in v2, since the review comments on
> v3 recommended an alternate solution
>
> Changes in v3:
> - Squashed 2 extra patches added in v2 into single patch as per review
> comments
>
> Changes in v2:
> - Took care of review comments from v1
> + Removed new YAML file and reused SM8450 CAMCC YAML file for SM8550
> + Sorted the PLL names in proper order
> + Updated all PLL configurations to lower case hex
> + Reused evo ops instead of adding new ops for ole pll
> + Moved few clocks to separate patch to fix patch too long error
> + Padded non-zero address part to 8 hex digits in DT change
> - Added 2 extra patches updating .l config value across chipsets to
> include CAL_L and RINGOSC_CAL_L fields and removed setting CAL_L
> field explicitly in clk_lucid_evo_pll_configure().
>
> v1:
> - Initial CAMCC changes for SM8550
>
> Previous series:
> v5 - https://patchwork.kernel.org/project/linux-clk/list/?series=759863
> v4 - https://patchwork.kernel.org/project/linux-clk/list/?series=755683
> v3 - https://patchwork.kernel.org/project/linux-clk/list/?series=753150
> v2 - https://patchwork.kernel.org/project/linux-clk/list/?series=751058
> v1 - https://patchwork.kernel.org/project/linux-clk/list/?series=749294
>
> Jagadeesh Kona (5):
> dt-bindings: clock: qcom: Add SM8550 camera clock controller
> clk: qcom: clk-alpha-pll: Add support for lucid ole pll configure
> clk: qcom: camcc-sm8550: Add camera clock controller driver for SM8550
> clk: qcom: camcc-sm8550: Add support for qdss, sleep and xo clocks
> arm64: dts: qcom: sm8550: Add camera clock controller
>
> .../bindings/clock/qcom,sm8450-camcc.yaml | 8 +-
> arch/arm64/boot/dts/qcom/sm8550.dtsi | 15 +
> drivers/clk/qcom/Kconfig | 7 +
> drivers/clk/qcom/Makefile | 1 +
> drivers/clk/qcom/camcc-sm8550.c | 3564 +++++++++++++++++
> drivers/clk/qcom/clk-alpha-pll.c | 29 +
> drivers/clk/qcom/clk-alpha-pll.h | 2 +
> include/dt-bindings/clock/qcom,sm8550-camcc.h | 187 +
> 8 files changed, 3811 insertions(+), 2 deletions(-)
> create mode 100644 drivers/clk/qcom/camcc-sm8550.c
> create mode 100644 include/dt-bindings/clock/qcom,sm8550-camcc.h
>
Hi Bjorn,
All patches in this series are in reviewed state, could you please help
to pick this series in the next release? Thanks!
Thanks,
Jagadeesh
On Fri, 07 Jul 2023 09:27:39 +0530, Jagadeesh Kona wrote:
> Add bindings, driver and devicetree node for camera clock controller on
> SM8550.
>
> Changes in v6:
> - Updated parent map and frequency table of cam_cc_xo_clk_src to use
> active only source P_BI_TCXO_AO instead of P_BI_TCXO
>
> [...]
Applied, thanks!
[5/5] arm64: dts: qcom: sm8550: Add camera clock controller
commit: e271b59e39a6fbdc57784fdda7e68076f8e58ef7
Best regards,
--
Bjorn Andersson <[email protected]>