This patch series adds the relevant phy and controller
configurations for enabling USB2 on IPQ5332
v3:
Fix bindings file based on review comments
v1:
Cleanup DTS
Combine driver, kconfig and makefile patches
Remove unused functions from M31 driver
Drop the clock driver changes
Varadarajan Narayanan (6):
dt-bindings: usb: dwc3: Add IPQ5332 compatible
dt-bindings: phy: qcom,m31: Document qcom,m31 USB phy
phy: qcom-m31: Introduce qcom,m31 USB phy driver
arm64: dts: qcom: ipq5332: Add USB related nodes
arm64: dts: qcom: ipq5332: Enable USB
arm64: defconfig: Enable M31 USB phy driver
.../bindings/phy/qcom,ipq5332-usb-hsphy.yaml | 49 ++++
.../devicetree/bindings/usb/qcom,dwc3.yaml | 3 +
arch/arm64/boot/dts/qcom/ipq5332-rdp468.dts | 12 +
arch/arm64/boot/dts/qcom/ipq5332.dtsi | 54 +++++
arch/arm64/configs/defconfig | 1 +
drivers/phy/qualcomm/Kconfig | 11 +
drivers/phy/qualcomm/Makefile | 1 +
drivers/phy/qualcomm/phy-qcom-m31.c | 256 +++++++++++++++++++++
8 files changed, 387 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/qcom,ipq5332-usb-hsphy.yaml
create mode 100644 drivers/phy/qualcomm/phy-qcom-m31.c
--
2.7.4
Enable M31 USB phy driver present in IPQ5332.
Signed-off-by: Varadarajan Narayanan <[email protected]>
---
v2:
Add full stop to commit log.
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 347307e..cb9d728 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -1386,6 +1386,7 @@ CONFIG_PHY_QCOM_USB_HS=m
CONFIG_PHY_QCOM_USB_SNPS_FEMTO_V2=m
CONFIG_PHY_QCOM_USB_HS_28NM=m
CONFIG_PHY_QCOM_USB_SS=m
+CONFIG_PHY_QCOM_M31_USB=m
CONFIG_PHY_R8A779F0_ETHERNET_SERDES=y
CONFIG_PHY_RCAR_GEN3_PCIE=y
CONFIG_PHY_RCAR_GEN3_USB2=y
--
2.7.4
Document the IPQ5332 dwc3 compatible.
Signed-off-by: Varadarajan Narayanan <[email protected]>
---
v1:
Add ipq5332 to interrupts sections
---
Documentation/devicetree/bindings/usb/qcom,dwc3.yaml | 3 +++
1 file changed, 3 insertions(+)
diff --git a/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml b/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml
index ae24dac..9447b54 100644
--- a/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml
+++ b/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml
@@ -14,6 +14,7 @@ properties:
items:
- enum:
- qcom,ipq4019-dwc3
+ - qcom,ipq5332-dwc3
- qcom,ipq6018-dwc3
- qcom,ipq8064-dwc3
- qcom,ipq8074-dwc3
@@ -246,6 +247,7 @@ allOf:
compatible:
contains:
enum:
+ - qcom,ipq5332-dwc3
- qcom,msm8994-dwc3
- qcom,qcs404-dwc3
then:
@@ -410,6 +412,7 @@ allOf:
compatible:
contains:
enum:
+ - qcom,ipq5332-dwc3
- qcom,sdm660-dwc3
then:
properties:
--
2.7.4
Document the M31 USB2 phy present in IPQ5332.
Signed-off-by: Sricharan Ramabadhran <[email protected]>
Signed-off-by: Varadarajan Narayanan <[email protected]>
---
v3:
Incorporate review comments. Will bring in ipq5018 compatible
string while posting ipq5018 usb patchset.
v1:
Rename qcom,m31.yaml -> qcom,ipq5332-usb-hsphy.yaml
Drop default binding "m31,usb-hsphy"
Add clock
Remove 'oneOf' from compatible
Remove 'qscratch' region from register space as it is not needed
Remove reset-names
Fix the example definition
---
.../bindings/phy/qcom,ipq5332-usb-hsphy.yaml | 49 ++++++++++++++++++++++
1 file changed, 49 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/qcom,ipq5332-usb-hsphy.yaml
diff --git a/Documentation/devicetree/bindings/phy/qcom,ipq5332-usb-hsphy.yaml b/Documentation/devicetree/bindings/phy/qcom,ipq5332-usb-hsphy.yaml
new file mode 100644
index 0000000..2cfdd73
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/qcom,ipq5332-usb-hsphy.yaml
@@ -0,0 +1,49 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/qcom,ipq5332-usb-hsphy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: M31 (https://www.m31tech.com) USB PHY
+
+maintainers:
+ - Sricharan Ramabadhran <[email protected]>
+ - Varadarajan Narayanan <[email protected]>
+
+description:
+ USB M31 PHY found in Qualcomm IPQ5018, IPQ5332 SoCs.
+
+properties:
+ compatible:
+ enum:
+ - qcom,ipq5332-usb-hsphy
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ maxItems: 1
+ contains:
+ items:
+ - const: cfg_ahb
+
+ resets:
+ maxItems: 1
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,ipq5332-gcc.h>
+ usbphy0: ipq5332-hsphy@7b000 {
+ compatible = "qcom,ipq5332-usb-hsphy";
+ reg = <0x0007b000 0x12c>;
+
+ clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>;
+ clock-names = "cfg_ahb";
+
+ resets = <&gcc GCC_QUSB2_0_PHY_BCR>;
+ };
--
2.7.4
Add USB phy and controller nodes.
Signed-off-by: Varadarajan Narayanan <[email protected]>
---
v1:
Rename phy node
Change compatible from m31,ipq5332-usb-hsphy -> qcom,ipq5332-usb-hsphy
Remove 'qscratch' from phy node
Fix alignment and upper-case hex no.s
Add clock definition for the phy
Remove snps,ref-clock-period-ns as it is not used. dwc3_ref_clk_period()
in dwc3/core.c takes the frequency from ref clock and calculates fladj
as appropriate.
---
arch/arm64/boot/dts/qcom/ipq5332.dtsi | 54 +++++++++++++++++++++++++++++++++++
1 file changed, 54 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/ipq5332.dtsi b/arch/arm64/boot/dts/qcom/ipq5332.dtsi
index 8bfc2db..c945ff6 100644
--- a/arch/arm64/boot/dts/qcom/ipq5332.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi
@@ -405,6 +405,60 @@
status = "disabled";
};
};
+
+ usbphy0: ipq5332-hsphy@7b000 {
+ compatible = "qcom,ipq5332-usb-hsphy";
+ reg = <0x0007b000 0x12c>;
+
+ clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>;
+ clock-names = "cfg_ahb";
+
+ resets = <&gcc GCC_QUSB2_0_PHY_BCR>;
+
+ status = "disabled";
+ };
+
+ usb2: usb2@8a00000 {
+ compatible = "qcom,ipq5332-dwc3", "qcom,dwc3";
+
+ reg = <0x08af8800 0x400>;
+
+ interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hs_phy_irq";
+
+ clocks = <&gcc GCC_USB0_MASTER_CLK>,
+ <&gcc GCC_SNOC_USB_CLK>,
+ <&gcc GCC_USB0_SLEEP_CLK>,
+ <&gcc GCC_USB0_MOCK_UTMI_CLK>;
+ clock-names = "core",
+ "iface",
+ "sleep",
+ "mock_utmi";
+
+ resets = <&gcc GCC_USB_BCR>;
+
+ qcom,select-utmi-as-pipe-clk;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ status = "disabled";
+
+ usb2_0_dwc: usb@8a00000 {
+ compatible = "snps,dwc3";
+ reg = <0x08a00000 0xe000>;
+ clocks = <&gcc GCC_USB0_MOCK_UTMI_CLK>;
+ clock-names = "ref";
+ interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
+ usb-phy = <&usbphy0>;
+ tx-fifo-resize;
+ snps,is-utmi-l1-suspend;
+ snps,hird-threshold = /bits/ 8 <0x0>;
+ snps,dis_u2_susphy_quirk;
+ snps,dis_u3_susphy_quirk;
+ };
+ };
};
timer {
--
2.7.4
On 11/07/2023 10:51, Varadarajan Narayanan wrote:
> Add USB phy and controller nodes.
>
> Signed-off-by: Varadarajan Narayanan <[email protected]>
> ---
> v1:
> Rename phy node
I don't see any improvements.
> Change compatible from m31,ipq5332-usb-hsphy -> qcom,ipq5332-usb-hsphy
> Remove 'qscratch' from phy node
> Fix alignment and upper-case hex no.s
> Add clock definition for the phy
> Remove snps,ref-clock-period-ns as it is not used. dwc3_ref_clk_period()
> in dwc3/core.c takes the frequency from ref clock and calculates fladj
> as appropriate.
> ---
> arch/arm64/boot/dts/qcom/ipq5332.dtsi | 54 +++++++++++++++++++++++++++++++++++
> 1 file changed, 54 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/ipq5332.dtsi b/arch/arm64/boot/dts/qcom/ipq5332.dtsi
> index 8bfc2db..c945ff6 100644
> --- a/arch/arm64/boot/dts/qcom/ipq5332.dtsi
> +++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi
> @@ -405,6 +405,60 @@
> status = "disabled";
> };
> };
> +
> + usbphy0: ipq5332-hsphy@7b000 {
Node names should be generic. See also an explanation and list of
examples (not exhaustive) in DT specification:
https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetree-basics.html#generic-names-recommendation
"phy"
> + compatible = "qcom,ipq5332-usb-hsphy";
> + reg = <0x0007b000 0x12c>;
> +
> + clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>;
> + clock-names = "cfg_ahb";
> +
> + resets = <&gcc GCC_QUSB2_0_PHY_BCR>;
> +
> + status = "disabled";
> + };
> +
> + usb2: usb2@8a00000 {
It does not look like you tested the DTS against bindings. Please run
`make dtbs_check` (see
Documentation/devicetree/bindings/writing-schema.rst or
https://www.linaro.org/blog/tips-and-tricks-for-validating-devicetree-sources-with-the-devicetree-schema/
for instructions).
> + compatible = "qcom,ipq5332-dwc3", "qcom,dwc3";
> +
No need for blank line.
> + reg = <0x08af8800 0x400>;
> +
> + interrupts = <GIC_SPI 62 IRQ_
Best regards,
Krzysztof
Add the M31 USB2 phy driver.
Signed-off-by: Varadarajan Narayanan <[email protected]>
---
v1:
Combine driver, makefile and kconfig into 1 patch
Remove 'qscratch' region and its usage. The controller driver takes care
of those settings
Use compatible/data to handle ipq5332 init
Drop the default case
Get resources by index instead of name as there is only one resource
Add clock
Fix review comments in the driver
---
drivers/phy/qualcomm/Kconfig | 11 ++
drivers/phy/qualcomm/Makefile | 1 +
drivers/phy/qualcomm/phy-qcom-m31.c | 256 ++++++++++++++++++++++++++++++++++++
3 files changed, 268 insertions(+)
create mode 100644 drivers/phy/qualcomm/phy-qcom-m31.c
diff --git a/drivers/phy/qualcomm/Kconfig b/drivers/phy/qualcomm/Kconfig
index 97ca595..76be191 100644
--- a/drivers/phy/qualcomm/Kconfig
+++ b/drivers/phy/qualcomm/Kconfig
@@ -197,3 +197,14 @@ config PHY_QCOM_SGMII_ETH
help
Enable this to support the internal SerDes/SGMII PHY on various
Qualcomm chipsets.
+
+config PHY_QCOM_M31_USB
+ tristate "Qualcomm M31 HS PHY driver support"
+ depends on (USB || USB_GADGET) && ARCH_QCOM
+ select USB_PHY
+ help
+ Enable this to support M31 HS PHY transceivers on Qualcomm chips
+ with DWC3 USB core. It handles PHY initialization, clock
+ management required after resetting the hardware and power
+ management. This driver is required even for peripheral only or
+ host only mode configurations.
diff --git a/drivers/phy/qualcomm/Makefile b/drivers/phy/qualcomm/Makefile
index b030858..0b5dd66 100644
--- a/drivers/phy/qualcomm/Makefile
+++ b/drivers/phy/qualcomm/Makefile
@@ -22,3 +22,4 @@ obj-$(CONFIG_PHY_QCOM_USB_SS) += phy-qcom-usb-ss.o
obj-$(CONFIG_PHY_QCOM_USB_SNPS_FEMTO_V2)+= phy-qcom-snps-femto-v2.o
obj-$(CONFIG_PHY_QCOM_IPQ806X_USB) += phy-qcom-ipq806x-usb.o
obj-$(CONFIG_PHY_QCOM_SGMII_ETH) += phy-qcom-sgmii-eth.o
+obj-$(CONFIG_PHY_QCOM_M31_USB) += phy-qcom-m31.o
diff --git a/drivers/phy/qualcomm/phy-qcom-m31.c b/drivers/phy/qualcomm/phy-qcom-m31.c
new file mode 100644
index 0000000..8700728
--- /dev/null
+++ b/drivers/phy/qualcomm/phy-qcom-m31.c
@@ -0,0 +1,256 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2014-2016, 2020, The Linux Foundation. All rights reserved.
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/reset.h>
+#include <linux/slab.h>
+#include <linux/usb/of.h>
+#include <linux/usb/phy.h>
+
+enum clk_reset_action {
+ CLK_RESET_DEASSERT = 0,
+ CLK_RESET_ASSERT = 1
+};
+
+
+#define USB2PHY_PORT_UTMI_CTRL1 0x40
+
+#define USB2PHY_PORT_UTMI_CTRL2 0x44
+ #define UTMI_ULPI_SEL BIT(7)
+ #define UTMI_TEST_MUX_SEL BIT(6)
+
+#define HS_PHY_CTRL_REG 0x10
+ #define UTMI_OTG_VBUS_VALID BIT(20)
+ #define SW_SESSVLD_SEL BIT(28)
+
+#define USB_PHY_UTMI_CTRL0 0x3c
+
+#define USB_PHY_UTMI_CTRL5 0x50
+ #define POR_EN BIT(1)
+ #define ATERESET ~BIT(0)
+
+#define USB_PHY_HS_PHY_CTRL_COMMON0 0x54
+ #define COMMONONN BIT(7)
+ #define FSEL BIT(4)
+ #define RETENABLEN BIT(3)
+ #define FREQ_24MHZ (5 << 4)
+
+#define USB_PHY_HS_PHY_CTRL2 0x64
+ #define USB2_SUSPEND_N_SEL BIT(3)
+ #define USB2_SUSPEND_N BIT(2)
+ #define USB2_UTMI_CLK_EN BIT(1)
+
+#define USB_PHY_CFG0 0x94
+ #define UTMI_PHY_OVERRIDE_EN BIT(1)
+
+#define USB_PHY_REFCLK_CTRL 0xa0
+ #define CLKCORE BIT(1)
+
+#define USB2PHY_PORT_POWERDOWN 0xa4
+ #define POWER_UP BIT(0)
+ #define POWER_DOWN 0
+
+#define USB_PHY_FSEL_SEL 0xb8
+ #define FREQ_SEL BIT(0)
+
+#define USB2PHY_USB_PHY_M31_XCFGI_1 0xbc
+ #define USB2_0_TX_ENABLE BIT(2)
+
+#define USB2PHY_USB_PHY_M31_XCFGI_4 0xc8
+ #define HSTX_SLEW_RATE_565PS GENMASK(1, 0)
+ #define PLL_CHARGING_PUMP_CURRENT_35UA GENMASK(4, 3)
+ #define ODT_VALUE_38_02_OHM GENMASK(7, 6)
+
+#define USB2PHY_USB_PHY_M31_XCFGI_5 0xcc
+ #define ODT_VALUE_45_02_OHM BIT(2)
+ #define HSTX_PRE_EMPHASIS_LEVEL_0_55MA BIT(0)
+
+#define USB2PHY_USB_PHY_M31_XCFGI_11 0xe4
+ #define XCFG_COARSE_TUNE_NUM BIT(1)
+ #define XCFG_FINE_TUNE_NUM BIT(3)
+
+struct m31_phy_regs {
+ u32 off;
+ u32 val;
+ u32 delay;
+};
+
+struct m31_priv_data {
+ bool ulpi_mode;
+ const struct m31_phy_regs *regs;
+};
+
+#define M31_REG(__o, __v, __d) \
+ { .off = __o, .val = __v, .delay = __d }
+
+#define M31_REG_INVALID 0xffffffffu
+
+struct m31_phy_regs m31_ipq5332_regs[] = {
+ M31_REG(USB_PHY_CFG0, UTMI_PHY_OVERRIDE_EN, 0),
+ M31_REG(USB_PHY_UTMI_CTRL5, POR_EN, 15),
+ M31_REG(USB_PHY_FSEL_SEL, FREQ_SEL, 0),
+ M31_REG(USB_PHY_HS_PHY_CTRL_COMMON0,
+ COMMONONN | FREQ_24MHZ | RETENABLEN, 0),
+ M31_REG(USB_PHY_UTMI_CTRL5, POR_EN & ATERESET, 0),
+ M31_REG(USB_PHY_HS_PHY_CTRL2,
+ USB2_SUSPEND_N_SEL | USB2_SUSPEND_N | USB2_UTMI_CLK_EN, 0),
+ M31_REG(USB2PHY_USB_PHY_M31_XCFGI_11,
+ XCFG_COARSE_TUNE_NUM | XCFG_FINE_TUNE_NUM, 0),
+ M31_REG(USB2PHY_USB_PHY_M31_XCFGI_4,
+ HSTX_SLEW_RATE_565PS | PLL_CHARGING_PUMP_CURRENT_35UA |
+ ODT_VALUE_38_02_OHM, 0),
+ M31_REG(USB2PHY_USB_PHY_M31_XCFGI_1, USB2_0_TX_ENABLE, 0),
+ M31_REG(USB2PHY_USB_PHY_M31_XCFGI_5,
+ ODT_VALUE_45_02_OHM | HSTX_PRE_EMPHASIS_LEVEL_0_55MA, 4),
+ M31_REG(USB_PHY_UTMI_CTRL5, 0x0, 0),
+ M31_REG(USB_PHY_HS_PHY_CTRL2, USB2_SUSPEND_N | USB2_UTMI_CLK_EN, 0),
+ M31_REG(M31_REG_INVALID, 0, 0),
+};
+
+struct m31usb_phy {
+ struct usb_phy phy;
+ void __iomem *base;
+ const struct m31_phy_regs *regs;
+
+ struct clk *cfg_ahb_clk;
+ struct reset_control *phy_reset;
+
+ bool cable_connected;
+ bool suspended;
+ bool ulpi_mode;
+};
+
+static void m31usb_phy_enable_clock(struct m31usb_phy *qphy)
+{
+ const struct m31_phy_regs *regs = qphy->regs;
+
+ for (; regs->off != M31_REG_INVALID; regs++) {
+ writel(regs->val, qphy->base + regs->off);
+ if (regs->delay)
+ udelay(regs->delay);
+ }
+}
+
+static int m31usb_phy_init(struct usb_phy *phy)
+{
+ int ret;
+ struct m31usb_phy *qphy = container_of(phy, struct m31usb_phy, phy);
+
+ ret = clk_prepare_enable(qphy->cfg_ahb_clk);
+ if (ret) {
+ dev_err(phy->dev, "failed to enable cfg ahb clock, %d\n", ret);
+ return ret;
+ }
+
+ /* Perform phy reset */
+ reset_control_assert(qphy->phy_reset);
+ udelay(5);
+ reset_control_deassert(qphy->phy_reset);
+
+ /* configure for ULPI mode if requested */
+ if (qphy->ulpi_mode)
+ writel(0x0, qphy->base + USB2PHY_PORT_UTMI_CTRL2);
+
+ /* Enable the PHY */
+ writel(POWER_UP, qphy->base + USB2PHY_PORT_POWERDOWN);
+
+ /* Make sure above write completed */
+ wmb();
+
+ /* Turn on phy ref clock */
+ m31usb_phy_enable_clock(qphy);
+
+ return 0;
+}
+
+static void m31usb_phy_shutdown(struct usb_phy *phy)
+{
+ struct m31usb_phy *qphy = container_of(phy, struct m31usb_phy, phy);
+
+ /* Disable the PHY */
+ writel_relaxed(POWER_DOWN, qphy->base + USB2PHY_PORT_POWERDOWN);
+ /* Make sure above write completed */
+ wmb();
+
+ clk_disable_unprepare(qphy->cfg_ahb_clk);
+}
+
+static int m31usb_phy_probe(struct platform_device *pdev)
+{
+ const struct m31_priv_data *data;
+ struct device *dev = &pdev->dev;
+ struct m31usb_phy *qphy;
+ int ret;
+
+ qphy = devm_kzalloc(dev, sizeof(*qphy), GFP_KERNEL);
+ if (!qphy)
+ return -ENOMEM;
+
+ qphy->phy.dev = dev;
+
+ qphy->base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(qphy->base))
+ return PTR_ERR(qphy->base);
+
+ qphy->phy_reset = devm_reset_control_get_exclusive_by_index(dev, 0);
+ if (IS_ERR(qphy->phy_reset))
+ return PTR_ERR(qphy->phy_reset);
+
+ qphy->cfg_ahb_clk = devm_clk_get(dev, "cfg_ahb");
+ platform_set_drvdata(pdev, qphy);
+
+ data = of_device_get_match_data(dev);
+ qphy->regs = data->regs;
+ qphy->ulpi_mode = data->ulpi_mode;
+
+ qphy->phy.label = "m31-usb-phy";
+ qphy->phy.init = m31usb_phy_init;
+ qphy->phy.shutdown = m31usb_phy_shutdown;
+ qphy->phy.type = USB_PHY_TYPE_USB2;
+
+ ret = usb_add_phy_dev(&qphy->phy);
+
+ return ret;
+}
+
+static void m31usb_phy_remove(struct platform_device *pdev)
+{
+ struct m31usb_phy *qphy = platform_get_drvdata(pdev);
+
+ usb_remove_phy(&qphy->phy);
+}
+
+struct m31_priv_data m31_ipq5332_data = {
+ .ulpi_mode = false,
+ .regs = m31_ipq5332_regs,
+};
+
+static const struct of_device_id m31usb_phy_id_table[] = {
+ { .compatible = "qcom,ipq5332-usb-hsphy", .data = &m31_ipq5332_data },
+ { },
+};
+MODULE_DEVICE_TABLE(of, m31usb_phy_id_table);
+
+static struct platform_driver m31usb_phy_driver = {
+ .probe = m31usb_phy_probe,
+ .remove_new = m31usb_phy_remove,
+ .driver = {
+ .name = "qcom-m31usb-phy",
+ .of_match_table = m31usb_phy_id_table,
+ },
+};
+
+module_platform_driver(m31usb_phy_driver);
+
+MODULE_DESCRIPTION("USB2 Qualcomm M31 HSPHY driver");
+MODULE_LICENSE("GPL");
--
2.7.4
Enable USB2 in host mode.
Signed-off-by: Varadarajan Narayanan <[email protected]>
---
v1:
Enable usb-phy node
---
arch/arm64/boot/dts/qcom/ipq5332-rdp468.dts | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/ipq5332-rdp468.dts b/arch/arm64/boot/dts/qcom/ipq5332-rdp468.dts
index f96b0c8..f5dea16 100644
--- a/arch/arm64/boot/dts/qcom/ipq5332-rdp468.dts
+++ b/arch/arm64/boot/dts/qcom/ipq5332-rdp468.dts
@@ -79,3 +79,15 @@
bias-pull-up;
};
};
+
+&usbphy0 {
+ status = "okay";
+};
+
+&usb2 {
+ status = "okay";
+};
+
+&usb2_0_dwc {
+ dr_mode = "host";
+};
--
2.7.4
On 11/07/2023 10:51, Varadarajan Narayanan wrote:
> Document the IPQ5332 dwc3 compatible.
>
> Signed-off-by: Varadarajan Narayanan <[email protected]>
> ---
> v1:
> Add ipq5332 to interrupts sections
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Best regards,
Krzysztof
On 11/07/2023 10:51, Varadarajan Narayanan wrote:
> Add the M31 USB2 phy driver.
>
> Signed-off-by: Varadarajan Narayanan <[email protected]>
> ---
> v1:
> Combine driver, makefile and kconfig into 1 patch
> Remove 'qscratch' region and its usage. The controller driver takes care
> of those settings
> Use compatible/data to handle ipq5332 init
> Drop the default case
> Get resources by index instead of name as there is only one resource
> Add clock
> Fix review comments in the driver
> ---
> drivers/phy/qualcomm/Kconfig | 11 ++
> drivers/phy/qualcomm/Makefile | 1 +
> drivers/phy/qualcomm/phy-qcom-m31.c | 256 ++++++++++++++++++++++++++++++++++++
> 3 files changed, 268 insertions(+)
> create mode 100644 drivers/phy/qualcomm/phy-qcom-m31.c
>
> diff --git a/drivers/phy/qualcomm/Kconfig b/drivers/phy/qualcomm/Kconfig
> index 97ca595..76be191 100644
> --- a/drivers/phy/qualcomm/Kconfig
> +++ b/drivers/phy/qualcomm/Kconfig
> @@ -197,3 +197,14 @@ config PHY_QCOM_SGMII_ETH
> help
> Enable this to support the internal SerDes/SGMII PHY on various
> Qualcomm chipsets.
> +
> +config PHY_QCOM_M31_USB
> + tristate "Qualcomm M31 HS PHY driver support"
> + depends on (USB || USB_GADGET) && ARCH_QCOM
> + select USB_PHY
> + help
> + Enable this to support M31 HS PHY transceivers on Qualcomm chips
> + with DWC3 USB core. It handles PHY initialization, clock
> + management required after resetting the hardware and power
> + management. This driver is required even for peripheral only or
> + host only mode configurations.
> diff --git a/drivers/phy/qualcomm/Makefile b/drivers/phy/qualcomm/Makefile
> index b030858..0b5dd66 100644
> --- a/drivers/phy/qualcomm/Makefile
> +++ b/drivers/phy/qualcomm/Makefile
> @@ -22,3 +22,4 @@ obj-$(CONFIG_PHY_QCOM_USB_SS) += phy-qcom-usb-ss.o
> obj-$(CONFIG_PHY_QCOM_USB_SNPS_FEMTO_V2)+= phy-qcom-snps-femto-v2.o
> obj-$(CONFIG_PHY_QCOM_IPQ806X_USB) += phy-qcom-ipq806x-usb.o
> obj-$(CONFIG_PHY_QCOM_SGMII_ETH) += phy-qcom-sgmii-eth.o
> +obj-$(CONFIG_PHY_QCOM_M31_USB) += phy-qcom-m31.o
> diff --git a/drivers/phy/qualcomm/phy-qcom-m31.c b/drivers/phy/qualcomm/phy-qcom-m31.c
> new file mode 100644
> index 0000000..8700728
> --- /dev/null
> +++ b/drivers/phy/qualcomm/phy-qcom-m31.c
> @@ -0,0 +1,256 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (c) 2014-2016, 2020, The Linux Foundation. All rights reserved.
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/delay.h>
> +#include <linux/err.h>
> +#include <linux/io.h>
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/of_device.h>
> +#include <linux/of.h>
> +#include <linux/platform_device.h>
> +#include <linux/reset.h>
> +#include <linux/slab.h>
> +#include <linux/usb/of.h>
> +#include <linux/usb/phy.h>
> +
> +enum clk_reset_action {
> + CLK_RESET_DEASSERT = 0,
> + CLK_RESET_ASSERT = 1
> +};
Drop entire enum. I don't see it being used.
...
> +
> +static int m31usb_phy_probe(struct platform_device *pdev)
> +{
> + const struct m31_priv_data *data;
> + struct device *dev = &pdev->dev;
> + struct m31usb_phy *qphy;
> + int ret;
> +
> + qphy = devm_kzalloc(dev, sizeof(*qphy), GFP_KERNEL);
> + if (!qphy)
> + return -ENOMEM;
> +
> + qphy->phy.dev = dev;
> +
> + qphy->base = devm_platform_ioremap_resource(pdev, 0);
> + if (IS_ERR(qphy->base))
> + return PTR_ERR(qphy->base);
> +
> + qphy->phy_reset = devm_reset_control_get_exclusive_by_index(dev, 0);
> + if (IS_ERR(qphy->phy_reset))
> + return PTR_ERR(qphy->phy_reset);
> +
> + qphy->cfg_ahb_clk = devm_clk_get(dev, "cfg_ahb");
How do you handle errors? I don't see it.
> + platform_set_drvdata(pdev, qphy);
> +
> + data = of_device_get_match_data(dev);
> + qphy->regs = data->regs;
> + qphy->ulpi_mode = data->ulpi_mode;
> +
> + qphy->phy.label = "m31-usb-phy";
> + qphy->phy.init = m31usb_phy_init;
> + qphy->phy.shutdown = m31usb_phy_shutdown;
> + qphy->phy.type = USB_PHY_TYPE_USB2;
> +
> + ret = usb_add_phy_dev(&qphy->phy);
> +
> + return ret;
> +}
> +
> +static void m31usb_phy_remove(struct platform_device *pdev)
> +{
> + struct m31usb_phy *qphy = platform_get_drvdata(pdev);
> +
> + usb_remove_phy(&qphy->phy);
> +}
> +
> +struct m31_priv_data m31_ipq5332_data = {
static const
> + .ulpi_mode = false,
> + .regs = m31_ipq5332_regs,
> +};
Best regards,
Krzysztof
On Tue, Jul 11, 2023 at 11:01:03AM +0200, Krzysztof Kozlowski wrote:
> On 11/07/2023 10:51, Varadarajan Narayanan wrote:
> > Add USB phy and controller nodes.
> >
> > Signed-off-by: Varadarajan Narayanan <[email protected]>
> > ---
> > v1:
> > Rename phy node
>
> I don't see any improvements.
Will fix and post a new patch
> > Change compatible from m31,ipq5332-usb-hsphy -> qcom,ipq5332-usb-hsphy
> > Remove 'qscratch' from phy node
> > Fix alignment and upper-case hex no.s
> > Add clock definition for the phy
> > Remove snps,ref-clock-period-ns as it is not used. dwc3_ref_clk_period()
> > in dwc3/core.c takes the frequency from ref clock and calculates fladj
> > as appropriate.
> > ---
> > arch/arm64/boot/dts/qcom/ipq5332.dtsi | 54 +++++++++++++++++++++++++++++++++++
> > 1 file changed, 54 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/qcom/ipq5332.dtsi b/arch/arm64/boot/dts/qcom/ipq5332.dtsi
> > index 8bfc2db..c945ff6 100644
> > --- a/arch/arm64/boot/dts/qcom/ipq5332.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi
> > @@ -405,6 +405,60 @@
> > status = "disabled";
> > };
> > };
> > +
> > + usbphy0: ipq5332-hsphy@7b000 {
>
> Node names should be generic. See also an explanation and list of
> examples (not exhaustive) in DT specification:
> https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetree-basics.html#generic-names-recommendation
>
> "phy"
Will fix and post a new patch
> > + compatible = "qcom,ipq5332-usb-hsphy";
> > + reg = <0x0007b000 0x12c>;
> > +
> > + clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>;
> > + clock-names = "cfg_ahb";
> > +
> > + resets = <&gcc GCC_QUSB2_0_PHY_BCR>;
> > +
> > + status = "disabled";
> > + };
> > +
> > + usb2: usb2@8a00000 {
>
> It does not look like you tested the DTS against bindings. Please run
> `make dtbs_check` (see
> Documentation/devicetree/bindings/writing-schema.rst or
> https://www.linaro.org/blog/tips-and-tricks-for-validating-devicetree-sources-with-the-devicetree-schema/
> for instructions).
'make dtbs_check' passed. The '2' in 'usb2' is to indicate USB v2.
There is one more USB v3 controller in this SoC. Hence, to
differentiate between the two used 'usb2'.
Hope that is ok.
> > + compatible = "qcom,ipq5332-dwc3", "qcom,dwc3";
> > +
>
> No need for blank line.
Will remove.
Thanks
Varada
> > + reg = <0x08af8800 0x400>;
> > +
> > + interrupts = <GIC_SPI 62 IRQ_
>
>
> Best regards,
> Krzysztof
>
On 12/07/2023 13:28, Varadarajan Narayanan wrote:
>>> +
>>> + usb2: usb2@8a00000 {
>>
>> It does not look like you tested the DTS against bindings. Please run
>> `make dtbs_check` (see
>> Documentation/devicetree/bindings/writing-schema.rst or
>> https://www.linaro.org/blog/tips-and-tricks-for-validating-devicetree-sources-with-the-devicetree-schema/
>> for instructions).
>
> 'make dtbs_check' passed. The '2' in 'usb2' is to indicate USB v2.
> There is one more USB v3 controller in this SoC. Hence, to
> differentiate between the two used 'usb2'.
>
> Hope that is ok.
Nope, unfortunately it is not.
Best regards,
Krzysztof
On 11/07/2023 10:51, Varadarajan Narayanan wrote:
> Document the M31 USB2 phy present in IPQ5332.
>
> Signed-off-by: Sricharan Ramabadhran <[email protected]>
> Signed-off-by: Varadarajan Narayanan <[email protected]>
> ---
> v3:
> Incorporate review comments. Will bring in ipq5018 compatible
> string while posting ipq5018 usb patchset.
>
> v1:
> Rename qcom,m31.yaml -> qcom,ipq5332-usb-hsphy.yaml
> Drop default binding "m31,usb-hsphy"
> Add clock
> Remove 'oneOf' from compatible
> Remove 'qscratch' region from register space as it is not needed
> Remove reset-names
> Fix the example definition
> ---
> .../bindings/phy/qcom,ipq5332-usb-hsphy.yaml | 49 ++++++++++++++++++++++
> 1 file changed, 49 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/phy/qcom,ipq5332-usb-hsphy.yaml
>
> diff --git a/Documentation/devicetree/bindings/phy/qcom,ipq5332-usb-hsphy.yaml b/Documentation/devicetree/bindings/phy/qcom,ipq5332-usb-hsphy.yaml
> new file mode 100644
> index 0000000..2cfdd73
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/qcom,ipq5332-usb-hsphy.yaml
> @@ -0,0 +1,49 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/phy/qcom,ipq5332-usb-hsphy.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: M31 (https://www.m31tech.com) USB PHY
> +
> +maintainers:
> + - Sricharan Ramabadhran <[email protected]>
> + - Varadarajan Narayanan <[email protected]>
I was wondering why I keep receiving delays/bounces for my emails in
this thread... and here we have. Please correct your email.
Best regards,
Krzysztof