When the RK3568 PCIe v3 PHY supported has been upstreamed, RK3588
support was included, but the DT binding does not reflect this.
This adds the missing bits.
Reviewed-by: Conor Dooley <[email protected]>
Signed-off-by: Sebastian Reichel <[email protected]>
---
.../bindings/phy/rockchip,pcie3-phy.yaml | 33 ++++++++++++++++---
1 file changed, 28 insertions(+), 5 deletions(-)
diff --git a/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml b/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml
index 9f2d8d2cc7a5..c4fbffcde6e4 100644
--- a/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml
@@ -13,19 +13,18 @@ properties:
compatible:
enum:
- rockchip,rk3568-pcie3-phy
+ - rockchip,rk3588-pcie3-phy
reg:
maxItems: 1
clocks:
- minItems: 3
+ minItems: 1
maxItems: 3
clock-names:
- items:
- - const: refclk_m
- - const: refclk_n
- - const: pclk
+ minItems: 1
+ maxItems: 3
data-lanes:
description: which lanes (by position) should be mapped to which
@@ -61,6 +60,30 @@ required:
- rockchip,phy-grf
- "#phy-cells"
+allOf:
+ - if:
+ properties:
+ compatible:
+ enum:
+ - rockchip,rk3588-pcie3-phy
+ then:
+ properties:
+ clocks:
+ maxItems: 1
+ clock-names:
+ items:
+ - const: pclk
+ else:
+ properties:
+ clocks:
+ minItems: 3
+
+ clock-names:
+ items:
+ - const: refclk_m
+ - const: refclk_n
+ - const: pclk
+
additionalProperties: false
examples:
--
2.40.1