Add temperature sensor and thermal-zones support for
the StarFive JH7110 SoC. CPUFreq cooling is supported
in thermal-zones.
Co-developed-by: Emil Renner Berthing <[email protected]>
Signed-off-by: Emil Renner Berthing <[email protected]>
Signed-off-by: Hal Feng <[email protected]>
---
arch/riscv/boot/dts/starfive/jh7110.dtsi | 53 ++++++++++++++++++++++++
1 file changed, 53 insertions(+)
diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
index ec2e70011a73..2315acd560a3 100644
--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
@@ -7,6 +7,7 @@
/dts-v1/;
#include <dt-bindings/clock/starfive,jh7110-crg.h>
#include <dt-bindings/reset/starfive,jh7110-crg.h>
+#include <dt-bindings/thermal/thermal.h>
/ {
compatible = "starfive,jh7110";
@@ -56,6 +57,7 @@ U74_1: cpu@1 {
operating-points-v2 = <&cpu_opp>;
clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>;
clock-names = "cpu";
+ #cooling-cells = <2>;
cpu1_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
@@ -85,6 +87,7 @@ U74_2: cpu@2 {
operating-points-v2 = <&cpu_opp>;
clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>;
clock-names = "cpu";
+ #cooling-cells = <2>;
cpu2_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
@@ -114,6 +117,7 @@ U74_3: cpu@3 {
operating-points-v2 = <&cpu_opp>;
clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>;
clock-names = "cpu";
+ #cooling-cells = <2>;
cpu3_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
@@ -143,6 +147,7 @@ U74_4: cpu@4 {
operating-points-v2 = <&cpu_opp>;
clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>;
clock-names = "cpu";
+ #cooling-cells = <2>;
cpu4_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
@@ -197,6 +202,42 @@ opp-1500000000 {
};
};
+ thermal-zones {
+ cpu-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <15000>;
+
+ thermal-sensors = <&sfctemp>;
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu_alert0>;
+ cooling-device =
+ <&U74_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&U74_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&U74_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&U74_4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+
+ trips {
+ cpu_alert0: cpu_alert0 {
+ /* milliCelsius */
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu_crit {
+ /* milliCelsius */
+ temperature = <100000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+ };
+ };
+
gmac0_rgmii_rxin: gmac0-rgmii-rxin-clock {
compatible = "fixed-clock";
clock-output-names = "gmac0_rgmii_rxin";
@@ -473,6 +514,18 @@ i2c6: i2c@12060000 {
status = "disabled";
};
+ sfctemp: temperature-sensor@120e0000 {
+ compatible = "starfive,jh7110-temp";
+ reg = <0x0 0x120e0000 0x0 0x10000>;
+ clocks = <&syscrg JH7110_SYSCLK_TEMP_CORE>,
+ <&syscrg JH7110_SYSCLK_TEMP_APB>;
+ clock-names = "sense", "bus";
+ resets = <&syscrg JH7110_SYSRST_TEMP_CORE>,
+ <&syscrg JH7110_SYSRST_TEMP_APB>;
+ reset-names = "sense", "bus";
+ #thermal-sensor-cells = <0>;
+ };
+
syscrg: clock-controller@13020000 {
compatible = "starfive,jh7110-syscrg";
reg = <0x0 0x13020000 0x0 0x10000>;
--
2.38.1