Update GCC clocks and add support for GDSCs for QDU1000 and QRU1000 SoCs.
Changes since v3:
- Split the gcc rcg ops changes as per the review comments
Changes since v2:
- Split the gcc clkref clock changes as per the review comments
Changes since v1:
- Dropped the v2 variant compatible changes
- Update tha maintainers list
- Split the GCC driver patch as per the review comments
Previous series:
v3 - https://patchwork.kernel.org/project/linux-arm-msm/list/?series=763044
v2 - https://patchwork.kernel.org/project/linux-arm-msm/list/?series=760862
v1 - https://patchwork.kernel.org/project/linux-arm-msm/list/?series=757828
Imran Shaik (7):
dt-bindings: clock: Update GCC clocks for QDU1000 and QRU1000 SoCs
clk: qcom: gcc-qdu1000: Fix gcc_pcie_0_pipe_clk_src clock handling
clk: qcom: gcc-qdu1000: Fix clkref clocks handling
clk: qcom: gcc-qdu1000: Update GCC clocks as per the latest hw version
clk: qcom: gcc-qdu1000: Add support for GDSCs
clk: qcom: gcc-qdu1000: Update the SDCC clock RCG ops
clk: qcom: gcc-qdu1000: Update the RCGs ops
.../bindings/clock/qcom,qdu1000-gcc.yaml | 3 +-
drivers/clk/qcom/gcc-qdu1000.c | 159 ++++++++++++------
include/dt-bindings/clock/qcom,qdu1000-gcc.h | 4 +-
3 files changed, 110 insertions(+), 56 deletions(-)
--
2.25.1
Update the qcom GCC clock bindings for QDU1000 and QRU1000 SoCs.
Co-developed-by: Taniya Das <[email protected]>
Signed-off-by: Taniya Das <[email protected]>
Signed-off-by: Imran Shaik <[email protected]>
Acked-by: Rob Herring <[email protected]>
---
Changes since v3:
- None
Changes since v2:
- None
Changes since v1:
- Removed the v2 variant compatible string changes
- Updated the maintainers list
Documentation/devicetree/bindings/clock/qcom,qdu1000-gcc.yaml | 3 ++-
include/dt-bindings/clock/qcom,qdu1000-gcc.h | 4 +++-
2 files changed, 5 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/qcom,qdu1000-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,qdu1000-gcc.yaml
index 767a9d03aa32..d712b1a87e25 100644
--- a/Documentation/devicetree/bindings/clock/qcom,qdu1000-gcc.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,qdu1000-gcc.yaml
@@ -7,7 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Global Clock & Reset Controller for QDU1000 and QRU1000
maintainers:
- - Melody Olvera <[email protected]>
+ - Taniya Das <[email protected]>
+ - Imran Shaik <[email protected]>
description: |
Qualcomm global clock control module which supports the clocks, resets and
diff --git a/include/dt-bindings/clock/qcom,qdu1000-gcc.h b/include/dt-bindings/clock/qcom,qdu1000-gcc.h
index ddbc6b825e80..2fd36cbfddbb 100644
--- a/include/dt-bindings/clock/qcom,qdu1000-gcc.h
+++ b/include/dt-bindings/clock/qcom,qdu1000-gcc.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
/*
- * Copyright (c) 2021-2022, Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2021-2023, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _DT_BINDINGS_CLK_QCOM_GCC_QDU1000_H
@@ -138,6 +138,8 @@
#define GCC_AGGRE_NOC_ECPRI_GSI_CLK 128
#define GCC_PCIE_0_PIPE_CLK_SRC 129
#define GCC_PCIE_0_PHY_AUX_CLK_SRC 130
+#define GCC_GPLL1_OUT_EVEN 131
+#define GCC_DDRSS_ECPRI_GSI_CLK 132
/* GCC resets */
#define GCC_ECPRI_CC_BCR 0
--
2.25.1
Fix the gcc clkref clock ops and update the halt_check as per the
latest hw version of QDU1000 and QRU1000 SoCs.
Fixes: 1c9efb0bc040 ("clk: qcom: Add QDU1000 and QRU1000 GCC support")
Co-developed-by: Taniya Das <[email protected]>
Signed-off-by: Taniya Das <[email protected]>
Signed-off-by: Imran Shaik <[email protected]>
---
Changes since v3:
- None
Changes since v2:
- Split the patch as per the review comments
- Newly added
drivers/clk/qcom/gcc-qdu1000.c | 10 ++++------
1 file changed, 4 insertions(+), 6 deletions(-)
diff --git a/drivers/clk/qcom/gcc-qdu1000.c b/drivers/clk/qcom/gcc-qdu1000.c
index c00d26a3e6df..8df7b7983968 100644
--- a/drivers/clk/qcom/gcc-qdu1000.c
+++ b/drivers/clk/qcom/gcc-qdu1000.c
@@ -1447,14 +1447,13 @@ static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {
static struct clk_branch gcc_pcie_0_clkref_en = {
.halt_reg = 0x9c004,
- .halt_bit = 31,
- .halt_check = BRANCH_HALT_ENABLE,
+ .halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x9c004,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_0_clkref_en",
- .ops = &clk_branch_ops,
+ .ops = &clk_branch2_ops,
},
},
};
@@ -2274,14 +2273,13 @@ static struct clk_branch gcc_tsc_etu_clk = {
static struct clk_branch gcc_usb2_clkref_en = {
.halt_reg = 0x9c008,
- .halt_bit = 31,
- .halt_check = BRANCH_HALT_ENABLE,
+ .halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x9c008,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb2_clkref_en",
- .ops = &clk_branch_ops,
+ .ops = &clk_branch2_ops,
},
},
};
--
2.25.1
Update the GCC SDCC clock RCG ops to floor_ops to avoid
the overclocking issues on QDU1000 and QRU1000 SoCs.
Co-developed-by: Taniya Das <[email protected]>
Signed-off-by: Taniya Das <[email protected]>
Signed-off-by: Imran Shaik <[email protected]>
---
Changes since v3:
- Split the patch as per the review comments
- Newly added
drivers/clk/qcom/gcc-qdu1000.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/qcom/gcc-qdu1000.c b/drivers/clk/qcom/gcc-qdu1000.c
index 718c34dca6e8..540577ae58e4 100644
--- a/drivers/clk/qcom/gcc-qdu1000.c
+++ b/drivers/clk/qcom/gcc-qdu1000.c
@@ -903,7 +903,7 @@ static struct clk_rcg2 gcc_sdcc5_apps_clk_src = {
.name = "gcc_sdcc5_apps_clk_src",
.parent_data = gcc_parent_data_8,
.num_parents = ARRAY_SIZE(gcc_parent_data_8),
- .ops = &clk_rcg2_ops,
+ .ops = &clk_rcg2_floor_ops,
},
};
@@ -922,7 +922,7 @@ static struct clk_rcg2 gcc_sdcc5_ice_core_clk_src = {
.name = "gcc_sdcc5_ice_core_clk_src",
.parent_data = gcc_parent_data_2,
.num_parents = ARRAY_SIZE(gcc_parent_data_2),
- .ops = &clk_rcg2_ops,
+ .ops = &clk_rcg2_floor_ops,
},
};
--
2.25.1
Fix the gcc pcie pipe clock handling as per the clk_regmap_phy_mux_ops
implementation to let the clock framework automatically park the clock
at XO when the clock is switched off and restore the parent when the
clock is switched on.
Fixes: 1c9efb0bc040 ("clk: qcom: Add QDU1000 and QRU1000 GCC support")
Co-developed-by: Taniya Das <[email protected]>
Signed-off-by: Taniya Das <[email protected]>
Signed-off-by: Imran Shaik <[email protected]>
Reviewed-by: Konrad Dybcio <[email protected]>
---
Changes since v3:
- None
Changes since v2:
- Updated the commit text
Changes since v1:
- Newly added
drivers/clk/qcom/gcc-qdu1000.c | 23 ++++++-----------------
1 file changed, 6 insertions(+), 17 deletions(-)
diff --git a/drivers/clk/qcom/gcc-qdu1000.c b/drivers/clk/qcom/gcc-qdu1000.c
index 5051769ad90c..c00d26a3e6df 100644
--- a/drivers/clk/qcom/gcc-qdu1000.c
+++ b/drivers/clk/qcom/gcc-qdu1000.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
- * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <linux/clk-provider.h>
@@ -370,16 +370,6 @@ static const struct clk_parent_data gcc_parent_data_6[] = {
{ .index = DT_TCXO_IDX },
};
-static const struct parent_map gcc_parent_map_7[] = {
- { P_PCIE_0_PIPE_CLK, 0 },
- { P_BI_TCXO, 2 },
-};
-
-static const struct clk_parent_data gcc_parent_data_7[] = {
- { .index = DT_PCIE_0_PIPE_CLK_IDX },
- { .index = DT_TCXO_IDX },
-};
-
static const struct parent_map gcc_parent_map_8[] = {
{ P_BI_TCXO, 0 },
{ P_GCC_GPLL0_OUT_MAIN, 1 },
@@ -439,16 +429,15 @@ static struct clk_regmap_mux gcc_pcie_0_phy_aux_clk_src = {
},
};
-static struct clk_regmap_mux gcc_pcie_0_pipe_clk_src = {
+static struct clk_regmap_phy_mux gcc_pcie_0_pipe_clk_src = {
.reg = 0x9d064,
- .shift = 0,
- .width = 2,
- .parent_map = gcc_parent_map_7,
.clkr = {
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_0_pipe_clk_src",
- .parent_data = gcc_parent_data_7,
- .num_parents = ARRAY_SIZE(gcc_parent_data_7),
+ .parent_data = &(const struct clk_parent_data){
+ .index = DT_PCIE_0_PIPE_CLK_IDX,
+ },
+ .num_parents = 1,
.ops = &clk_regmap_phy_mux_ops,
},
},
--
2.25.1
On Wed, Jul 19, 2023 at 09:44:44AM +0530, Imran Shaik wrote:
> Update the qcom GCC clock bindings for QDU1000 and QRU1000 SoCs.
>
Please read [1], and as it says "Describe your problem.". This goes for
the most of the series.
There are changes in this series which could be applicable to existing
or future platforms. Your description of the problems you're solving
will help others solve the same problem, not make the same mistake, and
anyone fixing adjacent issues in the future can rely on your
documentation of why things looks the way they look.
[1] https://www.kernel.org/doc/html/v4.17/process/submitting-patches.html#describe-your-changes
> Co-developed-by: Taniya Das <[email protected]>
> Signed-off-by: Taniya Das <[email protected]>
> Signed-off-by: Imran Shaik <[email protected]>
Please don't use co-developed-by excessively. This patch is beyond
trivial, did you really both author it?
Regards,
Bjorn
> Acked-by: Rob Herring <[email protected]>
> ---
> Changes since v3:
> - None
> Changes since v2:
> - None
> Changes since v1:
> - Removed the v2 variant compatible string changes
> - Updated the maintainers list
>
> Documentation/devicetree/bindings/clock/qcom,qdu1000-gcc.yaml | 3 ++-
> include/dt-bindings/clock/qcom,qdu1000-gcc.h | 4 +++-
> 2 files changed, 5 insertions(+), 2 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/clock/qcom,qdu1000-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,qdu1000-gcc.yaml
> index 767a9d03aa32..d712b1a87e25 100644
> --- a/Documentation/devicetree/bindings/clock/qcom,qdu1000-gcc.yaml
> +++ b/Documentation/devicetree/bindings/clock/qcom,qdu1000-gcc.yaml
> @@ -7,7 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
> title: Qualcomm Global Clock & Reset Controller for QDU1000 and QRU1000
>
> maintainers:
> - - Melody Olvera <[email protected]>
> + - Taniya Das <[email protected]>
> + - Imran Shaik <[email protected]>
>
> description: |
> Qualcomm global clock control module which supports the clocks, resets and
> diff --git a/include/dt-bindings/clock/qcom,qdu1000-gcc.h b/include/dt-bindings/clock/qcom,qdu1000-gcc.h
> index ddbc6b825e80..2fd36cbfddbb 100644
> --- a/include/dt-bindings/clock/qcom,qdu1000-gcc.h
> +++ b/include/dt-bindings/clock/qcom,qdu1000-gcc.h
> @@ -1,6 +1,6 @@
> /* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
> /*
> - * Copyright (c) 2021-2022, Qualcomm Innovation Center, Inc. All rights reserved.
> + * Copyright (c) 2021-2023, Qualcomm Innovation Center, Inc. All rights reserved.
> */
>
> #ifndef _DT_BINDINGS_CLK_QCOM_GCC_QDU1000_H
> @@ -138,6 +138,8 @@
> #define GCC_AGGRE_NOC_ECPRI_GSI_CLK 128
> #define GCC_PCIE_0_PIPE_CLK_SRC 129
> #define GCC_PCIE_0_PHY_AUX_CLK_SRC 130
> +#define GCC_GPLL1_OUT_EVEN 131
> +#define GCC_DDRSS_ECPRI_GSI_CLK 132
>
> /* GCC resets */
> #define GCC_ECPRI_CC_BCR 0
> --
> 2.25.1
>
On 7/19/2023 9:05 PM, Bjorn Andersson wrote:
> On Wed, Jul 19, 2023 at 09:44:44AM +0530, Imran Shaik wrote:
>> Update the qcom GCC clock bindings for QDU1000 and QRU1000 SoCs.
>>
>
> Please read [1], and as it says "Describe your problem.". This goes for
> the most of the series.
>
> There are changes in this series which could be applicable to existing
> or future platforms. Your description of the problems you're solving
> will help others solve the same problem, not make the same mistake, and
> anyone fixing adjacent issues in the future can rely on your
> documentation of why things looks the way they look.
>
> [1] https://www.kernel.org/doc/html/v4.17/process/submitting-patches.html#describe-your-changes
>
Sure, will update the next series with the detailed commit text.
>> Co-developed-by: Taniya Das <[email protected]>
>> Signed-off-by: Taniya Das <[email protected]>
>> Signed-off-by: Imran Shaik <[email protected]>
>
> Please don't use co-developed-by excessively. This patch is beyond
> trivial, did you really both author it?
>
> Regards,
> Bjorn
>
Sure, will take care of this from now and will remove the
co-developed-by for trivial changes in next series.
Thanks,
Imran
>> Acked-by: Rob Herring <[email protected]>
>> ---
>> Changes since v3:
>> - None
>> Changes since v2:
>> - None
>> Changes since v1:
>> - Removed the v2 variant compatible string changes
>> - Updated the maintainers list
>>
>> Documentation/devicetree/bindings/clock/qcom,qdu1000-gcc.yaml | 3 ++-
>> include/dt-bindings/clock/qcom,qdu1000-gcc.h | 4 +++-
>> 2 files changed, 5 insertions(+), 2 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/clock/qcom,qdu1000-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,qdu1000-gcc.yaml
>> index 767a9d03aa32..d712b1a87e25 100644
>> --- a/Documentation/devicetree/bindings/clock/qcom,qdu1000-gcc.yaml
>> +++ b/Documentation/devicetree/bindings/clock/qcom,qdu1000-gcc.yaml
>> @@ -7,7 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
>> title: Qualcomm Global Clock & Reset Controller for QDU1000 and QRU1000
>>
>> maintainers:
>> - - Melody Olvera <[email protected]>
>> + - Taniya Das <[email protected]>
>> + - Imran Shaik <[email protected]>
>>
>> description: |
>> Qualcomm global clock control module which supports the clocks, resets and
>> diff --git a/include/dt-bindings/clock/qcom,qdu1000-gcc.h b/include/dt-bindings/clock/qcom,qdu1000-gcc.h
>> index ddbc6b825e80..2fd36cbfddbb 100644
>> --- a/include/dt-bindings/clock/qcom,qdu1000-gcc.h
>> +++ b/include/dt-bindings/clock/qcom,qdu1000-gcc.h
>> @@ -1,6 +1,6 @@
>> /* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
>> /*
>> - * Copyright (c) 2021-2022, Qualcomm Innovation Center, Inc. All rights reserved.
>> + * Copyright (c) 2021-2023, Qualcomm Innovation Center, Inc. All rights reserved.
>> */
>>
>> #ifndef _DT_BINDINGS_CLK_QCOM_GCC_QDU1000_H
>> @@ -138,6 +138,8 @@
>> #define GCC_AGGRE_NOC_ECPRI_GSI_CLK 128
>> #define GCC_PCIE_0_PIPE_CLK_SRC 129
>> #define GCC_PCIE_0_PHY_AUX_CLK_SRC 130
>> +#define GCC_GPLL1_OUT_EVEN 131
>> +#define GCC_DDRSS_ECPRI_GSI_CLK 132
>>
>> /* GCC resets */
>> #define GCC_ECPRI_CC_BCR 0
>> --
>> 2.25.1
>>
On 19.07.2023 06:14, Imran Shaik wrote:
> Fix the gcc clkref clock ops and update the halt_check as per the
> latest hw version of QDU1000 and QRU1000 SoCs.
>
> Fixes: 1c9efb0bc040 ("clk: qcom: Add QDU1000 and QRU1000 GCC support")
> Co-developed-by: Taniya Das <[email protected]>
> Signed-off-by: Taniya Das <[email protected]>
> Signed-off-by: Imran Shaik <[email protected]>
> ---
Reviewed-by: Konrad Dybcio <[email protected]>
Konrad
On 19.07.2023 06:14, Imran Shaik wrote:
> Update the GCC SDCC clock RCG ops to floor_ops to avoid
> the overclocking issues on QDU1000 and QRU1000 SoCs.
>
> Co-developed-by: Taniya Das <[email protected]>
> Signed-off-by: Taniya Das <[email protected]>
> Signed-off-by: Imran Shaik <[email protected]>
> ---
Reviewed-by: Konrad Dybcio <[email protected]>
Konrad