RTC interrupt level should be set to "LOW". This was revealed by the
introduction of commit:
f181987ef477 ("rtc: m41t80: use IRQ flags obtained from fwnode")
which changed the way IRQ type is obtained.
Signed-off-by: Andrej Picej <[email protected]>
---
Changes in v2:
- no changes
---
arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-mira.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-mira.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-mira.dtsi
index 1a599c294ab8..1ca4d219609f 100644
--- a/arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-mira.dtsi
+++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-mira.dtsi
@@ -182,7 +182,7 @@ i2c_rtc: rtc@68 {
pinctrl-0 = <&pinctrl_rtc_int>;
reg = <0x68>;
interrupt-parent = <&gpio7>;
- interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
status = "disabled";
};
};
--
2.25.1
Hi Andrej,
On Wed, 2023-07-19 at 13:43 +0200, Andrej Picej wrote:
> RTC interrupt level should be set to "LOW". This was revealed by the
> introduction of commit:
>
> f181987ef477 ("rtc: m41t80: use IRQ flags obtained from fwnode")
>
> which changed the way IRQ type is obtained.
>
> Signed-off-by: Andrej Picej <[email protected]>
Reviewed-by: Stefan Riedmüller <[email protected]>
> ---
> Changes in v2:
> - no changes
> ---
> arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-mira.dtsi | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-mira.dtsi
> b/arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-mira.dtsi
> index 1a599c294ab8..1ca4d219609f 100644
> --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-mira.dtsi
> +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-mira.dtsi
> @@ -182,7 +182,7 @@ i2c_rtc: rtc@68 {
> pinctrl-0 = <&pinctrl_rtc_int>;
> reg = <0x68>;
> interrupt-parent = <&gpio7>;
> - interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
> + interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
> status = "disabled";
> };
> };
Due to the missing signal connection between i.MX6 WDOG_B pin and the
PMICs external reset, the internal i.MX6 watchdog is not able to reset
the phyCORE i.MX6 SoM properly. Thus disable the internal i.MX6 watchdog
to prevent unexpected PMIC settings after reset.
NOTE: This patch should not be backported as it might break existing
uses and fixes in bootloaders.
Signed-off-by: Andrej Picej <[email protected]>
---
Changes in v2:
- new patch
- i.MX6 phyCOREs have the same problem as phyFLEX devices.
---
arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-phycore-som.dtsi | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-phycore-som.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-phycore-som.dtsi
index 28a805384668..86b4269e0e01 100644
--- a/arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-phycore-som.dtsi
+++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-phycore-som.dtsi
@@ -309,3 +309,11 @@ MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059
>;
};
};
+
+&wdog1 {
+ /*
+ * Rely on PMIC reboot handler. Internal i.MX6 watchdog, that is also
+ * used for reboot, does not reset all external PMIC voltages on reset.
+ */
+ status = "disabled";
+};
--
2.25.1
On Wed, Jul 19, 2023 at 01:43:26PM +0200, Andrej Picej wrote:
> RTC interrupt level should be set to "LOW". This was revealed by the
> introduction of commit:
>
> f181987ef477 ("rtc: m41t80: use IRQ flags obtained from fwnode")
>
> which changed the way IRQ type is obtained.
>
> Signed-off-by: Andrej Picej <[email protected]>
Applied as a fix with tag:
Fixes: 800d595151bb ("ARM: dts: imx6: Add initial support for phyBOARD-Mira")
Shawn
On Wed, Jul 19, 2023 at 01:43:28PM +0200, Andrej Picej wrote:
> Due to the missing signal connection between i.MX6 WDOG_B pin and the
> PMICs external reset, the internal i.MX6 watchdog is not able to reset
> the phyCORE i.MX6 SoM properly. Thus disable the internal i.MX6 watchdog
> to prevent unexpected PMIC settings after reset.
>
> NOTE: This patch should not be backported as it might break existing
> uses and fixes in bootloaders.
>
> Signed-off-by: Andrej Picej <[email protected]>
Applied, thanks!