This series adds initial support for the eMMC on the BeagleV Ahead
board. This allows the kernel to boot with the root fs on eMMC.
I tested [1] on top of v6.5-rc3 along with the prerequisite series [2]
that adds the BeagleV Ahead dts file.
I am submitting this as an RFC for other people that want to boot
mainline Liunx from the eMMC. There several issues that need to be
addressed in order to claim that MMC fully supported on TH1520:
- Only the MMC controller connected to the eMMC is enabled. I did
not attempt to configure or use the microSD card slot.
- The new th1520 compatible in the sdhci-of-dwcmshc driver turns off
DMA and just uses the inefficient PIO mode, because I did not yet
get into the correct configuration for DMA support.
- The new th1520 compatible in sdhci-of-dwcmshc turns the reset op
into a no-op. The vendor boot loader [3] fully configures the mmc
controller and the phy. The kernel does not yet know how to do that
so it avoids doing a reset. This is essentially a hack and not the
correct way to handle the situation.
Fortunately, Jisheng is the original author of sdhci-of-dwcmshc so I
am sure Jisheng will know many ways in which this can be improved.
NOTE: I combined schema, dts and driver patches into this one series for
the purposes discussing the RFC but that is probably not the correct
structure for a real patch series.
Thanks,
Drew
[1] https://gist.github.com/pdp7/23259595a7570f1f11086d286e16dfb6
[2] https://lore.kernel.org/linux-riscv/20230722-upstream-beaglev-ahead-dts-v2-0-a470ab8fe806@baylibre.com/
[3] https://git.beagleboard.org/beaglev-ahead/beaglev-ahead-u-boot
Signed-off-by: Drew Fustini <[email protected]>
---
Drew Fustini (4):
dt-bindings: mmc: sdhci-of-dwcmhsc: Add T-Head TH1520 compatible
riscv: dts: thead: Add TH1520 mmc controller and sdhci clock
riscv: dts: thead: Enable BeagleV Ahead eMMC controller
mmc: sdhci-of-dwcmshc: Add support for T-Head TH1520
.../bindings/mmc/snps,dwcmshc-sdhci.yaml | 1 +
arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts | 14 ++++++++
arch/riscv/boot/dts/thead/th1520.dtsi | 17 +++++++++
drivers/mmc/host/sdhci-of-dwcmshc.c | 42 ++++++++++++++++++++++
4 files changed, 74 insertions(+)
---
base-commit: cb8c874afdc063290797ae1776a5d410fecb06cb
change-id: 20230724-th1520-emmc-73cde98805d6
Best regards,
--
Drew Fustini <[email protected]>
Add basic support for the T-Head TH1520 SoC mmc controller. The new
compatible "thead,th1520-dwcmshc" enables basic support by:
- Enabling v4 mode to properly communicate with the mmc device
- Setting quirk to disable ADMA
- Setting flag to disable SDMA and force PIO mode
- Turing .reset op into a no-op as the driver does not yet know how to
configure the phy. Rely on the vendor u-boot to have configured the
phy and do not reset the controller in Linux.
Signed-off-by: Drew Fustini <[email protected]>
---
drivers/mmc/host/sdhci-of-dwcmshc.c | 42 +++++++++++++++++++++++++++++++++++++
1 file changed, 42 insertions(+)
diff --git a/drivers/mmc/host/sdhci-of-dwcmshc.c b/drivers/mmc/host/sdhci-of-dwcmshc.c
index e68cd87998c8..8573aff25a81 100644
--- a/drivers/mmc/host/sdhci-of-dwcmshc.c
+++ b/drivers/mmc/host/sdhci-of-dwcmshc.c
@@ -337,6 +337,14 @@ static void rk35xx_sdhci_reset(struct sdhci_host *host, u8 mask)
sdhci_reset(host, mask);
}
+static void th1520_sdhci_reset(struct sdhci_host *host, u8 mask)
+{
+ /*
+ * MMC controller and phy is configured by vendor u-boot so
+ * take the simplistic approach of not doing reset in Linux.
+ */
+}
+
static const struct sdhci_ops sdhci_dwcmshc_ops = {
.set_clock = sdhci_set_clock,
.set_bus_width = sdhci_set_bus_width,
@@ -355,6 +363,15 @@ static const struct sdhci_ops sdhci_dwcmshc_rk35xx_ops = {
.adma_write_desc = dwcmshc_adma_write_desc,
};
+static const struct sdhci_ops sdhci_dwcmshc_th1520_ops = {
+ .set_clock = sdhci_set_clock,
+ .set_bus_width = sdhci_set_bus_width,
+ .set_uhs_signaling = dwcmshc_set_uhs_signaling,
+ .get_max_clock = dwcmshc_get_max_clock,
+ .reset = th1520_sdhci_reset,
+ .adma_write_desc = dwcmshc_adma_write_desc,
+};
+
static const struct sdhci_pltfm_data sdhci_dwcmshc_pdata = {
.ops = &sdhci_dwcmshc_ops,
.quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
@@ -378,6 +395,13 @@ static const struct sdhci_pltfm_data sdhci_dwcmshc_rk35xx_pdata = {
SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN,
};
+static const struct sdhci_pltfm_data sdhci_dwcmshc_th1520_pdata = {
+ .ops = &sdhci_dwcmshc_th1520_ops,
+ .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN | SDHCI_QUIRK_BROKEN_DMA |
+ SDHCI_QUIRK_BROKEN_ADMA,
+ .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
+};
+
static int dwcmshc_rk35xx_init(struct sdhci_host *host, struct dwcmshc_priv *dwc_priv)
{
int err;
@@ -434,6 +458,10 @@ static void dwcmshc_rk35xx_postinit(struct sdhci_host *host, struct dwcmshc_priv
}
static const struct of_device_id sdhci_dwcmshc_dt_ids[] = {
+ {
+ .compatible = "thead,th1520-dwcmshc",
+ .data = &sdhci_dwcmshc_th1520_pdata,
+ },
{
.compatible = "rockchip,rk3588-dwcmshc",
.data = &sdhci_dwcmshc_rk35xx_pdata,
@@ -546,6 +574,20 @@ static int dwcmshc_probe(struct platform_device *pdev)
sdhci_enable_v4_mode(host);
#endif
+ if (pltfm_data == &sdhci_dwcmshc_th1520_pdata) {
+ /*
+ * The controller needs v4 mode enabled to properly
+ * communicate with the mmc device.
+ */
+ sdhci_enable_v4_mode(host);
+
+ /*
+ * Set flag so the SDHCI host core will disable DMA
+ * and use PIO mode.
+ */
+ host->flags &= ~SDHCI_USE_SDMA;
+ }
+
host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY;
err = sdhci_setup_host(host);
--
2.34.1
Add compatible value for the T-Head TH1520 dwcmshc controller.
Signed-off-by: Drew Fustini <[email protected]>
---
Documentation/devicetree/bindings/mmc/snps,dwcmshc-sdhci.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/mmc/snps,dwcmshc-sdhci.yaml b/Documentation/devicetree/bindings/mmc/snps,dwcmshc-sdhci.yaml
index a43eb837f8da..42804d955293 100644
--- a/Documentation/devicetree/bindings/mmc/snps,dwcmshc-sdhci.yaml
+++ b/Documentation/devicetree/bindings/mmc/snps,dwcmshc-sdhci.yaml
@@ -19,6 +19,7 @@ properties:
- rockchip,rk3568-dwcmshc
- rockchip,rk3588-dwcmshc
- snps,dwcmshc-sdhci
+ - thead,th1520-dwcmshc
reg:
maxItems: 1
--
2.34.1
Add nodes for the SDHCI fixed clock and the first mmc controller which
is typically connected to the eMMC device.
Signed-off-by: Drew Fustini <[email protected]>
---
arch/riscv/boot/dts/thead/th1520.dtsi | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi
index 56a73134b49e..b33bfb04c955 100644
--- a/arch/riscv/boot/dts/thead/th1520.dtsi
+++ b/arch/riscv/boot/dts/thead/th1520.dtsi
@@ -134,6 +134,13 @@ uart_sclk: uart-sclk-clock {
#clock-cells = <0>;
};
+ sdhci_clk: sdhci-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <198000000>;
+ clock-output-names = "sdhci_clk";
+ #clock-cells = <0>;
+ };
+
soc {
compatible = "simple-bus";
interrupt-parent = <&plic>;
@@ -291,6 +298,16 @@ dmac0: dma-controller@ffefc00000 {
status = "disabled";
};
+ mmc0: mmc@ffe7080000 {
+ compatible = "thead,th1520-dwcmshc";
+ reg = <0xff 0xe7080000 0x0 0x10000
+ 0xff 0xef014060 0x0 0x4>;
+ interrupts = <62 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "sdhciirq";
+ clocks = <&sdhci_clk>;
+ clock-names = "core";
+ };
+
timer0: timer@ffefc32000 {
compatible = "snps,dw-apb-timer";
reg = <0xff 0xefc32000 0x0 0x14>;
--
2.34.1
Add properties to the emmc node and enable it and set the frequency for
the sdhci clock.
Signed-off-by: Drew Fustini <[email protected]>
---
arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts b/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts
index c315e5bd3d2d..140f5d5c8c97 100644
--- a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts
+++ b/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts
@@ -52,6 +52,10 @@ &uart_sclk {
clock-frequency = <100000000>;
};
+&sdhci_clk {
+ clock-frequency = <198000000>;
+};
+
&dmac0 {
status = "okay";
};
@@ -59,3 +63,13 @@ &dmac0 {
&uart0 {
status = "okay";
};
+
+&mmc0 {
+ max-frequency = <198000000>;
+ non-removable;
+ mmc-hs400-1_8v;
+ no-sdio;
+ no-sd;
+ bus-width = <8>;
+ status = "okay";
+};
--
2.34.1
On 25/07/2023 02:59, Drew Fustini wrote:
> Add compatible value for the T-Head TH1520 dwcmshc controller.
>
> Signed-off-by: Drew Fustini <[email protected]>
> ---
> Documentation/devicetree/bindings/mmc/snps,dwcmshc-sdhci.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
Acked-by: Krzysztof Kozlowski <[email protected]>
Best regards,
Krzysztof
On Mon, Jul 24, 2023 at 05:59:18PM -0700, Drew Fustini wrote:
> Add basic support for the T-Head TH1520 SoC mmc controller. The new
> compatible "thead,th1520-dwcmshc" enables basic support by:
Hi Drew,
>
> - Enabling v4 mode to properly communicate with the mmc device
> - Setting quirk to disable ADMA
> - Setting flag to disable SDMA and force PIO mode
> - Turing .reset op into a no-op as the driver does not yet know how to
> configure the phy. Rely on the vendor u-boot to have configured the
> phy and do not reset the controller in Linux.
The last three itmes are not acceptable. The controller supports ADMA
well, can you plz bring in the phy driver? We can't rely on bootloader to
configure phy.
>
> Signed-off-by: Drew Fustini <[email protected]>
> ---
> drivers/mmc/host/sdhci-of-dwcmshc.c | 42 +++++++++++++++++++++++++++++++++++++
> 1 file changed, 42 insertions(+)
>
> diff --git a/drivers/mmc/host/sdhci-of-dwcmshc.c b/drivers/mmc/host/sdhci-of-dwcmshc.c
> index e68cd87998c8..8573aff25a81 100644
> --- a/drivers/mmc/host/sdhci-of-dwcmshc.c
> +++ b/drivers/mmc/host/sdhci-of-dwcmshc.c
> @@ -337,6 +337,14 @@ static void rk35xx_sdhci_reset(struct sdhci_host *host, u8 mask)
> sdhci_reset(host, mask);
> }
>
> +static void th1520_sdhci_reset(struct sdhci_host *host, u8 mask)
> +{
> + /*
> + * MMC controller and phy is configured by vendor u-boot so
> + * take the simplistic approach of not doing reset in Linux.
> + */
> +}
> +
> static const struct sdhci_ops sdhci_dwcmshc_ops = {
> .set_clock = sdhci_set_clock,
> .set_bus_width = sdhci_set_bus_width,
> @@ -355,6 +363,15 @@ static const struct sdhci_ops sdhci_dwcmshc_rk35xx_ops = {
> .adma_write_desc = dwcmshc_adma_write_desc,
> };
>
> +static const struct sdhci_ops sdhci_dwcmshc_th1520_ops = {
> + .set_clock = sdhci_set_clock,
> + .set_bus_width = sdhci_set_bus_width,
> + .set_uhs_signaling = dwcmshc_set_uhs_signaling,
> + .get_max_clock = dwcmshc_get_max_clock,
> + .reset = th1520_sdhci_reset,
> + .adma_write_desc = dwcmshc_adma_write_desc,
> +};
> +
> static const struct sdhci_pltfm_data sdhci_dwcmshc_pdata = {
> .ops = &sdhci_dwcmshc_ops,
> .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
> @@ -378,6 +395,13 @@ static const struct sdhci_pltfm_data sdhci_dwcmshc_rk35xx_pdata = {
> SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN,
> };
>
> +static const struct sdhci_pltfm_data sdhci_dwcmshc_th1520_pdata = {
> + .ops = &sdhci_dwcmshc_th1520_ops,
> + .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN | SDHCI_QUIRK_BROKEN_DMA |
> + SDHCI_QUIRK_BROKEN_ADMA,
> + .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
> +};
> +
> static int dwcmshc_rk35xx_init(struct sdhci_host *host, struct dwcmshc_priv *dwc_priv)
> {
> int err;
> @@ -434,6 +458,10 @@ static void dwcmshc_rk35xx_postinit(struct sdhci_host *host, struct dwcmshc_priv
> }
>
> static const struct of_device_id sdhci_dwcmshc_dt_ids[] = {
> + {
> + .compatible = "thead,th1520-dwcmshc",
> + .data = &sdhci_dwcmshc_th1520_pdata,
> + },
> {
> .compatible = "rockchip,rk3588-dwcmshc",
> .data = &sdhci_dwcmshc_rk35xx_pdata,
> @@ -546,6 +574,20 @@ static int dwcmshc_probe(struct platform_device *pdev)
> sdhci_enable_v4_mode(host);
> #endif
>
> + if (pltfm_data == &sdhci_dwcmshc_th1520_pdata) {
> + /*
> + * The controller needs v4 mode enabled to properly
> + * communicate with the mmc device.
> + */
> + sdhci_enable_v4_mode(host);
> +
> + /*
> + * Set flag so the SDHCI host core will disable DMA
> + * and use PIO mode.
> + */
> + host->flags &= ~SDHCI_USE_SDMA;
> + }
> +
> host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY;
>
> err = sdhci_setup_host(host);
>
> --
> 2.34.1
>
On Tue, Jul 25, 2023 at 11:03:44PM +0800, Jisheng Zhang wrote:
> On Mon, Jul 24, 2023 at 05:59:18PM -0700, Drew Fustini wrote:
> > Add basic support for the T-Head TH1520 SoC mmc controller. The new
> > compatible "thead,th1520-dwcmshc" enables basic support by:
>
> Hi Drew,
>
> >
> > - Enabling v4 mode to properly communicate with the mmc device
> > - Setting quirk to disable ADMA
> > - Setting flag to disable SDMA and force PIO mode
> > - Turing .reset op into a no-op as the driver does not yet know how to
> > configure the phy. Rely on the vendor u-boot to have configured the
> > phy and do not reset the controller in Linux.
>
> The last three itmes are not acceptable. The controller supports ADMA
> well, can you plz bring in the phy driver? We can't rely on bootloader to
> configure phy.
Yes, that makes sense that this is not acceptable. The T-Head vendor
kernel seems to contain all the necessary information needed to add the
phy configuration to sdhci-of-dwcmshc.
The shipping kernel for the BeagleV Ahead [1] is based on the T-Head SDK
releases. I looked at changes to drivers/mmc and found that key changes
are from Linux_SDK_V0.9.5 [2] and Linux_SDK_V1.0.2 [3].
That kernel contains drivers/mmc/host/sdhci-of-dwcmshc.h [4] which seems
to define information about the phy registers. The version of
drivers/mmc/host/sdhci-of-dwcmshc.h in that kernel defines several
functions for the phy config and controller reset:
sdhci_phy_1_8v_init_no_pull
sdhci_phy_3_3v_init_no_pull
snps_phy_1_8v_init
snps_phy_3_3v_init
snps_sdhci_set_phy
snps_sdhci_reset
I'll look into adapting that code into the upstream sdhci-of-dwcmshc.
Thanks,
Drew
[1] https://git.beagleboard.org/beaglev-ahead/beaglev-ahead-linux
[2] https://gist.github.com/pdp7/8d85d736dea24957c017eefdeb882668
[3] https://gist.github.com/pdp7/c1d3a18f9b7c25e630573d5953a58c99
[4] https://git.beagleboard.org/beaglev-ahead/beaglev-ahead-linux/-/blob/beaglev-v5.10.113-1.1.2/drivers/mmc/host/sdhci-of-dwcmshc.h
[5] https://git.beagleboard.org/beaglev-ahead/beaglev-ahead-linux/-/blob/beaglev-v5.10.113-1.1.2/drivers/mmc/host/sdhci-of-dwcmshc.c