From: Peng Fan <[email protected]>
V2:
Add blank line between property and child node in patch 3
Move compatible in the beginning in patch 8
For patch 9, the pinctrl settings are same, because drive strengh only
has a enable/disable bit.
Add flexspi, cm33, thermal, cpuidle, reserved memory nodes
Enable flexspi, lpi2c7, spi-nor, cm33 for i.MX8ULP-EVK
Set default clock for SDHC
Haibo Chen (3):
arm64: dts: imx8ulp: add flexspi node
arm64: dts: imx8ulp-evk: add 100MHz/200MHz pinctrl setting for eMMC
arm64: dts: imx8ulp-evk: enable lpi2c7 bus
Han Xu (1):
arm64: dts: imx8ulp-evk: add spi-nor device support
Peng Fan (6):
arm64: dts: imx8ulp: add cm33 node
arm64: dts: imx8ulp: set default clock for SDHC
arm64: dts: imx8ulp: add thermal node
arm64: dts: imx8ulp: add cpuidle node
arm64: dts: imx8ulp-evk: add reserved memory for cma
arm64: dts: imx8ulp-evk: enable CM33 node
arch/arm64/boot/dts/freescale/imx8ulp-evk.dts | 145 ++++++++++++++++--
arch/arm64/boot/dts/freescale/imx8ulp.dtsi | 73 ++++++++-
2 files changed, 205 insertions(+), 13 deletions(-)
--
2.37.1
From: Peng Fan <[email protected]>
Add cpuidle node and enable cpuidle for dual cores. The HW mode in
Arm Trusted Firmware is SoC Application Power Domain Sleep mode.
Signed-off-by: Jacky Bai <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
---
arch/arm64/boot/dts/freescale/imx8ulp.dtsi | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
index 8891b4dc3bea..17cbe526a5b0 100644
--- a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
@@ -40,6 +40,7 @@ A35_0: cpu@0 {
reg = <0x0 0x0>;
enable-method = "psci";
next-level-cache = <&A35_L2>;
+ cpu-idle-states = <&cpu_sleep>;
};
A35_1: cpu@1 {
@@ -48,6 +49,7 @@ A35_1: cpu@1 {
reg = <0x0 0x1>;
enable-method = "psci";
next-level-cache = <&A35_L2>;
+ cpu-idle-states = <&cpu_sleep>;
};
A35_L2: l2-cache0 {
@@ -55,6 +57,19 @@ A35_L2: l2-cache0 {
cache-level = <2>;
cache-unified;
};
+
+ idle-states {
+ entry-method = "psci";
+
+ cpu_sleep: cpu-sleep {
+ compatible = "arm,idle-state";
+ arm,psci-suspend-param = <0x0>;
+ local-timer-stop;
+ entry-latency-us = <1000>;
+ exit-latency-us = <700>;
+ min-residency-us = <2700>;
+ };
+ };
};
gic: interrupt-controller@2d400000 {
--
2.37.1
From: Peng Fan <[email protected]>
Enable CM33 node to support rpmsg feature. To use rpmsg, also need
to enable mu node for mailbox doorbell and reserved memory node
for vring, and data buffer. And reserved a piece DRAM memory for case
that m33 images loaded in DRAM.
Signed-off-by: Peng Fan <[email protected]>
---
arch/arm64/boot/dts/freescale/imx8ulp-evk.dts | 50 +++++++++++++++++++
1 file changed, 50 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts b/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts
index e171390a1888..d66e31cf83fe 100644
--- a/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts
@@ -31,6 +31,42 @@ linux,cma {
size = <0 0x28000000>;
linux,cma-default;
};
+
+ m33_reserved: noncacheable-section@a8600000 {
+ reg = <0 0xa8600000 0 0x1000000>;
+ no-map;
+ };
+
+ rsc_table: rsc-table@1fff8000{
+ reg = <0 0x1fff8000 0 0x1000>;
+ no-map;
+ };
+
+ vdev0vring0: vdev0vring0@aff00000 {
+ reg = <0 0xaff00000 0 0x8000>;
+ no-map;
+ };
+
+ vdev0vring1: vdev0vring1@aff08000 {
+ reg = <0 0xaff08000 0 0x8000>;
+ no-map;
+ };
+
+ vdev1vring0: vdev1vring0@aff10000 {
+ reg = <0 0xaff10000 0 0x8000>;
+ no-map;
+ };
+
+ vdev1vring1: vdev1vring1@aff18000 {
+ reg = <0 0xaff18000 0 0x8000>;
+ no-map;
+ };
+
+ vdevbuffer: vdevbuffer@a8400000 {
+ compatible = "shared-dma-pool";
+ reg = <0 0xa8400000 0 0x100000>;
+ no-map;
+ };
};
clock_ext_rmii: clock-ext-rmii {
@@ -49,6 +85,16 @@ clock_ext_ts: clock-ext-ts {
};
};
+&cm33 {
+ mbox-names = "tx", "rx", "rxdb";
+ mboxes = <&mu 0 1>,
+ <&mu 1 1>,
+ <&mu 3 1>;
+ memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>,
+ <&vdev1vring0>, <&vdev1vring1>, <&rsc_table>;
+ status = "okay";
+};
+
&lpuart5 {
/* console */
pinctrl-names = "default", "sleep";
@@ -92,6 +138,10 @@ ethphy: ethernet-phy@1 {
};
};
+&mu {
+ status = "okay";
+};
+
&iomuxc1 {
pinctrl_enet: enetgrp {
fsl,pins = <
--
2.37.1
On Mon, Jul 24, 2023 at 03:58:23PM +0800, Peng Fan (OSS) wrote:
> From: Peng Fan <[email protected]>
>
> V2:
> Add blank line between property and child node in patch 3
> Move compatible in the beginning in patch 8
> For patch 9, the pinctrl settings are same, because drive strengh only
> has a enable/disable bit.
>
> Add flexspi, cm33, thermal, cpuidle, reserved memory nodes
> Enable flexspi, lpi2c7, spi-nor, cm33 for i.MX8ULP-EVK
> Set default clock for SDHC
>
> Haibo Chen (3):
> arm64: dts: imx8ulp: add flexspi node
> arm64: dts: imx8ulp-evk: add 100MHz/200MHz pinctrl setting for eMMC
> arm64: dts: imx8ulp-evk: enable lpi2c7 bus
>
> Han Xu (1):
> arm64: dts: imx8ulp-evk: add spi-nor device support
>
> Peng Fan (6):
> arm64: dts: imx8ulp: add cm33 node
> arm64: dts: imx8ulp: set default clock for SDHC
> arm64: dts: imx8ulp: add thermal node
> arm64: dts: imx8ulp: add cpuidle node
> arm64: dts: imx8ulp-evk: add reserved memory for cma
> arm64: dts: imx8ulp-evk: enable CM33 node
Applied all, thanks!