This patch series does the following -
* Refactor LLCC driver to support multiple configuration
* Add stub function for nvmem_cell_read_u8
* Add support for multi channel DDR configuration in LLCC
* Add LLCC support for the Qualcomm QDU1000 and QRU1000 SoCs
Changes in v6 -
- Changed variable name from num_cfgs to num_config as suggested by Mukesh.
- Added a check for default llcc configuration as per suggestion from Mukesh.
- Updated the commit summary for the third and fifth patch.
- Fixed alignment in the fourth patch.
- Used ARRAY_SIZE() to calculate the num_config as per suggested by Konrad.
Changes in v5 -
- Seperated out the secure qfprom driver changes to a separate series [1].
- Created a wrapper struct with a pointer to qcom_llcc_config and
length of array qcom_llcc_config.
- Added stub function for nvmem_cell_read_u8.
- Split commit 6/6 in the previous series into two commits.
Changes in v4 -
- Created a separate driver for reading from secure fuse region as suggested.
- Added patch for dt-bindings of secure qfprom driver accordingly.
- Added new properties in the dt-bindings for LLCC.
- Implemented new logic to read the nvmem cell as suggested by Bjorn.
- Separating the DT patches from this series as per suggestion.
Changes in v3-
- Addressed comments from Krzysztof and Mani.
- Using qfprom to read DDR configuration from feature register.
Changes in v2:
- Addressing comments from Konrad.
[1] https://lore.kernel.org/linux-arm-msm/[email protected]/
Komal Bajaj (6):
dt-bindings: cache: qcom,llcc: Add LLCC compatible for QDU1000/QRU1000
soc: qcom: llcc: Refactor llcc driver to support multiple
configuration
nvmem: core: Add stub for nvmem_cell_read_u8
soc: qcom: Add LLCC support for multi channel DDR
soc: qcom: llcc: Updating the macro name
soc: qcom: llcc: Add QDU1000 and QRU1000 LLCC support
.../devicetree/bindings/cache/qcom,llcc.yaml | 10 +
drivers/soc/qcom/llcc-qcom.c | 357 +++++++++++++-----
include/linux/nvmem-consumer.h | 6 +
include/linux/soc/qcom/llcc-qcom.h | 2 +-
4 files changed, 287 insertions(+), 88 deletions(-)
--
2.41.0
Refactor driver to support multiple configuration for llcc on a target.
Signed-off-by: Komal Bajaj <[email protected]>
---
drivers/soc/qcom/llcc-qcom.c | 270 ++++++++++++++++++++++++-----------
1 file changed, 184 insertions(+), 86 deletions(-)
diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c
index 67c19ed2219a..808c5aaa7407 100644
--- a/drivers/soc/qcom/llcc-qcom.c
+++ b/drivers/soc/qcom/llcc-qcom.c
@@ -66,6 +66,8 @@
#define LLCC_VERSION_2_1_0_0 0x02010000
#define LLCC_VERSION_4_1_0_0 0x04010000
+#define DEFAULT_CONFIG 1
+
/**
* struct llcc_slice_config - Data associated with the llcc slice
* @usecase_id: Unique id for the client's use case
@@ -127,6 +129,12 @@ struct qcom_llcc_config {
bool no_edac;
};
+struct qcom_sct_config {
+ const struct qcom_llcc_config *llcc_config;
+ int num_config;
+};
+
+
enum llcc_reg_offset {
LLCC_COMMON_HW_INFO,
LLCC_COMMON_STATUS0,
@@ -423,101 +431,185 @@ static const u32 llcc_v2_1_reg_offset[] = {
[LLCC_COMMON_STATUS0] = 0x0003400c,
};
-static const struct qcom_llcc_config sc7180_cfg = {
- .sct_data = sc7180_data,
- .size = ARRAY_SIZE(sc7180_data),
- .need_llcc_cfg = true,
- .reg_offset = llcc_v1_reg_offset,
- .edac_reg_offset = &llcc_v1_edac_reg_offset,
+static const struct qcom_llcc_config sc7180_cfg[] = {
+ {
+ .sct_data = sc7180_data,
+ .size = ARRAY_SIZE(sc7180_data),
+ .need_llcc_cfg = true,
+ .reg_offset = llcc_v1_reg_offset,
+ .edac_reg_offset = &llcc_v1_edac_reg_offset,
+ },
+};
+
+static const struct qcom_llcc_config sc7280_cfg[] = {
+ {
+ .sct_data = sc7280_data,
+ .size = ARRAY_SIZE(sc7280_data),
+ .need_llcc_cfg = true,
+ .reg_offset = llcc_v1_reg_offset,
+ .edac_reg_offset = &llcc_v1_edac_reg_offset,
+ },
+};
+
+static const struct qcom_llcc_config sc8180x_cfg[] = {
+ {
+ .sct_data = sc8180x_data,
+ .size = ARRAY_SIZE(sc8180x_data),
+ .need_llcc_cfg = true,
+ .reg_offset = llcc_v1_reg_offset,
+ .edac_reg_offset = &llcc_v1_edac_reg_offset,
+ },
+};
+
+static const struct qcom_llcc_config sc8280xp_cfg[] = {
+ {
+ .sct_data = sc8280xp_data,
+ .size = ARRAY_SIZE(sc8280xp_data),
+ .need_llcc_cfg = true,
+ .reg_offset = llcc_v1_reg_offset,
+ .edac_reg_offset = &llcc_v1_edac_reg_offset,
+ },
+};
+
+static const struct qcom_llcc_config sdm845_cfg[] = {
+ {
+ .sct_data = sdm845_data,
+ .size = ARRAY_SIZE(sdm845_data),
+ .need_llcc_cfg = false,
+ .reg_offset = llcc_v1_reg_offset,
+ .edac_reg_offset = &llcc_v1_edac_reg_offset,
+ .no_edac = true,
+ },
+};
+
+static const struct qcom_llcc_config sm6350_cfg[] = {
+ {
+ .sct_data = sm6350_data,
+ .size = ARRAY_SIZE(sm6350_data),
+ .need_llcc_cfg = true,
+ .reg_offset = llcc_v1_reg_offset,
+ .edac_reg_offset = &llcc_v1_edac_reg_offset,
+ },
+};
+
+static const struct qcom_llcc_config sm7150_cfg[] = {
+ {
+ .sct_data = sm7150_data,
+ .size = ARRAY_SIZE(sm7150_data),
+ .need_llcc_cfg = true,
+ .reg_offset = llcc_v1_reg_offset,
+ .edac_reg_offset = &llcc_v1_edac_reg_offset,
+ },
};
-static const struct qcom_llcc_config sc7280_cfg = {
- .sct_data = sc7280_data,
- .size = ARRAY_SIZE(sc7280_data),
- .need_llcc_cfg = true,
- .reg_offset = llcc_v1_reg_offset,
- .edac_reg_offset = &llcc_v1_edac_reg_offset,
+static const struct qcom_llcc_config sm8150_cfg[] = {
+ {
+ .sct_data = sm8150_data,
+ .size = ARRAY_SIZE(sm8150_data),
+ .need_llcc_cfg = true,
+ .reg_offset = llcc_v1_reg_offset,
+ .edac_reg_offset = &llcc_v1_edac_reg_offset,
+ },
};
-static const struct qcom_llcc_config sc8180x_cfg = {
- .sct_data = sc8180x_data,
- .size = ARRAY_SIZE(sc8180x_data),
- .need_llcc_cfg = true,
- .reg_offset = llcc_v1_reg_offset,
- .edac_reg_offset = &llcc_v1_edac_reg_offset,
+static const struct qcom_llcc_config sm8250_cfg[] = {
+ {
+ .sct_data = sm8250_data,
+ .size = ARRAY_SIZE(sm8250_data),
+ .need_llcc_cfg = true,
+ .reg_offset = llcc_v1_reg_offset,
+ .edac_reg_offset = &llcc_v1_edac_reg_offset,
+ },
};
-static const struct qcom_llcc_config sc8280xp_cfg = {
- .sct_data = sc8280xp_data,
- .size = ARRAY_SIZE(sc8280xp_data),
- .need_llcc_cfg = true,
- .reg_offset = llcc_v1_reg_offset,
- .edac_reg_offset = &llcc_v1_edac_reg_offset,
+static const struct qcom_llcc_config sm8350_cfg[] = {
+ {
+ .sct_data = sm8350_data,
+ .size = ARRAY_SIZE(sm8350_data),
+ .need_llcc_cfg = true,
+ .reg_offset = llcc_v1_reg_offset,
+ .edac_reg_offset = &llcc_v1_edac_reg_offset,
+ },
+};
+
+static const struct qcom_llcc_config sm8450_cfg[] = {
+ {
+ .sct_data = sm8450_data,
+ .size = ARRAY_SIZE(sm8450_data),
+ .need_llcc_cfg = true,
+ .reg_offset = llcc_v2_1_reg_offset,
+ .edac_reg_offset = &llcc_v2_1_edac_reg_offset,
+ },
+};
+
+static const struct qcom_llcc_config sm8550_cfg[] = {
+ {
+ .sct_data = sm8550_data,
+ .size = ARRAY_SIZE(sm8550_data),
+ .need_llcc_cfg = true,
+ .reg_offset = llcc_v2_1_reg_offset,
+ .edac_reg_offset = &llcc_v2_1_edac_reg_offset,
+ },
};
-static const struct qcom_llcc_config sdm845_cfg = {
- .sct_data = sdm845_data,
- .size = ARRAY_SIZE(sdm845_data),
- .need_llcc_cfg = false,
- .reg_offset = llcc_v1_reg_offset,
- .edac_reg_offset = &llcc_v1_edac_reg_offset,
- .no_edac = true,
+static const struct qcom_sct_config sc7180_cfgs = {
+ .llcc_config = sc7180_cfg,
+ .num_config = ARRAY_SIZE(sc7180_cfg),
};
-static const struct qcom_llcc_config sm6350_cfg = {
- .sct_data = sm6350_data,
- .size = ARRAY_SIZE(sm6350_data),
- .need_llcc_cfg = true,
- .reg_offset = llcc_v1_reg_offset,
- .edac_reg_offset = &llcc_v1_edac_reg_offset,
+static const struct qcom_sct_config sc7280_cfgs = {
+ .llcc_config = sc7280_cfg,
+ .num_config = ARRAY_SIZE(sc7280_cfg),
};
-static const struct qcom_llcc_config sm7150_cfg = {
- .sct_data = sm7150_data,
- .size = ARRAY_SIZE(sm7150_data),
- .need_llcc_cfg = true,
- .reg_offset = llcc_v1_reg_offset,
- .edac_reg_offset = &llcc_v1_edac_reg_offset,
+static const struct qcom_sct_config sc8180x_cfgs = {
+ .llcc_config = sc8180x_cfg,
+ .num_config = ARRAY_SIZE(sc8180x_cfg),
};
-static const struct qcom_llcc_config sm8150_cfg = {
- .sct_data = sm8150_data,
- .size = ARRAY_SIZE(sm8150_data),
- .need_llcc_cfg = true,
- .reg_offset = llcc_v1_reg_offset,
- .edac_reg_offset = &llcc_v1_edac_reg_offset,
+static const struct qcom_sct_config sc8280xp_cfgs = {
+ .llcc_config = sc8280xp_cfg,
+ .num_config = ARRAY_SIZE(sc8280xp_cfg),
};
-static const struct qcom_llcc_config sm8250_cfg = {
- .sct_data = sm8250_data,
- .size = ARRAY_SIZE(sm8250_data),
- .need_llcc_cfg = true,
- .reg_offset = llcc_v1_reg_offset,
- .edac_reg_offset = &llcc_v1_edac_reg_offset,
+static const struct qcom_sct_config sdm845_cfgs = {
+ .llcc_config = sdm845_cfg,
+ .num_config = ARRAY_SIZE(sdm845_cfg),
};
-static const struct qcom_llcc_config sm8350_cfg = {
- .sct_data = sm8350_data,
- .size = ARRAY_SIZE(sm8350_data),
- .need_llcc_cfg = true,
- .reg_offset = llcc_v1_reg_offset,
- .edac_reg_offset = &llcc_v1_edac_reg_offset,
+static const struct qcom_sct_config sm6350_cfgs = {
+ .llcc_config = sm6350_cfg,
+ .num_config = ARRAY_SIZE(sm6350_cfg),
};
-static const struct qcom_llcc_config sm8450_cfg = {
- .sct_data = sm8450_data,
- .size = ARRAY_SIZE(sm8450_data),
- .need_llcc_cfg = true,
- .reg_offset = llcc_v2_1_reg_offset,
- .edac_reg_offset = &llcc_v2_1_edac_reg_offset,
+static const struct qcom_sct_config sm7150_cfgs = {
+ .llcc_config = sm7150_cfg,
+ .num_config = ARRAY_SIZE(sm7150_cfg),
};
-static const struct qcom_llcc_config sm8550_cfg = {
- .sct_data = sm8550_data,
- .size = ARRAY_SIZE(sm8550_data),
- .need_llcc_cfg = true,
- .reg_offset = llcc_v2_1_reg_offset,
- .edac_reg_offset = &llcc_v2_1_edac_reg_offset,
+static const struct qcom_sct_config sm8150_cfgs = {
+ .llcc_config = sm8150_cfg,
+ .num_config = ARRAY_SIZE(sm8150_cfg),
+};
+
+static const struct qcom_sct_config sm8250_cfgs = {
+ .llcc_config = sm8250_cfg,
+ .num_config = ARRAY_SIZE(sm8250_cfg),
+};
+
+static const struct qcom_sct_config sm8350_cfgs = {
+ .llcc_config = sm8350_cfg,
+ .num_config = ARRAY_SIZE(sm8350_cfg),
+};
+
+static const struct qcom_sct_config sm8450_cfgs = {
+ .llcc_config = sm8450_cfg,
+ .num_config = ARRAY_SIZE(sm8450_cfg),
+};
+
+static const struct qcom_sct_config sm8550_cfgs = {
+ .llcc_config = sm8550_cfg,
+ .num_config = ARRAY_SIZE(sm8550_cfg),
};
static struct llcc_drv_data *drv_data = (void *) -EPROBE_DEFER;
@@ -939,6 +1031,7 @@ static int qcom_llcc_probe(struct platform_device *pdev)
struct device *dev = &pdev->dev;
int ret, i;
struct platform_device *llcc_edac;
+ const struct qcom_sct_config *cfgs;
const struct qcom_llcc_config *cfg;
const struct llcc_slice_config *llcc_cfg;
u32 sz;
@@ -958,7 +1051,12 @@ static int qcom_llcc_probe(struct platform_device *pdev)
goto err;
}
- cfg = of_device_get_match_data(&pdev->dev);
+ cfgs = of_device_get_match_data(&pdev->dev);
+ if (cfgs->num_config != DEFAULT_CONFIG) {
+ ret = -EINVAL;
+ goto err;
+ }
+ cfg = &cfgs->llcc_config[DEFAULT_CONFIG - 1];
ret = regmap_read(regmap, cfg->reg_offset[LLCC_COMMON_STATUS0], &num_banks);
if (ret)
@@ -1051,18 +1149,18 @@ static int qcom_llcc_probe(struct platform_device *pdev)
}
static const struct of_device_id qcom_llcc_of_match[] = {
- { .compatible = "qcom,sc7180-llcc", .data = &sc7180_cfg },
- { .compatible = "qcom,sc7280-llcc", .data = &sc7280_cfg },
- { .compatible = "qcom,sc8180x-llcc", .data = &sc8180x_cfg },
- { .compatible = "qcom,sc8280xp-llcc", .data = &sc8280xp_cfg },
- { .compatible = "qcom,sdm845-llcc", .data = &sdm845_cfg },
- { .compatible = "qcom,sm6350-llcc", .data = &sm6350_cfg },
- { .compatible = "qcom,sm7150-llcc", .data = &sm7150_cfg },
- { .compatible = "qcom,sm8150-llcc", .data = &sm8150_cfg },
- { .compatible = "qcom,sm8250-llcc", .data = &sm8250_cfg },
- { .compatible = "qcom,sm8350-llcc", .data = &sm8350_cfg },
- { .compatible = "qcom,sm8450-llcc", .data = &sm8450_cfg },
- { .compatible = "qcom,sm8550-llcc", .data = &sm8550_cfg },
+ { .compatible = "qcom,sc7180-llcc", .data = &sc7180_cfgs },
+ { .compatible = "qcom,sc7280-llcc", .data = &sc7280_cfgs },
+ { .compatible = "qcom,sc8180x-llcc", .data = &sc8180x_cfgs },
+ { .compatible = "qcom,sc8280xp-llcc", .data = &sc8280xp_cfgs },
+ { .compatible = "qcom,sdm845-llcc", .data = &sdm845_cfgs },
+ { .compatible = "qcom,sm6350-llcc", .data = &sm6350_cfgs },
+ { .compatible = "qcom,sm7150-llcc", .data = &sm7150_cfgs },
+ { .compatible = "qcom,sm8150-llcc", .data = &sm8150_cfgs },
+ { .compatible = "qcom,sm8250-llcc", .data = &sm8250_cfgs },
+ { .compatible = "qcom,sm8350-llcc", .data = &sm8350_cfgs },
+ { .compatible = "qcom,sm8450-llcc", .data = &sm8450_cfgs },
+ { .compatible = "qcom,sm8550-llcc", .data = &sm8550_cfgs },
{ }
};
MODULE_DEVICE_TABLE(of, qcom_llcc_of_match);
--
2.41.0
Add the stub nvmem_cell_read_u8() function for drivers running with
CONFIG_NVMEM disabled.
Signed-off-by: Komal Bajaj <[email protected]>
---
include/linux/nvmem-consumer.h | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/include/linux/nvmem-consumer.h b/include/linux/nvmem-consumer.h
index fa030d93b768..5c88635d4c2b 100644
--- a/include/linux/nvmem-consumer.h
+++ b/include/linux/nvmem-consumer.h
@@ -125,6 +125,12 @@ static inline int nvmem_cell_write(struct nvmem_cell *cell,
return -EOPNOTSUPP;
}
+static inline int nvmem_cell_read_u8(struct device *dev,
+ const char *cell_id, u8 *val)
+{
+ return -EOPNOTSUPP;
+}
+
static inline int nvmem_cell_read_u16(struct device *dev,
const char *cell_id, u16 *val)
{
--
2.41.0
Update macro name for LLCC_DRE to LLCC_ECC as per the latest specification.
Signed-off-by: Komal Bajaj <[email protected]>
Reviewed-by: Mukesh Ojha <[email protected]>
Acked-by: Konrad Dybcio <[email protected]>
---
drivers/soc/qcom/llcc-qcom.c | 2 +-
include/linux/soc/qcom/llcc-qcom.h | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c
index f6ed4e4aaf3b..315f7a1b90aa 100644
--- a/drivers/soc/qcom/llcc-qcom.c
+++ b/drivers/soc/qcom/llcc-qcom.c
@@ -195,7 +195,7 @@ static const struct llcc_slice_config sc8280xp_data[] = {
{ LLCC_MMUHWT, 13, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 },
{ LLCC_DISP, 16, 6144, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
{ LLCC_AUDHW, 22, 2048, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
- { LLCC_DRE, 26, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
+ { LLCC_ECC, 26, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
{ LLCC_CVP, 28, 512, 3, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
{ LLCC_APTCM, 30, 1024, 3, 1, 0x0, 0x1, 1, 0, 0, 1, 0, 0 },
{ LLCC_WRCACHE, 31, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 },
diff --git a/include/linux/soc/qcom/llcc-qcom.h b/include/linux/soc/qcom/llcc-qcom.h
index 93417ba1ead4..1a886666bbb6 100644
--- a/include/linux/soc/qcom/llcc-qcom.h
+++ b/include/linux/soc/qcom/llcc-qcom.h
@@ -30,7 +30,7 @@
#define LLCC_NPU 23
#define LLCC_WLHW 24
#define LLCC_PIMEM 25
-#define LLCC_DRE 26
+#define LLCC_ECC 26
#define LLCC_CVP 28
#define LLCC_MODPE 29
#define LLCC_APTCM 30
--
2.41.0
Add LLCC support for multi channel DDR configuration
based on a feature register.
Signed-off-by: Komal Bajaj <[email protected]>
---
drivers/soc/qcom/llcc-qcom.c | 30 ++++++++++++++++++++++++++----
1 file changed, 26 insertions(+), 4 deletions(-)
diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c
index 808c5aaa7407..f6ed4e4aaf3b 100644
--- a/drivers/soc/qcom/llcc-qcom.c
+++ b/drivers/soc/qcom/llcc-qcom.c
@@ -12,6 +12,7 @@
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/mutex.h>
+#include <linux/nvmem-consumer.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/regmap.h>
@@ -999,6 +1000,26 @@ static int qcom_llcc_cfg_program(struct platform_device *pdev,
return ret;
}
+static int qcom_llcc_get_cfg_index(struct platform_device *pdev, u8 *cfg_index, int num_config)
+{
+ int ret;
+
+ ret = nvmem_cell_read_u8(&pdev->dev, "multi-chan-ddr", cfg_index);
+ if (ret == -ENOENT || ret == -EOPNOTSUPP) {
+ if (num_config != DEFAULT_CONFIG) {
+ ret = -EINVAL;
+ return ret;
+ }
+ *cfg_index = DEFAULT_CONFIG - 1;
+ return 0;
+ }
+
+ if (!ret && *cfg_index >= num_config)
+ ret = -EINVAL;
+
+ return ret;
+}
+
static int qcom_llcc_remove(struct platform_device *pdev)
{
/* Set the global pointer to a error code to avoid referencing it */
@@ -1035,6 +1056,7 @@ static int qcom_llcc_probe(struct platform_device *pdev)
const struct qcom_llcc_config *cfg;
const struct llcc_slice_config *llcc_cfg;
u32 sz;
+ u8 cfg_index;
u32 version;
struct regmap *regmap;
@@ -1052,11 +1074,11 @@ static int qcom_llcc_probe(struct platform_device *pdev)
}
cfgs = of_device_get_match_data(&pdev->dev);
- if (cfgs->num_config != DEFAULT_CONFIG) {
- ret = -EINVAL;
+ ret = qcom_llcc_get_cfg_index(pdev, &cfg_index, cfgs->num_config);
+ if (ret)
goto err;
- }
- cfg = &cfgs->llcc_config[DEFAULT_CONFIG - 1];
+
+ cfg = &cfgs->llcc_config[cfg_index];
ret = regmap_read(regmap, cfg->reg_offset[LLCC_COMMON_STATUS0], &num_banks);
if (ret)
--
2.41.0
Add LLCC configuration data for QDU1000 and QRU1000 SoCs.
Signed-off-by: Komal Bajaj <[email protected]>
---
drivers/soc/qcom/llcc-qcom.c | 67 ++++++++++++++++++++++++++++++++++++
1 file changed, 67 insertions(+)
diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c
index 315f7a1b90aa..8e1b2399700d 100644
--- a/drivers/soc/qcom/llcc-qcom.c
+++ b/drivers/soc/qcom/llcc-qcom.c
@@ -366,6 +366,36 @@ static const struct llcc_slice_config sm8550_data[] = {
{LLCC_VIDVSP, 28, 256, 4, 1, 0xFFFFFF, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
};
+static const struct llcc_slice_config qdu1000_data_2ch[] = {
+ { LLCC_MDMHPGRW, 7, 512, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0, 0 },
+ { LLCC_MODHW, 9, 256, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0, 0 },
+ { LLCC_MDMPNG, 21, 256, 0, 1, 0x3, 0x0, 0, 0, 0, 1, 0, 0, 0 },
+ { LLCC_ECC, 26, 512, 3, 1, 0xffc, 0x0, 0, 0, 0, 0, 1, 0, 0 },
+ { LLCC_MODPE, 29, 256, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0, 0 },
+ { LLCC_APTCM, 30, 256, 3, 1, 0x0, 0xc, 1, 0, 0, 1, 0, 0, 0 },
+ { LLCC_WRCACHE, 31, 128, 1, 1, 0x3, 0x0, 0, 0, 0, 0, 1, 0, 0 },
+};
+
+static const struct llcc_slice_config qdu1000_data_4ch[] = {
+ { LLCC_MDMHPGRW, 7, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0, 0 },
+ { LLCC_MODHW, 9, 512, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0, 0 },
+ { LLCC_MDMPNG, 21, 512, 0, 1, 0x3, 0x0, 0, 0, 0, 1, 0, 0, 0 },
+ { LLCC_ECC, 26, 1024, 3, 1, 0xffc, 0x0, 0, 0, 0, 0, 1, 0, 0 },
+ { LLCC_MODPE, 29, 512, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0, 0 },
+ { LLCC_APTCM, 30, 512, 3, 1, 0x0, 0xc, 1, 0, 0, 1, 0, 0, 0 },
+ { LLCC_WRCACHE, 31, 256, 1, 1, 0x3, 0x0, 0, 0, 0, 0, 1, 0, 0 },
+};
+
+static const struct llcc_slice_config qdu1000_data_8ch[] = {
+ { LLCC_MDMHPGRW, 7, 2048, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0, 0 },
+ { LLCC_MODHW, 9, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0, 0 },
+ { LLCC_MDMPNG, 21, 1024, 0, 1, 0x3, 0x0, 0, 0, 0, 1, 0, 0, 0 },
+ { LLCC_ECC, 26, 2048, 3, 1, 0xffc, 0x0, 0, 0, 0, 0, 1, 0, 0 },
+ { LLCC_MODPE, 29, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0, 0 },
+ { LLCC_APTCM, 30, 1024, 3, 1, 0x0, 0xc, 1, 0, 0, 1, 0, 0, 0 },
+ { LLCC_WRCACHE, 31, 512, 1, 1, 0x3, 0x0, 0, 0, 0, 0, 1, 0, 0 },
+};
+
static const struct llcc_edac_reg_offset llcc_v1_edac_reg_offset = {
.trp_ecc_error_status0 = 0x20344,
.trp_ecc_error_status1 = 0x20348,
@@ -432,6 +462,37 @@ static const u32 llcc_v2_1_reg_offset[] = {
[LLCC_COMMON_STATUS0] = 0x0003400c,
};
+static const struct qcom_llcc_config qdu1000_cfg[] = {
+ {
+ .sct_data = qdu1000_data_8ch,
+ .size = ARRAY_SIZE(qdu1000_data_8ch),
+ .need_llcc_cfg = true,
+ .reg_offset = llcc_v2_1_reg_offset,
+ .edac_reg_offset = &llcc_v2_1_edac_reg_offset,
+ },
+ {
+ .sct_data = qdu1000_data_4ch,
+ .size = ARRAY_SIZE(qdu1000_data_4ch),
+ .need_llcc_cfg = true,
+ .reg_offset = llcc_v2_1_reg_offset,
+ .edac_reg_offset = &llcc_v2_1_edac_reg_offset,
+ },
+ {
+ .sct_data = qdu1000_data_4ch,
+ .size = ARRAY_SIZE(qdu1000_data_4ch),
+ .need_llcc_cfg = true,
+ .reg_offset = llcc_v2_1_reg_offset,
+ .edac_reg_offset = &llcc_v2_1_edac_reg_offset,
+ },
+ {
+ .sct_data = qdu1000_data_2ch,
+ .size = ARRAY_SIZE(qdu1000_data_2ch),
+ .need_llcc_cfg = true,
+ .reg_offset = llcc_v2_1_reg_offset,
+ .edac_reg_offset = &llcc_v2_1_edac_reg_offset,
+ },
+};
+
static const struct qcom_llcc_config sc7180_cfg[] = {
{
.sct_data = sc7180_data,
@@ -553,6 +614,11 @@ static const struct qcom_llcc_config sm8550_cfg[] = {
},
};
+static const struct qcom_sct_config qdu1000_cfgs = {
+ .llcc_config = qdu1000_cfg,
+ .num_config = 4,
+};
+
static const struct qcom_sct_config sc7180_cfgs = {
.llcc_config = sc7180_cfg,
.num_config = ARRAY_SIZE(sc7180_cfg),
@@ -1171,6 +1237,7 @@ static int qcom_llcc_probe(struct platform_device *pdev)
}
static const struct of_device_id qcom_llcc_of_match[] = {
+ { .compatible = "qcom,qdu1000-llcc", .data = &qdu1000_cfgs},
{ .compatible = "qcom,sc7180-llcc", .data = &sc7180_cfgs },
{ .compatible = "qcom,sc7280-llcc", .data = &sc7280_cfgs },
{ .compatible = "qcom,sc8180x-llcc", .data = &sc8180x_cfgs },
--
2.41.0
Add LLCC compatible for QDU1000/QRU1000 SoCs and add optional
nvmem-cells and nvmem-cell-names properties to support multiple
configurations for multi channel DDR.
Signed-off-by: Komal Bajaj <[email protected]>
Reviewed-by: Krzysztof Kozlowski <[email protected]>
---
Documentation/devicetree/bindings/cache/qcom,llcc.yaml | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/Documentation/devicetree/bindings/cache/qcom,llcc.yaml b/Documentation/devicetree/bindings/cache/qcom,llcc.yaml
index 44892aa589fd..580f9a97ddf7 100644
--- a/Documentation/devicetree/bindings/cache/qcom,llcc.yaml
+++ b/Documentation/devicetree/bindings/cache/qcom,llcc.yaml
@@ -20,6 +20,7 @@ description: |
properties:
compatible:
enum:
+ - qcom,qdu1000-llcc
- qcom,sc7180-llcc
- qcom,sc7280-llcc
- qcom,sc8180x-llcc
@@ -44,6 +45,14 @@ properties:
interrupts:
maxItems: 1
+ nvmem-cells:
+ items:
+ - description: Reference to an nvmem node for multi channel DDR
+
+ nvmem-cell-names:
+ items:
+ - const: multi-chan-ddr
+
required:
- compatible
- reg
@@ -92,6 +101,7 @@ allOf:
compatible:
contains:
enum:
+ - qcom,qdu1000-llcc
- qcom,sc8180x-llcc
- qcom,sc8280xp-llcc
then:
--
2.41.0
On 8/2/2023 2:44 PM, Komal Bajaj wrote:
> Refactor driver to support multiple configuration for llcc on a target.
>
> Signed-off-by: Komal Bajaj <[email protected]>
> ---
> drivers/soc/qcom/llcc-qcom.c | 270 ++++++++++++++++++++++++-----------
> 1 file changed, 184 insertions(+), 86 deletions(-)
>
> diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c
> index 67c19ed2219a..808c5aaa7407 100644
> --- a/drivers/soc/qcom/llcc-qcom.c
> +++ b/drivers/soc/qcom/llcc-qcom.c
> @@ -66,6 +66,8 @@
> #define LLCC_VERSION_2_1_0_0 0x02010000
> #define LLCC_VERSION_4_1_0_0 0x04010000
>
> +#define DEFAULT_CONFIG 1
Could it be DEF_NUM_CFG ?
> +
> /**
> * struct llcc_slice_config - Data associated with the llcc slice
> * @usecase_id: Unique id for the client's use case
> @@ -127,6 +129,12 @@ struct qcom_llcc_config {
> bool no_edac;
> };
>
> +struct qcom_sct_config {
> + const struct qcom_llcc_config *llcc_config;
> + int num_config;
> +};
> +
> +
Extra line..
> enum llcc_reg_offset {
> LLCC_COMMON_HW_INFO,
> LLCC_COMMON_STATUS0,
> @@ -423,101 +431,185 @@ static const u32 llcc_v2_1_reg_offset[] = {
> [LLCC_COMMON_STATUS0] = 0x0003400c,
> };
>
> -static const struct qcom_llcc_config sc7180_cfg = {
> - .sct_data = sc7180_data,
> - .size = ARRAY_SIZE(sc7180_data),
> - .need_llcc_cfg = true,
> - .reg_offset = llcc_v1_reg_offset,
> - .edac_reg_offset = &llcc_v1_edac_reg_offset,
> +static const struct qcom_llcc_config sc7180_cfg[] = {
> + {
> + .sct_data = sc7180_data,
> + .size = ARRAY_SIZE(sc7180_data),
> + .need_llcc_cfg = true,
> + .reg_offset = llcc_v1_reg_offset,
> + .edac_reg_offset = &llcc_v1_edac_reg_offset,
> + },
> +};
> +
> +static const struct qcom_llcc_config sc7280_cfg[] = {
> + {
> + .sct_data = sc7280_data,
> + .size = ARRAY_SIZE(sc7280_data),
> + .need_llcc_cfg = true,
> + .reg_offset = llcc_v1_reg_offset,
> + .edac_reg_offset = &llcc_v1_edac_reg_offset,
> + },
> +};
> +
> +static const struct qcom_llcc_config sc8180x_cfg[] = {
> + {
> + .sct_data = sc8180x_data,
> + .size = ARRAY_SIZE(sc8180x_data),
> + .need_llcc_cfg = true,
> + .reg_offset = llcc_v1_reg_offset,
> + .edac_reg_offset = &llcc_v1_edac_reg_offset,
> + },
> +};
> +
> +static const struct qcom_llcc_config sc8280xp_cfg[] = {
> + {
> + .sct_data = sc8280xp_data,
> + .size = ARRAY_SIZE(sc8280xp_data),
> + .need_llcc_cfg = true,
> + .reg_offset = llcc_v1_reg_offset,
> + .edac_reg_offset = &llcc_v1_edac_reg_offset,
> + },
> +};
> +
> +static const struct qcom_llcc_config sdm845_cfg[] = {
> + {
> + .sct_data = sdm845_data,
> + .size = ARRAY_SIZE(sdm845_data),
> + .need_llcc_cfg = false,
> + .reg_offset = llcc_v1_reg_offset,
> + .edac_reg_offset = &llcc_v1_edac_reg_offset,
> + .no_edac = true,
> + },
> +};
> +
> +static const struct qcom_llcc_config sm6350_cfg[] = {
> + {
> + .sct_data = sm6350_data,
> + .size = ARRAY_SIZE(sm6350_data),
> + .need_llcc_cfg = true,
> + .reg_offset = llcc_v1_reg_offset,
> + .edac_reg_offset = &llcc_v1_edac_reg_offset,
> + },
> +};
> +
> +static const struct qcom_llcc_config sm7150_cfg[] = {
> + {
> + .sct_data = sm7150_data,
> + .size = ARRAY_SIZE(sm7150_data),
> + .need_llcc_cfg = true,
> + .reg_offset = llcc_v1_reg_offset,
> + .edac_reg_offset = &llcc_v1_edac_reg_offset,
> + },
> };
>
> -static const struct qcom_llcc_config sc7280_cfg = {
> - .sct_data = sc7280_data,
> - .size = ARRAY_SIZE(sc7280_data),
> - .need_llcc_cfg = true,
> - .reg_offset = llcc_v1_reg_offset,
> - .edac_reg_offset = &llcc_v1_edac_reg_offset,
> +static const struct qcom_llcc_config sm8150_cfg[] = {
> + {
> + .sct_data = sm8150_data,
> + .size = ARRAY_SIZE(sm8150_data),
> + .need_llcc_cfg = true,
> + .reg_offset = llcc_v1_reg_offset,
> + .edac_reg_offset = &llcc_v1_edac_reg_offset,
> + },
> };
>
> -static const struct qcom_llcc_config sc8180x_cfg = {
> - .sct_data = sc8180x_data,
> - .size = ARRAY_SIZE(sc8180x_data),
> - .need_llcc_cfg = true,
> - .reg_offset = llcc_v1_reg_offset,
> - .edac_reg_offset = &llcc_v1_edac_reg_offset,
> +static const struct qcom_llcc_config sm8250_cfg[] = {
> + {
> + .sct_data = sm8250_data,
> + .size = ARRAY_SIZE(sm8250_data),
> + .need_llcc_cfg = true,
> + .reg_offset = llcc_v1_reg_offset,
> + .edac_reg_offset = &llcc_v1_edac_reg_offset,
> + },
> };
>
> -static const struct qcom_llcc_config sc8280xp_cfg = {
> - .sct_data = sc8280xp_data,
> - .size = ARRAY_SIZE(sc8280xp_data),
> - .need_llcc_cfg = true,
> - .reg_offset = llcc_v1_reg_offset,
> - .edac_reg_offset = &llcc_v1_edac_reg_offset,
> +static const struct qcom_llcc_config sm8350_cfg[] = {
> + {
> + .sct_data = sm8350_data,
> + .size = ARRAY_SIZE(sm8350_data),
> + .need_llcc_cfg = true,
> + .reg_offset = llcc_v1_reg_offset,
> + .edac_reg_offset = &llcc_v1_edac_reg_offset,
> + },
> +};
> +
> +static const struct qcom_llcc_config sm8450_cfg[] = {
> + {
> + .sct_data = sm8450_data,
> + .size = ARRAY_SIZE(sm8450_data),
> + .need_llcc_cfg = true,
> + .reg_offset = llcc_v2_1_reg_offset,
> + .edac_reg_offset = &llcc_v2_1_edac_reg_offset,
> + },
> +};
> +
> +static const struct qcom_llcc_config sm8550_cfg[] = {
> + {
> + .sct_data = sm8550_data,
> + .size = ARRAY_SIZE(sm8550_data),
> + .need_llcc_cfg = true,
> + .reg_offset = llcc_v2_1_reg_offset,
> + .edac_reg_offset = &llcc_v2_1_edac_reg_offset,
> + },
> };
>
> -static const struct qcom_llcc_config sdm845_cfg = {
> - .sct_data = sdm845_data,
> - .size = ARRAY_SIZE(sdm845_data),
> - .need_llcc_cfg = false,
> - .reg_offset = llcc_v1_reg_offset,
> - .edac_reg_offset = &llcc_v1_edac_reg_offset,
> - .no_edac = true,
> +static const struct qcom_sct_config sc7180_cfgs = {
> + .llcc_config = sc7180_cfg,
> + .num_config = ARRAY_SIZE(sc7180_cfg),
> };
>
> -static const struct qcom_llcc_config sm6350_cfg = {
> - .sct_data = sm6350_data,
> - .size = ARRAY_SIZE(sm6350_data),
> - .need_llcc_cfg = true,
> - .reg_offset = llcc_v1_reg_offset,
> - .edac_reg_offset = &llcc_v1_edac_reg_offset,
> +static const struct qcom_sct_config sc7280_cfgs = {
> + .llcc_config = sc7280_cfg,
> + .num_config = ARRAY_SIZE(sc7280_cfg),
> };
>
> -static const struct qcom_llcc_config sm7150_cfg = {
> - .sct_data = sm7150_data,
> - .size = ARRAY_SIZE(sm7150_data),
> - .need_llcc_cfg = true,
> - .reg_offset = llcc_v1_reg_offset,
> - .edac_reg_offset = &llcc_v1_edac_reg_offset,
> +static const struct qcom_sct_config sc8180x_cfgs = {
> + .llcc_config = sc8180x_cfg,
> + .num_config = ARRAY_SIZE(sc8180x_cfg),
> };
>
> -static const struct qcom_llcc_config sm8150_cfg = {
> - .sct_data = sm8150_data,
> - .size = ARRAY_SIZE(sm8150_data),
> - .need_llcc_cfg = true,
> - .reg_offset = llcc_v1_reg_offset,
> - .edac_reg_offset = &llcc_v1_edac_reg_offset,
> +static const struct qcom_sct_config sc8280xp_cfgs = {
> + .llcc_config = sc8280xp_cfg,
> + .num_config = ARRAY_SIZE(sc8280xp_cfg),
> };
>
> -static const struct qcom_llcc_config sm8250_cfg = {
> - .sct_data = sm8250_data,
> - .size = ARRAY_SIZE(sm8250_data),
> - .need_llcc_cfg = true,
> - .reg_offset = llcc_v1_reg_offset,
> - .edac_reg_offset = &llcc_v1_edac_reg_offset,
> +static const struct qcom_sct_config sdm845_cfgs = {
> + .llcc_config = sdm845_cfg,
> + .num_config = ARRAY_SIZE(sdm845_cfg),
> };
>
> -static const struct qcom_llcc_config sm8350_cfg = {
> - .sct_data = sm8350_data,
> - .size = ARRAY_SIZE(sm8350_data),
> - .need_llcc_cfg = true,
> - .reg_offset = llcc_v1_reg_offset,
> - .edac_reg_offset = &llcc_v1_edac_reg_offset,
> +static const struct qcom_sct_config sm6350_cfgs = {
> + .llcc_config = sm6350_cfg,
> + .num_config = ARRAY_SIZE(sm6350_cfg),
> };
>
> -static const struct qcom_llcc_config sm8450_cfg = {
> - .sct_data = sm8450_data,
> - .size = ARRAY_SIZE(sm8450_data),
> - .need_llcc_cfg = true,
> - .reg_offset = llcc_v2_1_reg_offset,
> - .edac_reg_offset = &llcc_v2_1_edac_reg_offset,
> +static const struct qcom_sct_config sm7150_cfgs = {
> + .llcc_config = sm7150_cfg,
> + .num_config = ARRAY_SIZE(sm7150_cfg),
> };
>
> -static const struct qcom_llcc_config sm8550_cfg = {
> - .sct_data = sm8550_data,
> - .size = ARRAY_SIZE(sm8550_data),
> - .need_llcc_cfg = true,
> - .reg_offset = llcc_v2_1_reg_offset,
> - .edac_reg_offset = &llcc_v2_1_edac_reg_offset,
> +static const struct qcom_sct_config sm8150_cfgs = {
> + .llcc_config = sm8150_cfg,
> + .num_config = ARRAY_SIZE(sm8150_cfg),
> +};
> +
> +static const struct qcom_sct_config sm8250_cfgs = {
> + .llcc_config = sm8250_cfg,
> + .num_config = ARRAY_SIZE(sm8250_cfg),
> +};
> +
> +static const struct qcom_sct_config sm8350_cfgs = {
> + .llcc_config = sm8350_cfg,
> + .num_config = ARRAY_SIZE(sm8350_cfg),
> +};
> +
> +static const struct qcom_sct_config sm8450_cfgs = {
> + .llcc_config = sm8450_cfg,
> + .num_config = ARRAY_SIZE(sm8450_cfg),
> +};
> +
> +static const struct qcom_sct_config sm8550_cfgs = {
> + .llcc_config = sm8550_cfg,
> + .num_config = ARRAY_SIZE(sm8550_cfg),
> };
>
> static struct llcc_drv_data *drv_data = (void *) -EPROBE_DEFER;
> @@ -939,6 +1031,7 @@ static int qcom_llcc_probe(struct platform_device *pdev)
> struct device *dev = &pdev->dev;
> int ret, i;
> struct platform_device *llcc_edac;
> + const struct qcom_sct_config *cfgs;
> const struct qcom_llcc_config *cfg;
> const struct llcc_slice_config *llcc_cfg;
> u32 sz;
> @@ -958,7 +1051,12 @@ static int qcom_llcc_probe(struct platform_device *pdev)
> goto err;
> }
>
> - cfg = of_device_get_match_data(&pdev->dev);
> + cfgs = of_device_get_match_data(&pdev->dev);
> + if (cfgs->num_config != DEFAULT_CONFIG) {
NUL check is needed for cfgs;
-Mukesh
> + ret = -EINVAL;
> + goto err;
> + }
> + cfg = &cfgs->llcc_config[DEFAULT_CONFIG - 1];
>
> ret = regmap_read(regmap, cfg->reg_offset[LLCC_COMMON_STATUS0], &num_banks);
> if (ret)
> @@ -1051,18 +1149,18 @@ static int qcom_llcc_probe(struct platform_device *pdev)
> }
>
> static const struct of_device_id qcom_llcc_of_match[] = {
> - { .compatible = "qcom,sc7180-llcc", .data = &sc7180_cfg },
> - { .compatible = "qcom,sc7280-llcc", .data = &sc7280_cfg },
> - { .compatible = "qcom,sc8180x-llcc", .data = &sc8180x_cfg },
> - { .compatible = "qcom,sc8280xp-llcc", .data = &sc8280xp_cfg },
> - { .compatible = "qcom,sdm845-llcc", .data = &sdm845_cfg },
> - { .compatible = "qcom,sm6350-llcc", .data = &sm6350_cfg },
> - { .compatible = "qcom,sm7150-llcc", .data = &sm7150_cfg },
> - { .compatible = "qcom,sm8150-llcc", .data = &sm8150_cfg },
> - { .compatible = "qcom,sm8250-llcc", .data = &sm8250_cfg },
> - { .compatible = "qcom,sm8350-llcc", .data = &sm8350_cfg },
> - { .compatible = "qcom,sm8450-llcc", .data = &sm8450_cfg },
> - { .compatible = "qcom,sm8550-llcc", .data = &sm8550_cfg },
> + { .compatible = "qcom,sc7180-llcc", .data = &sc7180_cfgs },
> + { .compatible = "qcom,sc7280-llcc", .data = &sc7280_cfgs },
> + { .compatible = "qcom,sc8180x-llcc", .data = &sc8180x_cfgs },
> + { .compatible = "qcom,sc8280xp-llcc", .data = &sc8280xp_cfgs },
> + { .compatible = "qcom,sdm845-llcc", .data = &sdm845_cfgs },
> + { .compatible = "qcom,sm6350-llcc", .data = &sm6350_cfgs },
> + { .compatible = "qcom,sm7150-llcc", .data = &sm7150_cfgs },
> + { .compatible = "qcom,sm8150-llcc", .data = &sm8150_cfgs },
> + { .compatible = "qcom,sm8250-llcc", .data = &sm8250_cfgs },
> + { .compatible = "qcom,sm8350-llcc", .data = &sm8350_cfgs },
> + { .compatible = "qcom,sm8450-llcc", .data = &sm8450_cfgs },
> + { .compatible = "qcom,sm8550-llcc", .data = &sm8550_cfgs },
> { }
> };
> MODULE_DEVICE_TABLE(of, qcom_llcc_of_match);
> --
> 2.41.0
>
On 8/2/2023 2:44 PM, Komal Bajaj wrote:
> Add LLCC configuration data for QDU1000 and QRU1000 SoCs.
>
> Signed-off-by: Komal Bajaj <[email protected]>
> ---
> drivers/soc/qcom/llcc-qcom.c | 67 ++++++++++++++++++++++++++++++++++++
> 1 file changed, 67 insertions(+)
>
> diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c
> index 315f7a1b90aa..8e1b2399700d 100644
> --- a/drivers/soc/qcom/llcc-qcom.c
> +++ b/drivers/soc/qcom/llcc-qcom.c
> @@ -366,6 +366,36 @@ static const struct llcc_slice_config sm8550_data[] = {
> {LLCC_VIDVSP, 28, 256, 4, 1, 0xFFFFFF, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
> };
>
> +static const struct llcc_slice_config qdu1000_data_2ch[] = {
> + { LLCC_MDMHPGRW, 7, 512, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0, 0 },
> + { LLCC_MODHW, 9, 256, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0, 0 },
> + { LLCC_MDMPNG, 21, 256, 0, 1, 0x3, 0x0, 0, 0, 0, 1, 0, 0, 0 },
> + { LLCC_ECC, 26, 512, 3, 1, 0xffc, 0x0, 0, 0, 0, 0, 1, 0, 0 },
> + { LLCC_MODPE, 29, 256, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0, 0 },
> + { LLCC_APTCM, 30, 256, 3, 1, 0x0, 0xc, 1, 0, 0, 1, 0, 0, 0 },
> + { LLCC_WRCACHE, 31, 128, 1, 1, 0x3, 0x0, 0, 0, 0, 0, 1, 0, 0 },
> +};
> +
> +static const struct llcc_slice_config qdu1000_data_4ch[] = {
> + { LLCC_MDMHPGRW, 7, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0, 0 },
> + { LLCC_MODHW, 9, 512, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0, 0 },
> + { LLCC_MDMPNG, 21, 512, 0, 1, 0x3, 0x0, 0, 0, 0, 1, 0, 0, 0 },
> + { LLCC_ECC, 26, 1024, 3, 1, 0xffc, 0x0, 0, 0, 0, 0, 1, 0, 0 },
> + { LLCC_MODPE, 29, 512, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0, 0 },
> + { LLCC_APTCM, 30, 512, 3, 1, 0x0, 0xc, 1, 0, 0, 1, 0, 0, 0 },
> + { LLCC_WRCACHE, 31, 256, 1, 1, 0x3, 0x0, 0, 0, 0, 0, 1, 0, 0 },
> +};
> +
> +static const struct llcc_slice_config qdu1000_data_8ch[] = {
> + { LLCC_MDMHPGRW, 7, 2048, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0, 0 },
> + { LLCC_MODHW, 9, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0, 0 },
> + { LLCC_MDMPNG, 21, 1024, 0, 1, 0x3, 0x0, 0, 0, 0, 1, 0, 0, 0 },
> + { LLCC_ECC, 26, 2048, 3, 1, 0xffc, 0x0, 0, 0, 0, 0, 1, 0, 0 },
> + { LLCC_MODPE, 29, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0, 0 },
> + { LLCC_APTCM, 30, 1024, 3, 1, 0x0, 0xc, 1, 0, 0, 1, 0, 0, 0 },
> + { LLCC_WRCACHE, 31, 512, 1, 1, 0x3, 0x0, 0, 0, 0, 0, 1, 0, 0 },
> +};
> +
> static const struct llcc_edac_reg_offset llcc_v1_edac_reg_offset = {
> .trp_ecc_error_status0 = 0x20344,
> .trp_ecc_error_status1 = 0x20348,
> @@ -432,6 +462,37 @@ static const u32 llcc_v2_1_reg_offset[] = {
> [LLCC_COMMON_STATUS0] = 0x0003400c,
> };
>
> +static const struct qcom_llcc_config qdu1000_cfg[] = {
> + {
> + .sct_data = qdu1000_data_8ch,
> + .size = ARRAY_SIZE(qdu1000_data_8ch),
> + .need_llcc_cfg = true,
> + .reg_offset = llcc_v2_1_reg_offset,
> + .edac_reg_offset = &llcc_v2_1_edac_reg_offset,
> + },
> + {
> + .sct_data = qdu1000_data_4ch,
> + .size = ARRAY_SIZE(qdu1000_data_4ch),
> + .need_llcc_cfg = true,
> + .reg_offset = llcc_v2_1_reg_offset,
> + .edac_reg_offset = &llcc_v2_1_edac_reg_offset,
> + },
> + {
> + .sct_data = qdu1000_data_4ch,
> + .size = ARRAY_SIZE(qdu1000_data_4ch),
> + .need_llcc_cfg = true,
> + .reg_offset = llcc_v2_1_reg_offset,
> + .edac_reg_offset = &llcc_v2_1_edac_reg_offset,
> + },
> + {
> + .sct_data = qdu1000_data_2ch,
> + .size = ARRAY_SIZE(qdu1000_data_2ch),
> + .need_llcc_cfg = true,
> + .reg_offset = llcc_v2_1_reg_offset,
> + .edac_reg_offset = &llcc_v2_1_edac_reg_offset,
> + },
> +};
> +
> static const struct qcom_llcc_config sc7180_cfg[] = {
> {
> .sct_data = sc7180_data,
> @@ -553,6 +614,11 @@ static const struct qcom_llcc_config sm8550_cfg[] = {
> },
> };
>
> +static const struct qcom_sct_config qdu1000_cfgs = {
> + .llcc_config = qdu1000_cfg,
> + .num_config = 4,
looks like you missed to take konrad suggestion here
https://lore.kernel.org/lkml/[email protected]/
-Mukesh
> +};
> +
> static const struct qcom_sct_config sc7180_cfgs = {
> .llcc_config = sc7180_cfg,
> .num_config = ARRAY_SIZE(sc7180_cfg),
> @@ -1171,6 +1237,7 @@ static int qcom_llcc_probe(struct platform_device *pdev)
> }
>
> static const struct of_device_id qcom_llcc_of_match[] = {
> + { .compatible = "qcom,qdu1000-llcc", .data = &qdu1000_cfgs},
> { .compatible = "qcom,sc7180-llcc", .data = &sc7180_cfgs },
> { .compatible = "qcom,sc7280-llcc", .data = &sc7280_cfgs },
> { .compatible = "qcom,sc8180x-llcc", .data = &sc8180x_cfgs },
> --
> 2.41.0
>
On 8/3/2023 6:39 PM, Mukesh Ojha wrote:
>
>
> On 8/2/2023 2:44 PM, Komal Bajaj wrote:
>> Add LLCC configuration data for QDU1000 and QRU1000 SoCs.
>>
>> Signed-off-by: Komal Bajaj <[email protected]>
>> ---
>> drivers/soc/qcom/llcc-qcom.c | 67 ++++++++++++++++++++++++++++++++++++
>> 1 file changed, 67 insertions(+)
>>
>> diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c
>> index 315f7a1b90aa..8e1b2399700d 100644
>> --- a/drivers/soc/qcom/llcc-qcom.c
>> +++ b/drivers/soc/qcom/llcc-qcom.c
>> @@ -366,6 +366,36 @@ static const struct llcc_slice_config
>> sm8550_data[] = {
>> {LLCC_VIDVSP, 28, 256, 4, 1, 0xFFFFFF, 0x0, 0, 0, 0, 0, 0,
>> 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
>> };
>>
>> +static const struct llcc_slice_config qdu1000_data_2ch[] = {
>> + { LLCC_MDMHPGRW, 7, 512, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0, 0 },
>> + { LLCC_MODHW, 9, 256, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0, 0 },
>> + { LLCC_MDMPNG, 21, 256, 0, 1, 0x3, 0x0, 0, 0, 0, 1, 0, 0, 0 },
>> + { LLCC_ECC, 26, 512, 3, 1, 0xffc, 0x0, 0, 0, 0, 0, 1, 0, 0 },
>> + { LLCC_MODPE, 29, 256, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0, 0 },
>> + { LLCC_APTCM, 30, 256, 3, 1, 0x0, 0xc, 1, 0, 0, 1, 0, 0, 0 },
>> + { LLCC_WRCACHE, 31, 128, 1, 1, 0x3, 0x0, 0, 0, 0, 0, 1, 0, 0 },
>> +};
>> +
>> +static const struct llcc_slice_config qdu1000_data_4ch[] = {
>> + { LLCC_MDMHPGRW, 7, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0, 0 },
>> + { LLCC_MODHW, 9, 512, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0, 0 },
>> + { LLCC_MDMPNG, 21, 512, 0, 1, 0x3, 0x0, 0, 0, 0, 1, 0, 0, 0 },
>> + { LLCC_ECC, 26, 1024, 3, 1, 0xffc, 0x0, 0, 0, 0, 0, 1, 0, 0 },
>> + { LLCC_MODPE, 29, 512, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0, 0 },
>> + { LLCC_APTCM, 30, 512, 3, 1, 0x0, 0xc, 1, 0, 0, 1, 0, 0, 0 },
>> + { LLCC_WRCACHE, 31, 256, 1, 1, 0x3, 0x0, 0, 0, 0, 0, 1, 0, 0 },
>> +};
>> +
>> +static const struct llcc_slice_config qdu1000_data_8ch[] = {
>> + { LLCC_MDMHPGRW, 7, 2048, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0, 0 },
>> + { LLCC_MODHW, 9, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0, 0 },
>> + { LLCC_MDMPNG, 21, 1024, 0, 1, 0x3, 0x0, 0, 0, 0, 1, 0, 0, 0 },
>> + { LLCC_ECC, 26, 2048, 3, 1, 0xffc, 0x0, 0, 0, 0, 0, 1, 0, 0 },
>> + { LLCC_MODPE, 29, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0, 0 },
>> + { LLCC_APTCM, 30, 1024, 3, 1, 0x0, 0xc, 1, 0, 0, 1, 0, 0, 0 },
>> + { LLCC_WRCACHE, 31, 512, 1, 1, 0x3, 0x0, 0, 0, 0, 0, 1, 0, 0 },
>> +};
>> +
>> static const struct llcc_edac_reg_offset llcc_v1_edac_reg_offset = {
>> .trp_ecc_error_status0 = 0x20344,
>> .trp_ecc_error_status1 = 0x20348,
>> @@ -432,6 +462,37 @@ static const u32 llcc_v2_1_reg_offset[] = {
>> [LLCC_COMMON_STATUS0] = 0x0003400c,
>> };
>>
>> +static const struct qcom_llcc_config qdu1000_cfg[] = {
>> + {
>> + .sct_data = qdu1000_data_8ch,
>> + .size = ARRAY_SIZE(qdu1000_data_8ch),
>> + .need_llcc_cfg = true,
>> + .reg_offset = llcc_v2_1_reg_offset,
>> + .edac_reg_offset = &llcc_v2_1_edac_reg_offset,
>> + },
>> + {
>> + .sct_data = qdu1000_data_4ch,
>> + .size = ARRAY_SIZE(qdu1000_data_4ch),
>> + .need_llcc_cfg = true,
>> + .reg_offset = llcc_v2_1_reg_offset,
>> + .edac_reg_offset = &llcc_v2_1_edac_reg_offset,
>> + },
>> + {
>> + .sct_data = qdu1000_data_4ch,
>> + .size = ARRAY_SIZE(qdu1000_data_4ch),
>> + .need_llcc_cfg = true,
>> + .reg_offset = llcc_v2_1_reg_offset,
>> + .edac_reg_offset = &llcc_v2_1_edac_reg_offset,
>> + },
>> + {
>> + .sct_data = qdu1000_data_2ch,
>> + .size = ARRAY_SIZE(qdu1000_data_2ch),
>> + .need_llcc_cfg = true,
>> + .reg_offset = llcc_v2_1_reg_offset,
>> + .edac_reg_offset = &llcc_v2_1_edac_reg_offset,
>> + },
>> +};
>> +
>> static const struct qcom_llcc_config sc7180_cfg[] = {
>> {
>> .sct_data = sc7180_data,
>> @@ -553,6 +614,11 @@ static const struct qcom_llcc_config
>> sm8550_cfg[] = {
>> },
>> };
>>
>> +static const struct qcom_sct_config qdu1000_cfgs = {
>> + .llcc_config = qdu1000_cfg,
>> + .num_config = 4,
>
> looks like you missed to take konrad suggestion here
>
> https://lore.kernel.org/lkml/[email protected]/
>
Yes, I missed that. Thanks for catching it.
>
> -Mukesh
>
>> +};
>> +
>> static const struct qcom_sct_config sc7180_cfgs = {
>> .llcc_config = sc7180_cfg,
>> .num_config = ARRAY_SIZE(sc7180_cfg),
>> @@ -1171,6 +1237,7 @@ static int qcom_llcc_probe(struct
>> platform_device *pdev)
>> }
>>
>> static const struct of_device_id qcom_llcc_of_match[] = {
>> + { .compatible = "qcom,qdu1000-llcc", .data = &qdu1000_cfgs},
>> { .compatible = "qcom,sc7180-llcc", .data = &sc7180_cfgs },
>> { .compatible = "qcom,sc7280-llcc", .data = &sc7280_cfgs },
>> { .compatible = "qcom,sc8180x-llcc", .data = &sc8180x_cfgs },
>> --
>> 2.41.0
>>
On 8/3/2023 6:33 PM, Mukesh Ojha wrote:
>
>
> On 8/2/2023 2:44 PM, Komal Bajaj wrote:
>> Refactor driver to support multiple configuration for llcc on a target.
>>
>> Signed-off-by: Komal Bajaj <[email protected]>
>> ---
>> drivers/soc/qcom/llcc-qcom.c | 270 ++++++++++++++++++++++++-----------
>> 1 file changed, 184 insertions(+), 86 deletions(-)
>>
>> diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c
>> index 67c19ed2219a..808c5aaa7407 100644
>> --- a/drivers/soc/qcom/llcc-qcom.c
>> +++ b/drivers/soc/qcom/llcc-qcom.c
>> @@ -66,6 +66,8 @@
>> #define LLCC_VERSION_2_1_0_0 0x02010000
>> #define LLCC_VERSION_4_1_0_0 0x04010000
>>
>> +#define DEFAULT_CONFIG 1
>
> Could it be DEF_NUM_CFG ?
Okay, will update the macro name.
>
>> +
>> /**
>> * struct llcc_slice_config - Data associated with the llcc slice
>> * @usecase_id: Unique id for the client's use case
>> @@ -127,6 +129,12 @@ struct qcom_llcc_config {
>> bool no_edac;
>> };
>>
>> +struct qcom_sct_config {
>> + const struct qcom_llcc_config *llcc_config;
>> + int num_config;
>> +};
>> +
>> +
>
> Extra line..
Noted.
>
>> enum llcc_reg_offset {
>> LLCC_COMMON_HW_INFO,
>> LLCC_COMMON_STATUS0,
>> @@ -423,101 +431,185 @@ static const u32 llcc_v2_1_reg_offset[] = {
>> [LLCC_COMMON_STATUS0] = 0x0003400c,
>> };
>>
>> -static const struct qcom_llcc_config sc7180_cfg = {
>> - .sct_data = sc7180_data,
>> - .size = ARRAY_SIZE(sc7180_data),
>> - .need_llcc_cfg = true,
>> - .reg_offset = llcc_v1_reg_offset,
>> - .edac_reg_offset = &llcc_v1_edac_reg_offset,
>> +static const struct qcom_llcc_config sc7180_cfg[] = {
>> + {
>> + .sct_data = sc7180_data,
>> + .size = ARRAY_SIZE(sc7180_data),
>> + .need_llcc_cfg = true,
>> + .reg_offset = llcc_v1_reg_offset,
>> + .edac_reg_offset = &llcc_v1_edac_reg_offset,
>> + },
>> +};
>> +
>> +static const struct qcom_llcc_config sc7280_cfg[] = {
>> + {
>> + .sct_data = sc7280_data,
>> + .size = ARRAY_SIZE(sc7280_data),
>> + .need_llcc_cfg = true,
>> + .reg_offset = llcc_v1_reg_offset,
>> + .edac_reg_offset = &llcc_v1_edac_reg_offset,
>> + },
>> +};
>> +
>> +static const struct qcom_llcc_config sc8180x_cfg[] = {
>> + {
>> + .sct_data = sc8180x_data,
>> + .size = ARRAY_SIZE(sc8180x_data),
>> + .need_llcc_cfg = true,
>> + .reg_offset = llcc_v1_reg_offset,
>> + .edac_reg_offset = &llcc_v1_edac_reg_offset,
>> + },
>> +};
>> +
>> +static const struct qcom_llcc_config sc8280xp_cfg[] = {
>> + {
>> + .sct_data = sc8280xp_data,
>> + .size = ARRAY_SIZE(sc8280xp_data),
>> + .need_llcc_cfg = true,
>> + .reg_offset = llcc_v1_reg_offset,
>> + .edac_reg_offset = &llcc_v1_edac_reg_offset,
>> + },
>> +};
>> +
>> +static const struct qcom_llcc_config sdm845_cfg[] = {
>> + {
>> + .sct_data = sdm845_data,
>> + .size = ARRAY_SIZE(sdm845_data),
>> + .need_llcc_cfg = false,
>> + .reg_offset = llcc_v1_reg_offset,
>> + .edac_reg_offset = &llcc_v1_edac_reg_offset,
>> + .no_edac = true,
>> + },
>> +};
>> +
>> +static const struct qcom_llcc_config sm6350_cfg[] = {
>> + {
>> + .sct_data = sm6350_data,
>> + .size = ARRAY_SIZE(sm6350_data),
>> + .need_llcc_cfg = true,
>> + .reg_offset = llcc_v1_reg_offset,
>> + .edac_reg_offset = &llcc_v1_edac_reg_offset,
>> + },
>> +};
>> +
>> +static const struct qcom_llcc_config sm7150_cfg[] = {
>> + {
>> + .sct_data = sm7150_data,
>> + .size = ARRAY_SIZE(sm7150_data),
>> + .need_llcc_cfg = true,
>> + .reg_offset = llcc_v1_reg_offset,
>> + .edac_reg_offset = &llcc_v1_edac_reg_offset,
>> + },
>> };
>>
>> -static const struct qcom_llcc_config sc7280_cfg = {
>> - .sct_data = sc7280_data,
>> - .size = ARRAY_SIZE(sc7280_data),
>> - .need_llcc_cfg = true,
>> - .reg_offset = llcc_v1_reg_offset,
>> - .edac_reg_offset = &llcc_v1_edac_reg_offset,
>> +static const struct qcom_llcc_config sm8150_cfg[] = {
>> + {
>> + .sct_data = sm8150_data,
>> + .size = ARRAY_SIZE(sm8150_data),
>> + .need_llcc_cfg = true,
>> + .reg_offset = llcc_v1_reg_offset,
>> + .edac_reg_offset = &llcc_v1_edac_reg_offset,
>> + },
>> };
>>
>> -static const struct qcom_llcc_config sc8180x_cfg = {
>> - .sct_data = sc8180x_data,
>> - .size = ARRAY_SIZE(sc8180x_data),
>> - .need_llcc_cfg = true,
>> - .reg_offset = llcc_v1_reg_offset,
>> - .edac_reg_offset = &llcc_v1_edac_reg_offset,
>> +static const struct qcom_llcc_config sm8250_cfg[] = {
>> + {
>> + .sct_data = sm8250_data,
>> + .size = ARRAY_SIZE(sm8250_data),
>> + .need_llcc_cfg = true,
>> + .reg_offset = llcc_v1_reg_offset,
>> + .edac_reg_offset = &llcc_v1_edac_reg_offset,
>> + },
>> };
>>
>> -static const struct qcom_llcc_config sc8280xp_cfg = {
>> - .sct_data = sc8280xp_data,
>> - .size = ARRAY_SIZE(sc8280xp_data),
>> - .need_llcc_cfg = true,
>> - .reg_offset = llcc_v1_reg_offset,
>> - .edac_reg_offset = &llcc_v1_edac_reg_offset,
>> +static const struct qcom_llcc_config sm8350_cfg[] = {
>> + {
>> + .sct_data = sm8350_data,
>> + .size = ARRAY_SIZE(sm8350_data),
>> + .need_llcc_cfg = true,
>> + .reg_offset = llcc_v1_reg_offset,
>> + .edac_reg_offset = &llcc_v1_edac_reg_offset,
>> + },
>> +};
>> +
>> +static const struct qcom_llcc_config sm8450_cfg[] = {
>> + {
>> + .sct_data = sm8450_data,
>> + .size = ARRAY_SIZE(sm8450_data),
>> + .need_llcc_cfg = true,
>> + .reg_offset = llcc_v2_1_reg_offset,
>> + .edac_reg_offset = &llcc_v2_1_edac_reg_offset,
>> + },
>> +};
>> +
>> +static const struct qcom_llcc_config sm8550_cfg[] = {
>> + {
>> + .sct_data = sm8550_data,
>> + .size = ARRAY_SIZE(sm8550_data),
>> + .need_llcc_cfg = true,
>> + .reg_offset = llcc_v2_1_reg_offset,
>> + .edac_reg_offset = &llcc_v2_1_edac_reg_offset,
>> + },
>> };
>>
>> -static const struct qcom_llcc_config sdm845_cfg = {
>> - .sct_data = sdm845_data,
>> - .size = ARRAY_SIZE(sdm845_data),
>> - .need_llcc_cfg = false,
>> - .reg_offset = llcc_v1_reg_offset,
>> - .edac_reg_offset = &llcc_v1_edac_reg_offset,
>> - .no_edac = true,
>> +static const struct qcom_sct_config sc7180_cfgs = {
>> + .llcc_config = sc7180_cfg,
>> + .num_config = ARRAY_SIZE(sc7180_cfg),
>> };
>>
>> -static const struct qcom_llcc_config sm6350_cfg = {
>> - .sct_data = sm6350_data,
>> - .size = ARRAY_SIZE(sm6350_data),
>> - .need_llcc_cfg = true,
>> - .reg_offset = llcc_v1_reg_offset,
>> - .edac_reg_offset = &llcc_v1_edac_reg_offset,
>> +static const struct qcom_sct_config sc7280_cfgs = {
>> + .llcc_config = sc7280_cfg,
>> + .num_config = ARRAY_SIZE(sc7280_cfg),
>> };
>>
>> -static const struct qcom_llcc_config sm7150_cfg = {
>> - .sct_data = sm7150_data,
>> - .size = ARRAY_SIZE(sm7150_data),
>> - .need_llcc_cfg = true,
>> - .reg_offset = llcc_v1_reg_offset,
>> - .edac_reg_offset = &llcc_v1_edac_reg_offset,
>> +static const struct qcom_sct_config sc8180x_cfgs = {
>> + .llcc_config = sc8180x_cfg,
>> + .num_config = ARRAY_SIZE(sc8180x_cfg),
>> };
>>
>> -static const struct qcom_llcc_config sm8150_cfg = {
>> - .sct_data = sm8150_data,
>> - .size = ARRAY_SIZE(sm8150_data),
>> - .need_llcc_cfg = true,
>> - .reg_offset = llcc_v1_reg_offset,
>> - .edac_reg_offset = &llcc_v1_edac_reg_offset,
>> +static const struct qcom_sct_config sc8280xp_cfgs = {
>> + .llcc_config = sc8280xp_cfg,
>> + .num_config = ARRAY_SIZE(sc8280xp_cfg),
>> };
>>
>> -static const struct qcom_llcc_config sm8250_cfg = {
>> - .sct_data = sm8250_data,
>> - .size = ARRAY_SIZE(sm8250_data),
>> - .need_llcc_cfg = true,
>> - .reg_offset = llcc_v1_reg_offset,
>> - .edac_reg_offset = &llcc_v1_edac_reg_offset,
>> +static const struct qcom_sct_config sdm845_cfgs = {
>> + .llcc_config = sdm845_cfg,
>> + .num_config = ARRAY_SIZE(sdm845_cfg),
>> };
>>
>> -static const struct qcom_llcc_config sm8350_cfg = {
>> - .sct_data = sm8350_data,
>> - .size = ARRAY_SIZE(sm8350_data),
>> - .need_llcc_cfg = true,
>> - .reg_offset = llcc_v1_reg_offset,
>> - .edac_reg_offset = &llcc_v1_edac_reg_offset,
>> +static const struct qcom_sct_config sm6350_cfgs = {
>> + .llcc_config = sm6350_cfg,
>> + .num_config = ARRAY_SIZE(sm6350_cfg),
>> };
>>
>> -static const struct qcom_llcc_config sm8450_cfg = {
>> - .sct_data = sm8450_data,
>> - .size = ARRAY_SIZE(sm8450_data),
>> - .need_llcc_cfg = true,
>> - .reg_offset = llcc_v2_1_reg_offset,
>> - .edac_reg_offset = &llcc_v2_1_edac_reg_offset,
>> +static const struct qcom_sct_config sm7150_cfgs = {
>> + .llcc_config = sm7150_cfg,
>> + .num_config = ARRAY_SIZE(sm7150_cfg),
>> };
>>
>> -static const struct qcom_llcc_config sm8550_cfg = {
>> - .sct_data = sm8550_data,
>> - .size = ARRAY_SIZE(sm8550_data),
>> - .need_llcc_cfg = true,
>> - .reg_offset = llcc_v2_1_reg_offset,
>> - .edac_reg_offset = &llcc_v2_1_edac_reg_offset,
>> +static const struct qcom_sct_config sm8150_cfgs = {
>> + .llcc_config = sm8150_cfg,
>> + .num_config = ARRAY_SIZE(sm8150_cfg),
>> +};
>> +
>> +static const struct qcom_sct_config sm8250_cfgs = {
>> + .llcc_config = sm8250_cfg,
>> + .num_config = ARRAY_SIZE(sm8250_cfg),
>> +};
>> +
>> +static const struct qcom_sct_config sm8350_cfgs = {
>> + .llcc_config = sm8350_cfg,
>> + .num_config = ARRAY_SIZE(sm8350_cfg),
>> +};
>> +
>> +static const struct qcom_sct_config sm8450_cfgs = {
>> + .llcc_config = sm8450_cfg,
>> + .num_config = ARRAY_SIZE(sm8450_cfg),
>> +};
>> +
>> +static const struct qcom_sct_config sm8550_cfgs = {
>> + .llcc_config = sm8550_cfg,
>> + .num_config = ARRAY_SIZE(sm8550_cfg),
>> };
>>
>> static struct llcc_drv_data *drv_data = (void *) -EPROBE_DEFER;
>> @@ -939,6 +1031,7 @@ static int qcom_llcc_probe(struct
>> platform_device *pdev)
>> struct device *dev = &pdev->dev;
>> int ret, i;
>> struct platform_device *llcc_edac;
>> + const struct qcom_sct_config *cfgs;
>> const struct qcom_llcc_config *cfg;
>> const struct llcc_slice_config *llcc_cfg;
>> u32 sz;
>> @@ -958,7 +1051,12 @@ static int qcom_llcc_probe(struct
>> platform_device *pdev)
>> goto err;
>> }
>>
>> - cfg = of_device_get_match_data(&pdev->dev);
>> + cfgs = of_device_get_match_data(&pdev->dev);
>> + if (cfgs->num_config != DEFAULT_CONFIG) {
>
> NUL check is needed for cfgs;
Sure, will add the NULL check.
Thanks
Komal
>
>
> -Mukesh
>> + ret = -EINVAL;
>> + goto err;
>> + }
>> + cfg = &cfgs->llcc_config[DEFAULT_CONFIG - 1];
>>
>> ret = regmap_read(regmap, cfg->reg_offset[LLCC_COMMON_STATUS0],
>> &num_banks);
>> if (ret)
>> @@ -1051,18 +1149,18 @@ static int qcom_llcc_probe(struct
>> platform_device *pdev)
>> }
>>
>> static const struct of_device_id qcom_llcc_of_match[] = {
>> - { .compatible = "qcom,sc7180-llcc", .data = &sc7180_cfg },
>> - { .compatible = "qcom,sc7280-llcc", .data = &sc7280_cfg },
>> - { .compatible = "qcom,sc8180x-llcc", .data = &sc8180x_cfg },
>> - { .compatible = "qcom,sc8280xp-llcc", .data = &sc8280xp_cfg },
>> - { .compatible = "qcom,sdm845-llcc", .data = &sdm845_cfg },
>> - { .compatible = "qcom,sm6350-llcc", .data = &sm6350_cfg },
>> - { .compatible = "qcom,sm7150-llcc", .data = &sm7150_cfg },
>> - { .compatible = "qcom,sm8150-llcc", .data = &sm8150_cfg },
>> - { .compatible = "qcom,sm8250-llcc", .data = &sm8250_cfg },
>> - { .compatible = "qcom,sm8350-llcc", .data = &sm8350_cfg },
>> - { .compatible = "qcom,sm8450-llcc", .data = &sm8450_cfg },
>> - { .compatible = "qcom,sm8550-llcc", .data = &sm8550_cfg },
>> + { .compatible = "qcom,sc7180-llcc", .data = &sc7180_cfgs },
>> + { .compatible = "qcom,sc7280-llcc", .data = &sc7280_cfgs },
>> + { .compatible = "qcom,sc8180x-llcc", .data = &sc8180x_cfgs },
>> + { .compatible = "qcom,sc8280xp-llcc", .data = &sc8280xp_cfgs },
>> + { .compatible = "qcom,sdm845-llcc", .data = &sdm845_cfgs },
>> + { .compatible = "qcom,sm6350-llcc", .data = &sm6350_cfgs },
>> + { .compatible = "qcom,sm7150-llcc", .data = &sm7150_cfgs },
>> + { .compatible = "qcom,sm8150-llcc", .data = &sm8150_cfgs },
>> + { .compatible = "qcom,sm8250-llcc", .data = &sm8250_cfgs },
>> + { .compatible = "qcom,sm8350-llcc", .data = &sm8350_cfgs },
>> + { .compatible = "qcom,sm8450-llcc", .data = &sm8450_cfgs },
>> + { .compatible = "qcom,sm8550-llcc", .data = &sm8550_cfgs },
>> { }
>> };
>> MODULE_DEVICE_TABLE(of, qcom_llcc_of_match);
>> --
>> 2.41.0
>>