Update GCC clocks and add support for GDSCs for QDU1000 and QRU1000 SoCs.
Changes since v4:
- Updated the commit text as per the review comments
- Split the gcc_ddrss_ecpri_gsi_clk and gcc_gpll1_out_even clock changes
Changes since v3:
- Split the gcc rcg ops changes as per the review comments
Changes since v2:
- Split the gcc clkref clock changes as per the review comments
Changes since v1:
- Dropped the v2 variant compatible changes
- Update tha maintainers list
- Split the GCC driver patch as per the review comments
Previous series:
v4 - https://patchwork.kernel.org/project/linux-arm-msm/list/?series=767111
v3 - https://patchwork.kernel.org/project/linux-arm-msm/list/?series=763044
v2 - https://patchwork.kernel.org/project/linux-arm-msm/list/?series=760862
v1 - https://patchwork.kernel.org/project/linux-arm-msm/list/?series=757828
Imran Shaik (8):
dt-bindings: clock: Update GCC clocks for QDU1000 and QRU1000 SoCs
clk: qcom: gcc-qdu1000: Fix gcc_pcie_0_pipe_clk_src clock handling
clk: qcom: gcc-qdu1000: Fix clkref clocks handling
clk: qcom: gcc-qdu1000: Register gcc_gpll1_out_even clock
clk: qcom: gcc-qdu1000: Add gcc_ddrss_ecpri_gsi_clk support
clk: qcom: gcc-qdu1000: Add support for GDSCs
clk: qcom: gcc-qdu1000: Update the SDCC clock RCG ops
clk: qcom: gcc-qdu1000: Update the RCGs ops
.../bindings/clock/qcom,qdu1000-gcc.yaml | 3 +-
drivers/clk/qcom/gcc-qdu1000.c | 159 ++++++++++++------
include/dt-bindings/clock/qcom,qdu1000-gcc.h | 4 +-
3 files changed, 110 insertions(+), 56 deletions(-)
--
2.25.1
Fix the gcc pcie pipe clock handling as per the clk_regmap_phy_mux_ops
implementation to let the clock framework automatically park the clock
at XO when the clock is switched off and restore the parent when the
clock is switched on.
Fixes: 1c9efb0bc040 ("clk: qcom: Add QDU1000 and QRU1000 GCC support")
Co-developed-by: Taniya Das <[email protected]>
Signed-off-by: Taniya Das <[email protected]>
Signed-off-by: Imran Shaik <[email protected]>
Reviewed-by: Konrad Dybcio <[email protected]>
---
Changes since v4:
- None
Changes since v3:
- None
Changes since v2:
- Updated the commit text
Changes since v1:
- Newly added
drivers/clk/qcom/gcc-qdu1000.c | 23 ++++++-----------------
1 file changed, 6 insertions(+), 17 deletions(-)
diff --git a/drivers/clk/qcom/gcc-qdu1000.c b/drivers/clk/qcom/gcc-qdu1000.c
index 328b306297ef..9fa0616952d9 100644
--- a/drivers/clk/qcom/gcc-qdu1000.c
+++ b/drivers/clk/qcom/gcc-qdu1000.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
- * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <linux/clk-provider.h>
@@ -371,16 +371,6 @@ static const struct clk_parent_data gcc_parent_data_6[] = {
{ .index = DT_TCXO_IDX },
};
-static const struct parent_map gcc_parent_map_7[] = {
- { P_PCIE_0_PIPE_CLK, 0 },
- { P_BI_TCXO, 2 },
-};
-
-static const struct clk_parent_data gcc_parent_data_7[] = {
- { .index = DT_PCIE_0_PIPE_CLK_IDX },
- { .index = DT_TCXO_IDX },
-};
-
static const struct parent_map gcc_parent_map_8[] = {
{ P_BI_TCXO, 0 },
{ P_GCC_GPLL0_OUT_MAIN, 1 },
@@ -440,16 +430,15 @@ static struct clk_regmap_mux gcc_pcie_0_phy_aux_clk_src = {
},
};
-static struct clk_regmap_mux gcc_pcie_0_pipe_clk_src = {
+static struct clk_regmap_phy_mux gcc_pcie_0_pipe_clk_src = {
.reg = 0x9d064,
- .shift = 0,
- .width = 2,
- .parent_map = gcc_parent_map_7,
.clkr = {
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_0_pipe_clk_src",
- .parent_data = gcc_parent_data_7,
- .num_parents = ARRAY_SIZE(gcc_parent_data_7),
+ .parent_data = &(const struct clk_parent_data){
+ .index = DT_PCIE_0_PIPE_CLK_IDX,
+ },
+ .num_parents = 1,
.ops = &clk_regmap_phy_mux_ops,
},
},
--
2.25.1
Add the gcc_ddrss_ecpri_gsi_clk support as per the latest hardware
version of QDU1000 and QRU100 SoCs.
Signed-off-by: Imran Shaik <[email protected]>
---
Changes since v4:
- Split the patch
- Newly added
drivers/clk/qcom/gcc-qdu1000.c | 21 +++++++++++++++++++++
1 file changed, 21 insertions(+)
diff --git a/drivers/clk/qcom/gcc-qdu1000.c b/drivers/clk/qcom/gcc-qdu1000.c
index 97fd1947637a..5bf62f04cf12 100644
--- a/drivers/clk/qcom/gcc-qdu1000.c
+++ b/drivers/clk/qcom/gcc-qdu1000.c
@@ -1132,6 +1132,26 @@ static struct clk_branch gcc_ddrss_ecpri_dma_clk = {
},
};
+static struct clk_branch gcc_ddrss_ecpri_gsi_clk = {
+ .halt_reg = 0x54298,
+ .halt_check = BRANCH_HALT_VOTED,
+ .hwcg_reg = 0x54298,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x54298,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_ddrss_ecpri_gsi_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &gcc_aggre_noc_ecpri_gsi_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_aon_ops,
+ },
+ },
+};
+
static struct clk_branch gcc_ecpri_ahb_clk = {
.halt_reg = 0x3a008,
.halt_check = BRANCH_HALT_VOTED,
@@ -2523,6 +2543,7 @@ static struct clk_regmap *gcc_qdu1000_clocks[] = {
[GCC_PCIE_0_PHY_AUX_CLK_SRC] = &gcc_pcie_0_phy_aux_clk_src.clkr,
[GCC_PCIE_0_PIPE_CLK_SRC] = &gcc_pcie_0_pipe_clk_src.clkr,
[GCC_GPLL1_OUT_EVEN] = &gcc_gpll1_out_even.clkr,
+ [GCC_DDRSS_ECPRI_GSI_CLK] = &gcc_ddrss_ecpri_gsi_clk.clkr,
};
static const struct qcom_reset_map gcc_qdu1000_resets[] = {
--
2.25.1
On 3.08.2023 12:57, Imran Shaik wrote:
> Add the gcc_ddrss_ecpri_gsi_clk support as per the latest hardware
> version of QDU1000 and QRU100 SoCs.
>
> Signed-off-by: Imran Shaik <[email protected]>
> ---
Reviewed-by: Konrad Dybcio <[email protected]>
Konrad
On Thu, 03 Aug 2023 16:27:33 +0530, Imran Shaik wrote:
> Update GCC clocks and add support for GDSCs for QDU1000 and QRU1000 SoCs.
>
> Changes since v4:
> - Updated the commit text as per the review comments
> - Split the gcc_ddrss_ecpri_gsi_clk and gcc_gpll1_out_even clock changes
>
> Changes since v3:
> - Split the gcc rcg ops changes as per the review comments
>
> [...]
Applied, thanks!
[1/8] dt-bindings: clock: Update GCC clocks for QDU1000 and QRU1000 SoCs
commit: df873243b2398a082d34a006bebe0e0ed7538f5c
[2/8] clk: qcom: gcc-qdu1000: Fix gcc_pcie_0_pipe_clk_src clock handling
commit: b311f5d3c4749259043a9a458a8db07915210142
[3/8] clk: qcom: gcc-qdu1000: Fix clkref clocks handling
commit: 2524dae5cd453ca39e8ba1b95c2755a8a2d94059
[4/8] clk: qcom: gcc-qdu1000: Register gcc_gpll1_out_even clock
commit: 06d71fa10f2e507444c6759328a6c19d38eab788
[5/8] clk: qcom: gcc-qdu1000: Add gcc_ddrss_ecpri_gsi_clk support
commit: 089aad8c769ca0710a66a2adc3e11d94b027b5f7
[6/8] clk: qcom: gcc-qdu1000: Add support for GDSCs
commit: 76346cf7089abd488fb3ad9753901b99baa3cafc
[7/8] clk: qcom: gcc-qdu1000: Update the SDCC clock RCG ops
commit: baa316580013ca100c23c8e92ac713f69f19fb08
[8/8] clk: qcom: gcc-qdu1000: Update the RCGs ops
commit: 1c16a7b794e15a2e843a1fbfd3ffaea46672f6e7
Best regards,
--
Bjorn Andersson <[email protected]>