2023-08-07 07:46:33

by Stanley Chang[昌育德]

Subject: [PATCH v1 RESEND] usb: dwc3: core: configure TX/RX threshold for DWC3_IP

In Synopsys's dwc3 data book:
To avoid underrun and overrun during the burst, in a high-latency bus
system (like USB), threshold and burst size control is provided through
GTXTHRCFG and GRXTHRCFG registers.

In Realtek DHC SoC, DWC3 USB 3.0 uses AHB system bus. When dwc3 is
connected with USB 2.5G Ethernet, there will be overrun problem.
Therefore, setting TX/RX thresholds can avoid this issue.

Signed-off-by: Stanley Chang <[email protected]>
---
drivers/usb/dwc3/core.c | 33 +++++++++++++++++++++++++++++++++
drivers/usb/dwc3/core.h | 5 +++++
2 files changed, 38 insertions(+)

diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index f6689b731718..a0a54e5c4ad9 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -1262,6 +1262,39 @@ static int dwc3_core_init(struct dwc3 *dwc)
}
}

+ if (DWC3_IP_IS(DWC3)) {
+ u8 rx_thr_num = dwc->rx_thr_num_pkt_prd;
+ u8 rx_maxburst = dwc->rx_max_burst_prd;
+ u8 tx_thr_num = dwc->tx_thr_num_pkt_prd;
+ u8 tx_maxburst = dwc->tx_max_burst_prd;
+
+ if (rx_thr_num && rx_maxburst) {
+ reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
+ reg |= DWC3_GRXTHRCFG_PKTCNTSEL;
+
+ reg &= ~DWC3_GRXTHRCFG_RXPKTCNT(~0);
+ reg |= DWC3_GRXTHRCFG_RXPKTCNT(rx_thr_num);
+
+ reg &= ~DWC3_GRXTHRCFG_MAXRXBURSTSIZE(~0);
+ reg |= DWC3_GRXTHRCFG_MAXRXBURSTSIZE(rx_maxburst);
+
+ dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
+ }
+
+ if (tx_thr_num && tx_maxburst) {
+ reg = dwc3_readl(dwc->regs, DWC3_GTXTHRCFG);
+ reg |= DWC3_GTXTHRCFG_PKTCNTSEL;
+
+ reg &= ~DWC3_GTXTHRCFG_TXPKTCNT(~0);
+ reg |= DWC3_GTXTHRCFG_TXPKTCNT(tx_thr_num);
+
+ reg &= ~DWC3_GTXTHRCFG_MAXTXBURSTSIZE(~0);
+ reg |= DWC3_GTXTHRCFG_MAXTXBURSTSIZE(tx_maxburst);
+
+ dwc3_writel(dwc->regs, DWC3_GTXTHRCFG, reg);
+ }
+ }
+
return 0;

err_power_off_phy:
diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index 8b1295e4dcdd..5480fcb59bcb 100644
--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
@@ -211,6 +211,11 @@
#define DWC3_GRXTHRCFG_RXPKTCNT(n) (((n) & 0xf) << 24)
#define DWC3_GRXTHRCFG_PKTCNTSEL BIT(29)

+/* Global TX Threshold Configuration Register */
+#define DWC3_GTXTHRCFG_MAXTXBURSTSIZE(n) (((n) & 0xff) << 16)
+#define DWC3_GTXTHRCFG_TXPKTCNT(n) (((n) & 0xf) << 24)
+#define DWC3_GTXTHRCFG_PKTCNTSEL BIT(29)
+
/* Global RX Threshold Configuration Register for DWC_usb31 only */
#define DWC31_GRXTHRCFG_MAXRXBURSTSIZE(n) (((n) & 0x1f) << 16)
#define DWC31_GRXTHRCFG_RXPKTCNT(n) (((n) & 0x1f) << 21)
--
2.34.1

2023-08-08 00:50:25

by Thinh Nguyen

Subject: Re: [PATCH v1 RESEND] usb: dwc3: core: configure TX/RX threshold for DWC3_IP

On Mon, Aug 07, 2023, Stanley Chang wrote:
> In Synopsys's dwc3 data book:
> To avoid underrun and overrun during the burst, in a high-latency bus
> system (like USB), threshold and burst size control is provided through
> GTXTHRCFG and GRXTHRCFG registers.
>
> In Realtek DHC SoC, DWC3 USB 3.0 uses AHB system bus. When dwc3 is
> connected with USB 2.5G Ethernet, there will be overrun problem.
> Therefore, setting TX/RX thresholds can avoid this issue.
>
> Signed-off-by: Stanley Chang <[email protected]>
> ---
> drivers/usb/dwc3/core.c | 33 +++++++++++++++++++++++++++++++++
> drivers/usb/dwc3/core.h | 5 +++++
> 2 files changed, 38 insertions(+)
>
> diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
> index f6689b731718..a0a54e5c4ad9 100644
> --- a/drivers/usb/dwc3/core.c
> +++ b/drivers/usb/dwc3/core.c
> @@ -1262,6 +1262,39 @@ static int dwc3_core_init(struct dwc3 *dwc)
> }
> }
>
> + if (DWC3_IP_IS(DWC3)) {
> + u8 rx_thr_num = dwc->rx_thr_num_pkt_prd;
> + u8 rx_maxburst = dwc->rx_max_burst_prd;
> + u8 tx_thr_num = dwc->tx_thr_num_pkt_prd;
> + u8 tx_maxburst = dwc->tx_max_burst_prd;

These are meant for periodic settings. You're overloading them for
non-periodic settings.

BR,
Thinh

> +
> + if (rx_thr_num && rx_maxburst) {
> + reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
> + reg |= DWC3_GRXTHRCFG_PKTCNTSEL;
> +
> + reg &= ~DWC3_GRXTHRCFG_RXPKTCNT(~0);
> + reg |= DWC3_GRXTHRCFG_RXPKTCNT(rx_thr_num);
> +
> + reg &= ~DWC3_GRXTHRCFG_MAXRXBURSTSIZE(~0);
> + reg |= DWC3_GRXTHRCFG_MAXRXBURSTSIZE(rx_maxburst);
> +
> + dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
> + }
> +
> + if (tx_thr_num && tx_maxburst) {
> + reg = dwc3_readl(dwc->regs, DWC3_GTXTHRCFG);
> + reg |= DWC3_GTXTHRCFG_PKTCNTSEL;
> +
> + reg &= ~DWC3_GTXTHRCFG_TXPKTCNT(~0);
> + reg |= DWC3_GTXTHRCFG_TXPKTCNT(tx_thr_num);
> +
> + reg &= ~DWC3_GTXTHRCFG_MAXTXBURSTSIZE(~0);
> + reg |= DWC3_GTXTHRCFG_MAXTXBURSTSIZE(tx_maxburst);
> +
> + dwc3_writel(dwc->regs, DWC3_GTXTHRCFG, reg);
> + }
> + }
> +
> return 0;
>
> err_power_off_phy:
> diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
> index 8b1295e4dcdd..5480fcb59bcb 100644
> --- a/drivers/usb/dwc3/core.h
> +++ b/drivers/usb/dwc3/core.h
> @@ -211,6 +211,11 @@
> #define DWC3_GRXTHRCFG_RXPKTCNT(n) (((n) & 0xf) << 24)
> #define DWC3_GRXTHRCFG_PKTCNTSEL BIT(29)
>
> +/* Global TX Threshold Configuration Register */
> +#define DWC3_GTXTHRCFG_MAXTXBURSTSIZE(n) (((n) & 0xff) << 16)
> +#define DWC3_GTXTHRCFG_TXPKTCNT(n) (((n) & 0xf) << 24)
> +#define DWC3_GTXTHRCFG_PKTCNTSEL BIT(29)
> +
> /* Global RX Threshold Configuration Register for DWC_usb31 only */
> #define DWC31_GRXTHRCFG_MAXRXBURSTSIZE(n) (((n) & 0x1f) << 16)
> #define DWC31_GRXTHRCFG_RXPKTCNT(n) (((n) & 0x1f) << 21)
> --
> 2.34.1
>

2023-08-08 03:01:48

by Stanley Chang[昌育德]

Subject: RE: [PATCH v1 RESEND] usb: dwc3: core: configure TX/RX threshold for DWC3_IP

Hi Thinh,

> > diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c index
> > f6689b731718..a0a54e5c4ad9 100644
> > --- a/drivers/usb/dwc3/core.c
> > +++ b/drivers/usb/dwc3/core.c
> > @@ -1262,6 +1262,39 @@ static int dwc3_core_init(struct dwc3 *dwc)
> > }
> > }
> >
> > + if (DWC3_IP_IS(DWC3)) {
> > + u8 rx_thr_num = dwc->rx_thr_num_pkt_prd;
> > + u8 rx_maxburst = dwc->rx_max_burst_prd;
> > + u8 tx_thr_num = dwc->tx_thr_num_pkt_prd;
> > + u8 tx_maxburst = dwc->tx_max_burst_prd;
>
> These are meant for periodic settings. You're overloading them for
> non-periodic settings.
>
I will add new property for non-periodic settings.

Thanks,
Stanley