Add bootph-pre-ram property for all the nodes used in SPL stage,
for syncing it later to u-boot j784s4 dts.
Signed-off-by: Apurva Nandan <[email protected]>
---
arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi
index 657fb1d72512..521d3cfd10c4 100644
--- a/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi
@@ -6,7 +6,9 @@
*/
&cbass_mcu_wakeup {
+ bootph-pre-ram;
sms: system-controller@44083000 {
+ bootph-pre-ram;
compatible = "ti,k2g-sci";
ti,host-id = <12>;
@@ -19,22 +21,26 @@ sms: system-controller@44083000 {
reg = <0x00 0x44083000 0x00 0x1000>;
k3_pds: power-controller {
+ bootph-pre-ram;
compatible = "ti,sci-pm-domain";
#power-domain-cells = <2>;
};
k3_clks: clock-controller {
+ bootph-pre-ram;
compatible = "ti,k2g-sci-clk";
#clock-cells = <2>;
};
k3_reset: reset-controller {
+ bootph-pre-ram;
compatible = "ti,sci-reset";
#reset-cells = <2>;
};
};
chipid@43000014 {
+ bootph-pre-ram;
compatible = "ti,am654-chipid";
reg = <0x00 0x43000014 0x00 0x4>;
};
@@ -161,6 +167,7 @@ mcu_timer0: timer@40400000 {
};
mcu_timer1: timer@40410000 {
+ bootph-pre-ram;
compatible = "ti,am654-timer";
reg = <0x00 0x40410000 0x00 0x400>;
interrupts = <GIC_SPI 817 IRQ_TYPE_LEVEL_HIGH>;
@@ -442,6 +449,7 @@ mcu_spi2: spi@40320000 {
};
mcu_navss: bus@28380000{
+ bootph-pre-ram;
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
@@ -451,6 +459,7 @@ mcu_navss: bus@28380000{
dma-ranges;
mcu_ringacc: ringacc@2b800000 {
+ bootph-pre-ram;
compatible = "ti,am654-navss-ringacc";
reg = <0x00 0x2b800000 0x00 0x400000>,
<0x00 0x2b000000 0x00 0x400000>,
@@ -465,6 +474,7 @@ mcu_ringacc: ringacc@2b800000 {
};
mcu_udmap: dma-controller@285c0000 {
+ bootph-pre-ram;
compatible = "ti,j721e-navss-mcu-udmap";
reg = <0x00 0x285c0000 0x00 0x100>,
<0x00 0x2a800000 0x00 0x40000>,
--
2.34.1